pci interface 기술-io system 소개

PCI Interface PCI Interface 1

PCI Interface PCI Interface

Part I IO System


OverviewOverview99 Computer IO System Computer IO System

9 PCI

9 PCI-X

9 PCI Express


PC Platform EvolutionPC Platform Evolution

Productivity PCProductivity PC Multimedia PCMultimedia PC Connected PCConnected PC Extended PCExtended PC


Productivity PCProductivity PC9 PC9 Office automation9 Word processor (HWP, word, )

Productivity PCProductivity PC


Multimedia PC (MPC)Multimedia PC (MPC)9 1990 IBM PC

9 MPC3 CPU (75MHz) 8MB 540MB CD-ROM 4 MPEG (MPEG )

Sound card

Multimedia PCMultimedia PC


Connected PCConnected PC9 Internet 10

9

9 2002 8000 Connected PCConnected PC


Extended PCExtended PC9 HDTV, , PDA, , DVD, , .

9 PC

Extended PCExtended PC


Increasing Bandwidth DemandIncreasing Bandwidth Demand

memory bandwidth requirementsmemory bandwidth requirements

100MB/sec

500MB/sec

3GB/sec

EDO DRAM

SDRAM

Main Memory BW

Time

RDRAM/DDR

processor performance will continue processor performance will continue to follow to follow MooresMoores lawlaw

286286 Intel386 CPUIntel386 CPU

Intel486CPUIntel486CPU

80888088

8585 9090 95958080

Relative processor Relative processor PerformancePerformance

PentiumPentium II II Processor Processor

Source: IntelSource: Intel

IntelDX2IntelDX2--5050

0000 0505

PentiumPentium III III Processor Processor

PentiumPentium 4 4 Processor Processor

PentiumPentiumProcessor Processor

PentiumPentium ProProProcessor Processor

processor performance will continue processor performance will continue to follow to follow MooresMoores lawlaw

286286 Intel386 CPUIntel386 CPU

Intel486CPUIntel486CPU

80888088

8585 9090 95958080

Relative processor Relative processor PerformancePerformance

PentiumPentium II II Processor Processor

Source: IntelSource: Intel

IntelDX2IntelDX2--5050

0000 0505

PentiumPentium III III Processor Processor

PentiumPentium 4 4 Processor Processor

PentiumPentiumProcessor Processor

PentiumPentium ProProProcessor Processor


Computer IO System EvolutionComputer IO System Evolution

Will be new Industry Will be new Industry Standard Standard

InterconnectInterconnect

ISAEISAMCAVESA

PCI PCI-XHL

Others

AGP

1980s 1990s

PCI Express

2000s

1 IO(1GIO)

2 IO(2GIO)

3 IO(3GIO)


Motivation Motivation -- PCIPCI9 1992 PCI Local Bus

9 Graphic Oriented OS(windows, OS/2) High bandwidth IO (full motion video, SCSI, LAN, etc)PC

9 IO system bottleneck


Motivation Motivation PCI ExpressPCI Express9 Connected PC PC CPU: GHz CPU , 10GHz CPU

High speed memory Giga bit LAN, 1394

9 IO system bottleneck


TodayTodays Platforms Platform

Local I/OLocal I/O

USB1.1USB1.1

GraphicsGraphics

I/O Bridge

I/O Bridge

Memory Bridge

Processor System BusProcessor System Bus

ATAATA

AGPAGP

HubLinkHubLink or othersor others

PCIPCI

HDDHDD

MemoryMemory

CPU


IntelIntels Platforms Platform

Pentium-4

82845MCH

82801BAICH2

PC133DDR

AGP4X

PCI 2.233MHz/32-bit

LAN

FSB(400 MHz)

USB1.1

ATA100

850(E)

Hub Interface

AC97

Pentium-4

82850EMCH

82801BAICH2

300(400)RDRAM

AGP4X

PCI 2.233MHz/32-bit

LAN

FSB(400(533) MHz)

USB1.1

ATA100

Hub Interface

AC97

845


AMDAMD s Platforms Platform

Athlon

751(System Controller)

756(PeripheralBus Controller)

PC100SDRAM

AGP2X

PCI 2.233MHz/32-bit

ISA

KeyboardPS/2 Mouse

FSB(200MHz)

USB1.0

750

ATA66

Athlon

762(System Controller)

766(768)(PeripheralBus Controller)

PC133DDR

AGP4X

PCI 2.233(66)MHz32/64-bit

AC97

FSB(266MHz)

USB1.1

760MP(MPX)

ATA100

Athlon


OverviewOverview9 Computer IO System

99 PCI PCI

9 PCI-X

9 PCI Express


PCI OverviewPCI Overview9 1992 PCI Local Bus

9 10 PC IO system

9 PC , , , , ,

9 10 ISA 10 PCI PCI Express


Revision History 1Revision History 19 Revision 1.0 92 6 22 Original Issue

9 Revision 2.0 93 4 30 Incorporated connector and expansion board specification


Revision History 2Revision History 29 Revision 2.1 95 6 1 Incorporated clarifications and added 66MHz chapter

9 Revision 2.2 98 12 18 Incorporated ECN(Engineering Change Notices) and improved readability


Revision History 3Revision History 39 Revision 2.3 02 3 29 Incorporated ECN(Engineering Change Notices), errata, and deleted 5V only keyed add-in cards


Option 1 Option 1 PMPM9 PCI Bus Power Management Interface Specification

9 Revision 1.0 97 6 30 original issue

9 Revision 1.1 98 12 18 integrated the 3.3Vaux ECR


Option 2 Option 2 -- HPHP9 PCI Hot-Plug Specification

9 Revision 1.0 97 10 6 Original issue

9 Revision 1.1 01 6 20 Add PCI 2.2, PCI power management, PCI-X and SMBus


Option 3 Option 3 PCIPCI--XX9 PCI-X Addendum to the PCI Local Bus Specification

9 Revision 1.0 99 9 22 Original issue

9 Revision 1.0a 00 7 24 Clarification and typographical corrections


Other FeaturesOther Features9 Mini PCI Specification

9 PCI Bios Specification

9 PCI Mobile Design Guide

9 PCI-to-PCI Bridge Specification


Goal of PCI Local Bus 1Goal of PCI Local Bus 19 Establishing and industry standard

9 High performance, Low cost Price-performance points in todays systems

9 Accommodates future system requirements

9 Be applicable across multiple platform and architecture


Goal of PCI Local Bus 2Goal of PCI Local Bus 2


PCI System Block DiagramPCI System Block Diagram


Basic Bus TransactionBasic Bus Transaction

InitiatorInitiator TargetTarget

AD[31:0], C/BE#[3:0]FRAME#IRDY#TRDY#

DEVSEL#


Read TransactionRead Transaction


Write TransactionWrite Transaction



9 PCI

99 PCIPCI--X X

9 PCI Express


PCIPCI--X OverviewX Overview9 1999 , 2000 7 revision 1.0a

9 1GB/s 133MHz, 64bit interface

9 Backward compatible Operate at conventional PCI frequencies and modes when installed in conventional systems


PCIPCI--XX 9 Bandwidth requirements of peripheral devices have steadily grown Devices are appeared to support 64bit bus and 66MHz (Peak performance 0.5GB/s)

9 Fast I/O technologies are required Gigabit Ethernet, Ultra 3 SCSI, and Fibre Channel


PCIPCI--X X 9 133MHz

9 Split transaction

9 No wait cycle except initial data phase

9 Attribute phase 2.2 address phase data phase


PCI 2.2PCI 2.2 PCIPCI--XX: 2.2: 2.2


PCI 2.2PCI 2.2 PCIPCI--XX: X: X


PCIPCI--X Read TransactionX Read Transaction


PCIPCI--X Write TransactionX Write Transaction


Source SamplingSource Sampling


TargetTargets View of the PCI Buss View of the PCI Bus


InitiatorInitiators View of the PCI Buss View of the PCI Bus


Split TransactionSplit Transaction



9 PCI

9 PCI-X

99 PCI Express PCI Express


PCI Express OverviewPCI Express Overview9 2002 4 revision 1.09 Point-to-point differential interconnect9 2.5Gbps/port/dir 2.5Gbps/port/dir x 16port = 40Gbps

9 PCI software mode compatible 100% OS and driver level compatible

9 Layered architecture Physical layer, data link layer, transaction layer


PCI Express MotivationPCI Express Motivation9 Practical limit of traditional bus based IO system Strict skew requirements between parallel signals Stringent routing rules Lake of scaling of frequency and voltage

9 Not cost effective


Goals for PCI ExpressGoals for PCI Express9 Broadly adapted industry solution Spanning multiple market segment: Clients(Desktops and Mobile), Servers(Standards and Enterprise), Embedded and Communication devices)

Industry leading performance, and price/performance


Requirements for the Goals Requirements for the Goals 9 Low cost, high volume Cost at or below PCI cost structure at system level

9 Support multiple market segment Unifying I/O interconnect technology for Desktop, Mobile, Server, Communication platform, workstation and Embedded system


Requirements for the Goals Requirements for the Goals 9 PCI Compatible Software Model Cost at or below PCI cost structure at system level

9 Advanced Features Power management, QoS, Hot Attach/Detach

9 Performance Scalable performance High bandwidth/pin, low overhead and low latency


Client Platform ExampleClient Platform Example

GbEthernet*

GbEthernet*

Mobile DockingMobile Docking

Add insAdd ins

USB2.0USB2.0

GraphicsGraphics MemoryBridge

MemoryBridge

I/OBridge

I/OBridge

Serial ATASerial ATA

3GIO3GIO

3GIO3GIO

PCIPCI

HDDHDD

MemoryMemory

SwitchSwitch

3GIO3GIO

3GIO3GIO

Local I/OLocal I/O3GIO3GIO

CPUCPU


Server Platform ExampleServer Platform Example

PCI

SATALPCUSB2

PCI-X

BridgeBridgeIBAIBA

ChipsetChipset

CPUCPU CPUCPU

GbEGbE

BridgeBridge

MemoryMemory

3GIO3GIO

InfiniBand*InfiniBand*

3GIO3GIO3GIO3GIO

InfiniBand*Switched

Fabric

InfiniBand*InfiniBand*SwitchedSwitched

FabricFabric


Communications ExampleCommunications ExampleCPU CPU

ChipsetChipsetGbE

Switch

MemoryMemory

MemoryMemory

3GIO x 83GIO x 8

3GIO x 83GIO x 8

3GIO3GIO

PCIBridge

PCIBridge

LineLineCardCard

LineLineCardCard

LineLineCardCard

LineLineCardCard

LineLineCardCard

3GIO3GIO


Advanced PeerAdvanced Peer--toto--Peer CommunicationPeer Communication


3GIO Architecture3GIO Architecture

Layered architecture enables future expansionLayered architecture enables future expansion

2.5+ Gb/s2.5+ Gb/s

PCI PnP Model (init, enum, config)PCI PnP Model (init, enum, config)

PCI Software/Driver ModelPCI Software/Driver Model

Data IntegrityData Integrity

Config/OS

S/W

Transaction

Data Link

PacketPacket--based Protocolbased Protocol

Physical(electrical

Mechanical)

Point to point, serial, differential,Point to point, serial, differential,hothot--plug, interplug, inter--op form factorsop form factors

>> 2.5Gb/s/port/direction2.5Gb/s/port/direction

Future speeds & encoding techniques only impact the Physical layer

No OS impactNo OS impact


Packet Flow Through the LayersPacket Flow Through the Layers

Packets are transmitted seriallyPackets are transmitted serially

Transaction LayerTransaction Layer

Data Link LayerData Link Layer

Physical LayerPhysical Layer

DataHeader CRC FramePacket

SequenceNumber

Frame


Physical LayerPhysical Layer9 Point-to-Point differential interconnect9 Low voltage signaling9 Two unidirectional links9 Bit rate: 2.5Gbps9 Embedded clock signaling9 Interface width: 1x, 2x, 4x, 8x, 12x, 16x, 32x

Clock Clock

D

e

v

i

c

e

A

Device B

Selectable Width


Physical LayerPhysical LayerByte StreamByte Stream

{conceptual}{conceptual}Byte 0Byte 1Byte 2Byte 3Byte 4Byte 5

. . .

Byte 4Byte 0

Byte 5Byte 1

Byte 6Byte 2

Byte 7Byte 3

Lane 0Lane 0

8b/10bP > S

Lane 1Lane 1

8b/10bP > S

Lane 2Lane 2

8b/10bP > S

Lane 3Lane 3

8b/10bP > S

Lane 0Lane 0

8b/10bP > S

Byte 2Byte 3

Byte 1Byte 0

Byte 0Byte 1Byte 2Byte 3Byte 4Byte 5

. . .

BandBandwidth is selectable width is selectable usingusingmultiple lanesmultiple lanes


Data Link LayerData Link Layer9 Basic responsibilities are error detection and error correction CRC generation Error checking TLP acknowledgment and retry messages


Transaction LayerTransaction Layer9 Primary responsibility is the assembly and deassembly of transaction layer packets(TLP)

9 Every request packet requiring a response packet is implemented as a split transaction.


3GIO Performance3GIO Performance

Best Bandwidth/Pin => Best ValueBest Bandwidth/Pin => Best Value

B

W

/

P

i

n

M

B

/

s

B

W

/

P

i

n

M

B

/

s

0.00

20.00

40.00

60.00

80.00

100.00

BW/pin 1.58 7.09 9.85 11.57 26.60 100

PCI PCI-X AGP4X HL1 HL2 3GIO


Mechanical Concept 1Mechanical Concept 1

Existing PCI Connector3GIO Connector

LowLow bandwidth conceptbandwidth concept



Existing PCI Connector

3GIO Connector

HighHigh bandwidth conceptbandwidth concept



Short cable concept for desktop/mobileShort cable concept for desktop/mobile



Small form factor conceptSmall form factor concept

Todays Add-in Cardwith large connector

Example: Mini-3GIO BTO/CTO Add-in Card with wired functionality


End of Part IEnd of Part I

pci interface 기술-io system 소개

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