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978-1-4799-6540-3/14/$31.00 ©2014 IEEE Phase Noise Measurement Techniques Using Delta-Sigma TDC Yusuke Osawa, Daiki Hirabayashi, Naohiro Harigai, Haruo Kobayashi, Kiichi Niitsu†, Osamu Kobayashi‡ Division of Electronics and Informatics, Gunma University, Kiryu 376-8515 Japan, [email protected] Nagoya University Semiconductor Technology Academic Research Center Abstract - This paper describes two techniques for measuring phase noise of a clock using a delta-sigma time-to-digital converter (TDC). One technique uses a reference signal (which has only very small phase noise), and the other does not use a reference signal. Both proposed techniques can be implemented with relatively simple circuitry, due to the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be increased by using longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. Costly high-performance spectrum analyzers which average several-time phase measurement results over a long measurement time (about 10s order), are not needed for phase noise measurement with the proposed technique. The other technique, which differs in that it uses a self-referenced clock rather than a reference signal, has potential wide applications. Keywords : Phase Noise Measurement, Time-to-Digital Converter, Delta-Sigma Modulation, PLL Testing I. INTRODUCTION In recent years, thanks to the advancement of semiconductor manufacturing processes, the semiconductor fabrication cost per transistor has decreased, while testing costs may increase if testing-related technologies are not improved; hence much attention is being paid to low-cost, high-quality testing technology [1]. We here consider how to perform low-cost high-quality phase noise testing of phase locked loop (PLL) circuits without using a spectrum analyzer. Phase noise is one of the most important performance metrics of PLL circuits [1-7], and to measure it directly [3] requires a spectrum analyzer with long measurement time (say, 10 seconds). Hence industry is looking for a technology breakthrough to provide low-cost high-quality testing. Jitter and phase noise on-chip testing circuits have already been proposed in [5, 6]. However, the on-chip jitter measurement circuit [5] can measure the rms value of jitter (phase noise), but not phase noise versus frequency. The technique in [7] uses a normal flash TDC which does not have fine time resolution, so precision phase noise measurement is not possible. This paper proposes two techniques for measuring phase noise of a clock using a delta-sigma TDC [8]. One technique uses a reference signal (which has only very small phase noise) [9]. The other is a new technique that doesn’t use a reference signal, and has potential wide applications. The delta-sigma TDC is useful for phase noise measurement because the clock under test (CUT) is a repetitive signal, and the time resolution with CUT and a reference clock can be increased by using longer measurement time in the delta-sigma TDC. We can also obtain the frequency characteristics of the phase noise by applying FFT to the TDC outputs. We show the validity of the proposed methods with theoretical analysis and MATLAB simulations. The proposed techniques can realize low-cost phase noise testing without requiring both an expensive spectrum analyzer and long testing time. This paper consists of the following: Section 2 explains the delta-sigma TDC, Section 3 describes the proposed phase noise measurement technique with a reference clock, and Section 4 discusses the simulation results. Section 5 describes the proposed phase noise measurement technique without a reference clock and Section 6 provides conclusions. II. DELTA-SIGMA TDC Fig.1 shows a delta-sigma TDC architecture [8] consisting of a delay element, three multiplexers, an analog integrator (or charge pump circuit), and a comparator. Its inputs are two clock signals CLK1 and CLK2 with the same frequency, and it measures the time difference ΔT of their clock timing edges. In this design, the TDC output as the time difference is positive when the CLK1 rising edge is earlier than CLK2, and it is negative when the CLK1 edge is later. The number of 1's of the comparator output for a given time is proportional to the time difference between CLK1 and CLK2 when CLK1 is earlier. Similarly the number of 0's is proportional to their time difference when CLK2 is earlier.

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Page 1: Phase Noise Measurement Techniques Using Delta-Sigma …kobaweb/news/pdf/2014/2014-09osawa.pdf · 978-1-4799-6540-3/14/$31.00 ©2014 IEEE (a) Proposed circuit block diagram (b) Matlab

978-1-4799-6540-3/14/$31.00 ©2014 IEEE

Phase Noise Measurement Techniques Using Delta-Sigma TDC Yusuke Osawa, Daiki Hirabayashi, Naohiro Harigai, Haruo Kobayashi, Kiichi Niitsu†, Osamu Kobayashi‡

Division of Electronics and Informatics, Gunma University, Kiryu 376-8515 Japan, [email protected]

†Nagoya University ‡ Semiconductor Technology Academic Research Center

Abstract - This paper describes two techniques for measuring phase noise of a clock using a delta-sigma time-to-digital converter (TDC). One technique uses a reference signal (which has only very small phase noise), and the other does not use a reference signal. Both proposed techniques can be implemented with relatively simple circuitry, due to the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be increased by using longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. Costly high-performance spectrum analyzers which average several-time phase measurement results over a long measurement time (about 10s order), are not needed for phase noise measurement with the proposed technique. The other technique, which differs in that it uses a self-referenced clock rather than a reference signal, has potential wide applications.

Keywords : Phase Noise Measurement, Time-to-Digital Converter, Delta-Sigma Modulation, PLL Testing

I. INTRODUCTION

In recent years, thanks to the advancement of semiconductor manufacturing processes, the semiconductor fabrication cost per transistor has decreased, while testing costs may increase if testing-related technologies are not improved; hence much attention is being paid to low-cost, high-quality testing technology [1].

We here consider how to perform low-cost high-quality phase noise testing of phase locked loop (PLL) circuits without using a spectrum analyzer. Phase noise is one of the most important performance metrics of PLL circuits [1-7], and to measure it directly [3] requires a spectrum analyzer with long measurement time (say, 10 seconds). Hence industry is looking for a technology breakthrough to provide low-cost high-quality testing.

Jitter and phase noise on-chip testing circuits have already been proposed in [5, 6]. However, the on-chip jitter measurement circuit [5] can measure the rms value of jitter (phase noise), but not phase noise versus frequency. The

technique in [7] uses a normal flash TDC which does not have fine time resolution, so precision phase noise measurement is not possible.

This paper proposes two techniques for measuring phase noise of a clock using a delta-sigma TDC [8]. One technique uses a reference signal (which has only very small phase noise) [9]. The other is a new technique that doesn’t use a reference signal, and has potential wide applications.

The delta-sigma TDC is useful for phase noise measurement because the clock under test (CUT) is a repetitive signal, and the time resolution with CUT and a reference clock can be increased by using longer measurement time in the delta-sigma TDC. We can also obtain the frequency characteristics of the phase noise by applying FFT to the TDC outputs.

We show the validity of the proposed methods with theoretical analysis and MATLAB simulations. The proposed techniques can realize low-cost phase noise testing without requiring both an expensive spectrum analyzer and long testing time.

This paper consists of the following: Section 2 explains the delta-sigma TDC, Section 3 describes the proposed phase noise measurement technique with a reference clock, and Section 4 discusses the simulation results. Section 5 describes the proposed phase noise measurement technique without a reference clock and Section 6 provides conclusions.

II. DELTA-SIGMA TDC Fig.1 shows a delta-sigma TDC architecture [8]

consisting of a delay element, three multiplexers, an analog integrator (or charge pump circuit), and a comparator. Its inputs are two clock signals CLK1 and CLK2 with the same frequency, and it measures the time difference ΔT of their clock timing edges. In this design, the TDC output as the time difference is positive when the CLK1 rising edge is earlier than CLK2, and it is negative when the CLK1 edge is later. The number of 1's of the comparator output for a given time is proportional to the time difference between CLK1 and CLK2 when CLK1 is earlier. Similarly the number of 0's is proportional to their time difference when CLK2 is earlier.

Page 2: Phase Noise Measurement Techniques Using Delta-Sigma …kobaweb/news/pdf/2014/2014-09osawa.pdf · 978-1-4799-6540-3/14/$31.00 ©2014 IEEE (a) Proposed circuit block diagram (b) Matlab

978-1-4799-6540-3/14/$31.00 ©2014 IEEE

(a) Proposed circuit block diagram

(b) Matlab simulation model diagra

Fig. 1. Block diagram of a delta-sigma TDC.

Its operation is as follows (Fig.2): (i) When the comparator output is "1", CLτ, while CLK2 is not delayed. When the cis "0", CLK1 is not delayed, while CLK2

(ii) The clock signals acquired as a resuCLK1a and CLK2a respectively.

(iii) The mask signal (generated in "Timinthe same as CLK1a when CLK1a coCLK2a; otherwise it is the same as CLK2

(iii) CLK1b is the logical AND of the CLK1a, while CLK2b is the logical ANsignal and CLK2a.

(iv) We generate the signal CLKin represbetween CLK1b and CLK2b and convesignal by subtracting CLK1b from CLKdomain, and feed it to the integrator INTout.

(v) The comparator examines (at the risiwhich is delayed by Td from the fallinsignal) whether the integrator output INT"0" or not. Its output Dout is the delta-sthat is fed-back to the multiplexers. Fig.3 shows the delta-sigma measur

the time difference Δ T of the input < τ . In other words, τ determines thnot the time resolution.

E

m.

am.

LK1 is delayed by comparator output is delayed by τ.

ult are defined as

ng Generator") is omes earlier than a. Mask signal and ND of the Mask

enting time delay ert it to a voltage K2b in the analog

whose output is

ing edge of CLK ng edge of Mask Tout is larger than sigma TDC signal

rement range of clock −τ <Δ T he input range,

Notice that the time resmeasurement with the delta_

The time resolution is determand the number of obtained Thence the longer the measureand then the finer the time reintegrator ADC). This enables to phase noise measurement.

Fig.3. Input-output characteristics of th

III. PROPOSE

MEASUREMENT USIWITH REFER

A. Principle of Phase NoisFig.4 shows the first

measurement principle us(with a reference clock)

Fig. 2. Timing chart of the delt

(in case Dout=1.) olution of the phase noise a-sigma TDC is given by 2

mined by the delay element τ TDC output data points NDATA; ement time, the larger NDATA , esolution (this is similar to an

to apply the delta-sigma TDC

he delta-sigma TDC.

ED PHASE NOISE ING DELTA-SIGMA TDC RENCE SIGNAL e Measurement t proposed phase noise ing the delta-sigma TDC [9]. We assume here that

a-sigma TDC in Fig.1

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978-1-4799-6540-3/14/$31.00 ©2014 IEEE

CLK1 is the clock under test and it mphase noise, while CLK2 is a referencphase noise, and also that the frequeand CLK2 are the same.

Suppose that CLK1 has no phase nrising edge timing difference betweCLK2 causes only a DC componentspectrum of the delta-sigma TDC, becdifference is always constant.

On the other hand, when there’s finin the input clock CLK1, the time diffCLK1 and CLK2 changes at each clthese fluctuation effects appear spectrum of the delta-sigma TDC; phase noise can be measured.

Note that since noise shaping delta-sigma modulation, the compcomparator quantization noise floorfrequencies increase. However, in mphase noise frequency characteristiccarrier frequency are important. The below shows the spectrum obtained sigma-delta TDC output. Phase noicarrier (CLK1) frequency; shaped quais at higher frequencies, and so doesaffect the accuracy of phase noise mea

Fig. 4. Principle of the proposed phase noise musing a delta-sigma TDC with a reference cloc B. Analytical Discussion

Fig.5 shows the proposed measurement system using a delta-sidelta-sigma TDC measures the tibetween CUT (CLK1 with phase reference clock REF (CLK2 withouThe phase noise frequency characteristics o

E

may have some ce clock without encies of CLK1

noise. Then the een CLK1 and t in the output

cause the timing

nite phase noise ference between lock cycle, and in the output based on this,

is applied by onents of the r rise as their

many cases, the cs close to the x-axis of Fig.4 by FFT of the

ise is near the antization noise s not appear to asurement.

measurement ck.

phase noise igma TDC. The ime difference

noise) and a t phase noise). of CLK1 from the

carrier (clock) frequency canTDC output. Now we derive phase noise.

Suppose that CLK1 is approxCUT sin 2πHere φ(t) is phase noise exprem-th zero-crossing rising edgewe have 2π 2π

Here τ(m) is the m-th zero-crconsider the case that τ(m) is aangular frequency of · · sin ·

Then we have the phase noise 2π · sinThus its power at is giv12 2π

Eq. (6) shows that the phase away from the CUT (carrier) fr Next, let us consider the casby superposition of several sin· · sin ·Then we have the phase noise 2 · sinThus its power at is giv12 2

We see that the phase noise pFFT of the delta-sigma TDC ou C. Phase Noise Measureme

We have confirmed the emethod with a reference cloFig.5 shows the circuit confwhere the frequency of the inpto 1MHz. In MATLAB simulathe input clock CUT (CLK1) iTime Delay, which is one ofCLK2 has no phase noise. Delset to 200ns, and the number we use is 4,096. TableⅠshowhave conducted simulations single sine wave and several su

n be obtained by FFT of the analytical expressions for the

ximated by a sinusoidal signal: ………….. (1)

essed in time domain. Let the e timing function be τ(m), and

2π …… (2) …… (3)

rossing timing, and let us a sinusoidal input with an

………….. (4) in time domain · ……….. (5) ven by

…………..

(6)

noise power spectrum at frequency. se that phase variation is given

ne waves. Let τ(m) be

…………..

(7)

in time domain · ………..

(8)

ven by …………..

(9)

power spectrum is obtained by utputs.

ent Simulation effectiveness of the proposed ock by MATLAB simulation. figuration for the simulation, put clocks REF and CUT is set ation, exact phase variation of s applied using VTD (Variable f MATLAB functions), while ay τ in the delta-sigma TDC is of the delta-sigma TDC data

ws simulation conditions. We for phase variation both for

uperposed sine waves.

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978-1-4799-6540-3/14/$31.00 ©2014 IEEE

1) In Case of Single Sine Wave Phase FluWe have conducted MATLAB simulat

variation of single sine waves of 10kHz anda) Phase variation of 10kHz

Fig.6 shows the FFT analysis results oTDC output data without and with phase neq.(4), /(2π)=10kHz). We see in Fig.6component appears at 10kHz.

b) Phase variation of 50kHz Fig.7 shows the FFT analysis results o

TDC output data with phase noise of 50/(2π)=50kHz). We see in Fig.7 th

component appears at 50kHz. 2) In Case of Superposition of Two SineFluctuation

We have also performed MATLAB simulfluctuation of CUT when two sine waves (in eq.(8), N=2, /(2π)=10kHz, /(2πshows simulation results, and we see tcomponents appear at the frequencies of 1Consequently, even if the CUT containfluctuation components, the proposed mettheir frequency components.

We have compared the simulation results and analytical results in Section 3-2, and foagree well.

IV. Proposed phase noise measure

delta-sigma TDC without referA. Principle of Phase Noise Measurem

Fig.9 shows the second proposedmeasurement principle using the de(without a reference clock). CLK is th

Fig. 5. Phase noise measurement system usingTDC and zero-cross variation function τ(m).

E

uctuation tions with phase d 50kHz.

f the delta-sigma noise of 10kHz (in 6 that the spurious

f the delta-sigma 0kHz (in eq.(4), hat the spurious

e Waves of Phase

ation of the phase are superimposed π)=50kHz). Fig.8 that the spurious 0kHz and 50kHz.

ns multiple phase thod can measure

in this section ound that both

ement using rence signal

ment d phase noise

elta-sigma TDC he clock under

TABLEⅠ.SIMULAT

Fig. 6. Power spectrum of the d(MATLAB simulation)

Fig. 7. Power spectrum of the d(MATLAB simulation).

Fig. 8. Power spectrum of the d(MATLAB simulation).

-140-120-100-80-60-40-200

0.1 1

Without Phase Noise

FrequPo

wer

[dB

]

g the delta-sigma

TION CONDITIONS

delta-sigma TDC output

delta-sigma TDC output

delta-sigma TDC output.

10 100

uency [kHz]

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978-1-4799-6540-3/14/$31.00 ©2014 IEEE

test, which may have some phase ndelayed by T. Here T is the clock prequired to be approximately one (exinteger is not necessary) and hence easy to implement.

Fig.9 Proposed phase noise measurement usinTDC without reference clock.

The proposed system can measure CLK (Fig.10). We can obtain the phaspectrum by multiplying the power speriod jitter obtained by FFT of the deoutput by 1/ (see Fig.10 [1] and F

Fig. 10 Explanation of period jitter [1].

Fig.11 Power spectrum of period jitter and ph

B. Analytical Discussion We derive analytical expressions for th

Fig.9. Suppose that CLK is approximatedsignal. CUT sin 2π ……Here φ(t) is phase noise expressed in timem-th zero-crossing rising edge timing funcwe have 2π 2π 2π .

Here τ(m) is the m-th zero-crossing timingconsider the case that τ(m) is a sinusoidal iangular frequency of .

E

noise, and it is eriod, and is

xactly one or an it is relatively

g delta-sigma

period jitter of ase noise power spectrum of the elta-sigma TDC ig. 11).

ase noise [1].

he phase noise in d by a sinusoidal

……….. (10) e domain. Let the ction be τ(m), and

…… (11) …… (12)

g, and let us input with an

· · sin ·The delta-sigma TDC in Fi1= · sin 1 s2 · sin /2 cosHere 1 T is DC comp2 sin /2 cos ( (m+1/2)Tat and its corresponding p12 2π 2 sinThen we have the phase no2 sin /2Assumption: is much This is reasonable in mawireless communications,frequency is very high, bonly to the phase noise coscillator frequency. When

we have /2 <<1.Then

and the phase noise power is

We have similar equations whesuperposition of several sinusoRemark: (i)The requirement for

one; It is easy to implemT is small. Other self-r

noise measurement methoexactness or an integerwhich is difficult to imaddition in T is relative

(ii) The deviation of frDC component in the freqthe delta-sigma TDC outp

(iii) Note that since noisdelta-sigma modulation, comparator quantization frequencies increase. Hobtain the phase noismultiplying the power spobtained by FFT of the d1/ ; hence noise-shaphigh-frequencies is also s

C. Phase Noise MeasuremeWe have confirmed the

………….. (13) ig.9 measures the time 1 T sin · 1 T

1/2 1 T …..(14)

onent. T) is the frequency component ower of at is /2

……..

(16)

oise power at as follows:

…………..

(17)

lower than2π . any applications, such as , because the oscillator ut attention must be paid haracteristics close to the the above assumption is valid,

we have 2sin

…………..

(18)

en the phase noise results from oidal signals.

is to be approximately ment, and noise addition in

eference clock jitter/phase ods such as in [5,6] require greater than one for , mplement, and the noise ely large. rom one only appears as a quency domain after FFT of put. se shaping is applied by

the components of the noise floor rise as their

owever in this case we se power spectrum by ectrum of the period jitter

delta-sigma TDC output by ed quantization noise at uppressed.

ent Simulation effectiveness of the second

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978-1-4799-6540-3/14/$31.00 ©2014 IEEE

proposed method (without a reference closimulation in Fig.9, where the input clock f1MHz. Figs.12 (a), (b), (c) show the simulthe same amount of phase variation at 1100kHz respectively; we see that as the phase noise increases, the corresponding Tspectrum increases. Fig. 13 shows simultheoretical analysis in eq.(17) for the phascorresponding TDC output power, and wagree well.

V. Conclusion We have proposed two techniques—wit

reference clock—for measuring phase noisa delta-sigma TDC, and we have verified tby MATLAB simulations. We have also dformula for phase noise measurement wmethod, which agree the simulation reproposed techniques enable low-cost hinoise measurement without requiring spectrum analyzers. Some concluding rema(i) Measurement of oscillator phase noise d

difficult with a spectrum analyzer becaeffect appears at the frequency close tfrequency. However the proposed memeasure it accurately

(ii) A multi-bit sigma-delta TDC wtechniques can further reduce the phase notime [8].

Acknowledgements We would likYamaguchi, M.Tsuji, M. Watanabe, R. ShS. Umeda, T. Matsuura, N. Takai, T. Araand K. Wilkinson for valuable discussionskind support of this research.

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