pixel technologies for the ilc material budget, forward σrφ≈σrz≈5...
TRANSCRIPT
![Page 1: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/1.jpg)
Pixel Technologies for the ILCPixel Technologies for the ILC
Marcel StanitzkiMarcel StanitzkiSTFC-Rutherford Appleton LaboratorySTFC-Rutherford Appleton Laboratory
Generic future Colliders of any shape
![Page 2: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/2.jpg)
Marcel Stanitzki2
In the beginning ...
SLD's VXD3 (1996)
− 307 Million channels
− 20 µm pixels
The Grandfather of all LC pixel detectors
Still provides valuable “lessons learned” from SLC
Starting point for ILC pixel R&D
![Page 3: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/3.jpg)
Marcel Stanitzki3
How does a Silicon Pixel work ? From a semiconductor perspective
− Silicon pn-junction (aka Diode)
− not really that different from a strip detector ...
Particle passing through
− always treated as MIP
− generate electron-hole pairs
− 80 e/per µm
Reverse bias pn junction
− can fully deplete bulk
− either collect holes or electrons
–
h+ e-
+
© Rainer Wallny
![Page 4: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/4.jpg)
Marcel Stanitzki4
Materials High resistivity Silicon
− R = 1kΩcm
used mostly for detectors
Quite expensive
Charge Collection
− thickness up to 500 µm
− Fully depleted
− Collect charge via drift
− Fast (~ 10 ns)
− small charge spread
Low resistivity Silicon
− R = 10Ωcm
Used in CMOS industry (epi)
Cheap
Charge collection
− thin (10 µm)
− basically undepleted− collect charge via diffusion
− Slow ( ~ 100 ns)
− larger charge spread
![Page 5: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/5.jpg)
Marcel Stanitzki5
Reality is more complex !
There are more things between p and n, Horatio, than are dreamt of in
your philosophy !
![Page 6: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/6.jpg)
Marcel Stanitzki6
Pixel RD for the ILC Very active field for the last ten years
Plenty of groups involved in all 3 ILC regions
− Europe
− Asia
− Americas
A lot of progress has been made
I'll focus on
− Pixel technologies
− Silicon-only pixels
Apologies in advance for omissions ...
![Page 7: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/7.jpg)
Marcel Stanitzki7
SiD - a typical ILC detector
VertexDetector
ECAL
HCAL
Solenoid
Tracker
Muon Chambers
Letter of Intent submitted 31st of March
![Page 8: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/8.jpg)
Marcel Stanitzki8
ILC Detector Requirements Impact parameter resolution
Momentum resolution
Jet energy resolution goal
Detector implications − Calorimeter granularity − Pixel size − Material budget, central − Material budget, forward
σ rφ≈σ rz≈5⊕10 / p sin3 /2 σ rφ=7 .7 ⊕33 / p sin
3 /2
σ 1pT =5× 10−5 GeV−1
σ EE=30%E
σ EE=60%E
Need factor 3 better than SLD
Need factor 10 (3) better than LEP (CMS)
Need factor 2 better than ZEUS
Detector implications− Need factor ~200 better than LHC − Need factor ~20 smaller than LHC− Need factor ~10 less than LHC− Need factor ~ >100 less than LHC
Highly segmented, low mass detectors required -> pixels !
![Page 9: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/9.jpg)
Marcel Stanitzki9
The ILC Vertex Detector 5 layers, either
− long barrels
− barrels + endcap disks
− gas-cooled
First layer ~ 1.2 cm away from primary vertex
Occupancy 1 %
Material budget: ~1 % X0
![Page 10: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/10.jpg)
Marcel Stanitzki10
And the pixels spread ... Pixels originally only intended for the vertex detectors
− like SLD ...
But pixels are becoming affordable
− Pixel detectors spread outwards
Silicon pixel trackers are now feasible
− ~70 m2 silicon , 30 Gigapixel
Digital EM calorimetry using pixels as particle counters
− 2000 m2 area, 1 Terapixel
![Page 11: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/11.jpg)
Marcel Stanitzki11
Pixels everywhere ...
0.1 1 10 100 1000 1000010
100
1000
10000
100000
1000000
10000000
SLD VXD3
ATLAS CMS
ILC Vertex
Pixel Tracker
Digital ECAL
Area (m2)
Mill
ion
Ch
an
nel
s
(m2)
![Page 12: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/12.jpg)
Marcel Stanitzki12
ILC timing
ILC environment is very different compared to LHC
− Bunch spacing of ~ 300 ns (baseline)
− 2625 bunches in 1ms
− 199 ms quiet time
Occupancy dominated by beam background & noise
Readout during quiet time possible
2625
![Page 13: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/13.jpg)
Marcel Stanitzki13
ILC Pixels : Timing and Readout Time stamping
− single bunch resolution
− buffer hits
− readout during quiet time
Time slicing
− divide train in n slices
− readout during train/quiet time
Time-integrating
− no bunch information
− readout during quiet time
On-Pixel processing
− each pixel self-sufficient
− digital data stream off pixel
− minimal amount of interconnects
Off-Pixel processing
− data is moved to a readout chip
− requires additional circuitry and interconnects
![Page 14: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/14.jpg)
Marcel Stanitzki14
How to achieve Occupancy goal ? Goal is 1 % occupancy
− can't be just done by integrating over the entire train
− Especially for the inner layers
Pixel size
− go to very small pixels
Time stamping and buffering
− read and store hits on pixel
Time Slicing
− read out the entire detector n times during the train
Combination of the above
![Page 15: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/15.jpg)
Marcel Stanitzki15
And CLIC ? CLIC is an alternative proposal for a linear
collider driven by CERN
− Up to 3 TeV center-of-mass energy
− 48 km long
Innovative “Drive-Beam” Technology
− Drive beam is used to generate accelerating field for main beam
− Proof -of-principle ongoing
− CTF3 at CERN is becoming online now
Very small beams
− Larger beam backgrounds
− vertex detector moves outwards (~ 4 cm)
![Page 16: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/16.jpg)
Marcel Stanitzki16
CLIC Bunch structure
Train repetition rate 50 Hz
CLIC
CLIC: 1 train = 312 bunches 0.5 ns apart 50 Hz
ILC: 1 train = 2680 bunches 337 ns apart5 Hz
Assess need for detection layers with time-stamping
− Innermost tracker layer with sub-ns resolution
− Additional time-stamping layers for photons and for neutrons
Readout electronics will be different from ILC
Consequences for power pulsing?
Consequences for a CLIC detector:
![Page 17: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/17.jpg)
Marcel Stanitzki17
Why not using LHC-style pixels ? LHC requirements
− extremely rad hard
− very fast (25 ns)
LHC pixels ..
− “large“
− cooling required
ILC requirements
− slow and not rad-hard
ILC pixels
− very low material budget
− high granularity
CMS Barrel Module
![Page 18: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/18.jpg)
Marcel Stanitzki18
The material budget
ATLAS ATLAS
ILC Goal for whole Tracking System
![Page 19: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/19.jpg)
Marcel Stanitzki19
Other short comings Excessive use of bump-bonding
− difficult
− yield issues
− limits minimum pixel size ...
Cooling requirements
− more material
− more complexity
Manufacturing & Cost
− Everything is custom-made (meaning expensive)
− Cost per m2 too high for large systems
![Page 20: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/20.jpg)
Marcel Stanitzki20
CCDMAPS
SoI-MAPSISIS
3D Pixels
DEPFET
Pixel Technology Tree
![Page 21: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/21.jpg)
Marcel Stanitzki21
CCD
CPCCD
FPCCD
![Page 22: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/22.jpg)
Marcel Stanitzki22
CCD's Charge-Coupled Device
Extensively used in imaging
Established technology
SLD's VXD3 used CCD's
Basic working principle
− charge storage
− readout as bucket-chain
− robust against pick-up
Require
− high charge transfer efficiency
− cooling to -20 C
− high drive currents
![Page 23: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/23.jpg)
Marcel Stanitzki23
CPCCD (LCFI) “Classic “ CCD readout is slow
Column Parallel CCD
Idea: divide readout chain into columns
− Higher speeds possible (50 MHz)
− Time slicing approach (20 frames)
− 20 µm pixels
CPCCD requires a dedicated readout chip
High currents driving the readout
already second generation design
“Classic CCD”Readout time ≈
N× M/fout
N
M
N
Column Parallel CCD
Readout time = N/fout
M
![Page 24: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/24.jpg)
Marcel Stanitzki24
A CPCCD Module
CCDDriver Chips
Readout ASIC
![Page 25: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/25.jpg)
Marcel Stanitzki25
FPCCD (KEK et. al.) Fine Pixel CCD
Time-integrating
− Instead of time slicing ...
− requires 5 µm pixels
Fully depleted epitaxial layer
− minimize the number of hits due to charge spread
Requires cooling
Readout similar to CPCCD
currently 12 µm pixel size
− Expect 5 µm pixels in 2011
Layout of prototype
ASIC
Amp. LPF CDS
CCD
ADC
First Prototype 12 First Prototype 12 µµm m pixels 512x128x4 pixels 512x128x4 pixels totalpixels total
![Page 26: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/26.jpg)
Marcel Stanitzki26
ISIS
![Page 27: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/27.jpg)
Marcel Stanitzki27
p+ shielding implant
n+buried channel (n)
Charge collection
p+ well
reflected charge
reflected chargeHigh resistivity epitaxial layer (p)
storage pixel #1
sense node (n+)
row select
reset gate
Source follower
VDDphotogate
transfer gate
Reset transistor Row select transistor
outputgate
to column load
storage pixel #20
substrate (p+)
ISIS (LCFI) In Situ Image Storage
− charge collection withphoto diode
− Transfer to CCD-likestructure
− Time-slicing (20x)
Readout chips separate
− semi-integrated pixels
− plans for full integration
First proof of principle devices
− ISIS1
− Successor ISIS2 has shown ”signs of life”
Output and reset transistors
CCD (5x6.75 μm pixels)
Photogate aperture (8 μm square)
![Page 28: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/28.jpg)
Marcel Stanitzki28
DEPFET
![Page 29: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/29.jpg)
Marcel Stanitzki29
DEPFET (DEPFET collaboration) DEpleted P-channel FETs
Basic principle
− Bulk fully depleted
− Collection by drift
− Internal gate collects charge
Clear gate necessary
Charge collection with FET's switched off, low power
Unique process developed by MPI Halbleiterlabor München
Leading Candidate for Super-Belle Vertex Detector
![Page 30: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/30.jpg)
Marcel Stanitzki30
DEPFET Prototypes DEPFET readout
− External gate row select
− Signal charge modifies current
− CDS style readout using Clear gate
Two driver ASICs needed
Latest version PXD05
− 24 µm pixel size
− tests ongoing
n x mpixel
IDRAIN
DEPFET- matrix
VGATE, OFF
off
off
on
off
VGATE, ON
gate
drain VCLEAR, OFF
off
off
reset
off
VCLEAR, ON
reset
output
0 suppression
VCLEAR-Control
![Page 31: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/31.jpg)
Marcel Stanitzki31
MAPS
TPAC
Chronopixels
Mimosa DNW-MAPS
LDRD
![Page 32: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/32.jpg)
Marcel Stanitzki32
MAPS basic principle Monolithic Active Pixel Sensors
CMOS technology
− Down to 180 nm/130 nm
Charge is collected by diffusion
− Slow > 100 ns
Integrated readout
Thin Epi-layers (< 15 µm)
Parasitic charge collection
− can't use PMOS ...
Basic MAPS cell for Particle Physics
− The 3T array
3T cell
![Page 33: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/33.jpg)
Marcel Stanitzki33
MIMOSA (IRES et. al.) MIMOSA family
− 3T architecture
− Restricted to NMOS
MIMOSA 22
− 0.35 µm AMS OPTO process
− 18.4 µm pixel size
− 128 columns
− 128 x 576 pixels in total
− Read-out time 100 μs
Readout as Rolling-Shutter
− One column read out at a time
![Page 34: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/34.jpg)
Marcel Stanitzki34
LDRD (LBNL et. al.) Current: LDRD03
− 3T with in-pixel “CDS”
− Readout at the end of a column
− Made in 0.35 µm AMS OPTO process
− 20 µm Pixels
− 96 columns with 96 pixels each
Rolling-Shutter readout
1 m
m
20x20 µm2
pixels
ADCs
SRAM
![Page 35: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/35.jpg)
Marcel Stanitzki35
Overcoming the limits Two approaches
Deep n-well
− n-well diode as a deep implant covering most of pixel
− Can have PMOS (small number)
Deep p-well
− Encapsulate electronics n-wells with deep p-implant
− shielding, so no parasitic charge collection
− Realized e.g. in INMAPS process and in ISIS
![Page 36: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/36.jpg)
Marcel Stanitzki36
Deep n-Well MAPS (INFN) Made in ST 130 nm process
− Triple-well approach
25 x 25 µm pixels with binary readout
− Goal 15 x 15 µm
Integrated electronics
− Pre-amp, discriminator
− Sparsification, time-stamping
Plans to explore smaller feature sizes
25
µm
25 µ m
DNW sensor
•Preamplifier
•Discriminator
Time stamp register
Sparsification logic
![Page 37: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/37.jpg)
Marcel Stanitzki37
TPAC (CALICE-UK) 50 x 50 µm with binary
readout
− Deep p-well/INMAPS 180 nm
− Pixel developed for digital EM calorimetry
− Different optimization
integrated electronics
− Pre-amp, comparator
− Pixel masks and trim
Logic strips
− Hold buffers and time- stamping
− Add ~ 11 % dead area
37
Deep p-well
Circuit N-Wells
Diodes
![Page 38: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/38.jpg)
Marcel Stanitzki38
Chronopixels (Yale/Oregon) Similar to previous pixels
− In-pixel electronics
− Hit buffering
− Time-stamping
− Binary readout
Prototype made in 180 nm TSMC
− Pixel size 50 x 50 µm
Goal
− 45 nm process
− 10 x 10 µm pixels
− Deep p-well and high-res epi
![Page 39: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/39.jpg)
Marcel Stanitzki39
SoI-MAPS
FermilabSOI LDRD
SOI
![Page 40: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/40.jpg)
Marcel Stanitzki40
SoI Basics Silicon on Insulator (SoI)
Thin active circuit layer on insulating substrate
~200 nm of silicon on a “buried” oxide (BOX) carried on a “handle” wafer.
Handle wafer can be high resistivity silicon
Integration of electronics and fully depleted detectors in a single wafer
Diode implant through the buried oxide
(Soitech illustration)
Active
BOX
Substrate(detector material)
![Page 41: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/41.jpg)
Marcel Stanitzki41
MAMBO (Fermilab) Monolithic Active pixel
Matrix with Binary cOunters
Made in 150 nm Oki Process
− 200 nm BOX layer
Pixel size is 26 x26 µm
− Implements a 12 bit counter
Common problem for all SoI
− Backgate effect handling wafer
− Can be fixed by using thicker BOX layer
− Alternatively design work-arounds
![Page 42: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/42.jpg)
Marcel Stanitzki42
3D Pixels
![Page 43: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/43.jpg)
Marcel Stanitzki43
3D Pixels The ultimate dream of any
pixel designer
− Fully active sensor area
− Independent control of substrate materials for each of the tiers
− Fabrication optimized by layer function
− In-pixel data processing
− Increased circuit density due to multiple tiers of electronics
A new way of doing things
Conventional MAPS
pixel
AddressingA/D, CDS, …
Add
ress
ing Diode
3T
3-D Pixel
pixel
Detector
ROIC
Processor
![Page 44: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/44.jpg)
Marcel Stanitzki44
VIP-I (Fermilab) Vertically Integrated Pixel
Pixel array 64x64, 20x20 µm pixels
− Analog and binary readout
− 5-bit Time stamping
− Sparsification
Designed for 1000 x 1000 array
Chip divided into 3 tiers
Made in MIT-LL process
VIP2a is on its way
Tier 38.2 µm
Tier 27.8 µm
Tier 16.0 µm
oxide-oxide bond
3D Via
![Page 45: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/45.jpg)
Marcel Stanitzki45
3D Process Developments The MIT LL process
− Demonstrated a fully functional device
However:
− Poor yield- both processing problems and overly aggressive design
− VIP2 will use degraded design rules (0.15 -> 0.2 or 0.3 µm) with improved transistor models
− Analog SoI design is challenging
− Long turn-around time
− Not a commercial process
Tezzaron 130 nm
− Existing rules for vias and bonding
− Relatively fast turn around
− One stop shop for wafer fabrication, via formation, thinning, bonding
− Low cost
− Process is available to customers from all countries
![Page 46: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/46.jpg)
Marcel Stanitzki46
Future Trends Always in motion the future is ...
− especially for pixels
Higher integration
− Smaller feature sizes and 3D integration will make this possible
Larger sensor areas
− Real CMOS Stitching allow wafer-scale sensors
Low power designs
− Large pixel system will need to reduce power usage per channel
![Page 47: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/47.jpg)
Marcel Stanitzki47
1985 1990 1995 2000 2005 2010 2015 2020 20250
100
200
300
400
500
600
700
800
900
Year of Availability
Fe
atu
re S
ize
(n
m)
Process trends
ATLAS ABCDATLAS ABCD
MIMOSA
CMS APV25
TPACDeep n-well
Intel Pentium 4Intel Core2 Intel iCore7
Le
ga
cy p
roc
ess
es
Deep
sub
-micro
n
Mixed
-Mo
de
CM
OS
![Page 48: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/48.jpg)
Marcel Stanitzki48
Why not deep submicron ?
Some problems
− Mostly pure digital processes (CPU, DRAM, etc)
− Leakage Currents become a problem
− small dynamic range due to operating voltage of 1 V ADC design becomes way more difficult
− New design kits, tools etc
− Smaller process does not automatically mean smaller pixels
Access to deep submicron processes
− Very difficult, foundries are not keen on a runs with a few wafers only
− Costs are not compatible with STFC funding 180 nm mask set (~ 50.000 US-$) 65 nm mask set ( 1.000.000 US-$)
![Page 49: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/49.jpg)
Marcel Stanitzki49
2002 2004 2006 2008 2010 2012 2014 2016 2018 2020 20220
10
20
30
40
50
60
70
80
90
100
Year of availability
Fe
atu
re s
ize
(n
m)
Where does it end ...CMOS
Na
no
s
tructu
res
Standard Lithographybreak-down
End of CMOS
![Page 50: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/50.jpg)
Marcel Stanitzki50
Large CMOS sensors CMOS structures have size limits
− the reticle size
− process-dependent
− usually 25x25 mm
This is a technology limit for large sensors
Mainstream Industry not very interested
− e.g. Intel Core2 (65 nm) 12x12 mm
− Only interesting for imaging applications
Way out : Stitching sensors
![Page 51: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/51.jpg)
Marcel Stanitzki51
Stitching
OriginalSensor Design
AB B
B
B
C C
CC
StitchableSensor Design
AB B
B
B
C C
CC
StitchedSensor Design
B
B
B
B
B
B
B
B
A A A A
A
A
A A A A
A
AAA
A A
C
C CB B B B
C CB B B B
2 cm 2 cm
5 cm
![Page 52: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/52.jpg)
Marcel Stanitzki52
Some comments Stitching can't be a second thought
− design for it from beginning
Stitchable designs are more complex
Mask set more expensive ..
But then
− normal wafer costs
− mass producible
− wafer size (300 mm) is the limit
Caveat
− larger structures mean lower yield ...
− Compensate by robust/simple designs
![Page 53: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/53.jpg)
Marcel Stanitzki53
Which Technology to choose? Even more difficult to make a forecast
For a vertex detector
− Small area (~ 1 m2) so choose technology that can do the job
− Cost is a minor issue
For Silicon Pixel Trackers/ECAL etc
− Industrial processes
− Mass producible and cheap (large areas)
− Minimize interconnects
Interesting times ahead ...
![Page 54: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/54.jpg)
Marcel Stanitzki54
SPiDeR CALICE-UK and LCFI got canceled by STFC
− despite being major players in the pixel world
− big innovations
UK Pixel Community made a new proposal
SPiDerR (Silicon Pixel Detector R&D)
− Birmingham, Bristol, Imperial College, Oxford and RAL
3 year Program
− Generic Pixel R&D (TPAC, Novel Structures)
− Generic Techniques using Pixels (DECAL)
− ISIS support was canceled by STFC
![Page 55: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/55.jpg)
Marcel Stanitzki55
Summary If you like to know more ...
− The ILC R&D reviews are an excellent summary of the activities− http://www.linearcollider.org/wiki/doku.php?id=drdp:drdp_home
Thanks to
− J. Brau, C. Damerell, M. Demarteau, T. Greenshaw, L. Linssen, R. Lipton, K.D. Stefanov, Y. Sugimoto, R. Turchetta, M. Tyndel, N. Wermes for material, comments and discussion
![Page 56: Pixel Technologies for the ILC Material budget, forward σrφ≈σrz≈5 ⊕10/ psin 3/2 σ rφ=7.7 ⊕33/ psin3/2 σ 1 pT =5× 10 −5 GeV−1 σ ... −Alternatively design work-arounds](https://reader034.vdocuments.pub/reader034/viewer/2022051722/5aa920c07f8b9a77188c6ad2/html5/thumbnails/56.jpg)
Marcel Stanitzki56
Who is doing what LCFI (UK collaboration)
− CPCCD/ISIS
FPCCD group
− FPCCD
DEPFET Collaboration
− DEPFET
LBNL/INFN/Purdue
− MAPS/SoI MAPS
Fermilab
− SoI MAPS/3D Pixels
CALICE-UK
− MAPS (TPAC)
CMOS-VD
− MAPS (MIMOSA)
Hawaii
− CAP