plasma-assisted mbe growth of inn film and …...米国における窒化物半導体開発動向 -...

米国における窒化物半導体開発動向- 超高周波GaN電子デバイス -

R&D activities of nitride semiconductors in USA

- High-frequency GaN electrical devices -

東脇正高

Masataka Higashiwaki

情報通信研究機構新世代ネットワーク研究センター

National Institute of Information and Communications Technology

Outline

1. Background

2. R&D projects of high-frequency GaN transistors in USA

3. Recent reports

4. Summary

Past background of R&D of high-frequency GaN HEMTs

Excellent GaN material properties for high-frequency applications

Large saturation electron velocity: ~3×107 cm/s (theory), ~ 2×107 cm/s (exp.)

High breakdown electric field: 3.3×106 V/cm

Past projects above mm-wave frequency

USA:

High-power GaN HEMTs at Ka band (27-40 GHz)

• 13.7 W/mm @ 30GHz, PAE 40-41% [Y.-F. Wu et al. (Cree), IEDM Tech. Dig. (2007)]

• 10 W/mm @ 30 GHz, PAE 55% [J. S. Moon et al. (HRL), IEEE EDL 29, 834 (2008)]

Japan:

FED (2002-2006)

• 5.8 W/mm @ 30 GHz, PAE 43.2% [ T. Inoue et al., IEEE TMTT 53, 74 (2005)]

`The research and development project for expansion of radio spectrum resources'„

the Ministry of Internal Affairs and Communications (2006-2010)

MMIC: 1.6 W/mm @ 75 GHz [Y. Nakasha et al. (Fujitsu), IEEE CSIC Symp. Dig. (2010)]

ONR MINE MURI program (2005-2010)

Multi-University Research Initiative (MURI) program

University of California, Santa Barbara (Profs. Mishra and York)

Cornell University (Prof. Shealy )

Notre Dame University (Prof. Xing)

University of North Carolina (Prof. Trew )

Ohio State University (Prof. Ringel)

University of Michigan (Prof. Singh)

Funding agency: Office of Naval Research (ONR)

Program: Millimeter-wave Initiative for Nitride Electronics (MINE)

Term: 2005-2010 (5+1=6 years)

Purpose: “Development of GaN-based mm-wave power sources”

DARPA NEXT program (2009- )

Ongoing US R&D program of high-frequency GaN HEMTs and circuits

Funding agency: US Defense Advanced Research Projects Agency (DARPA)

Microsystems Technology Office (MTO)

Program: Nitride Electronic NeXt-Generation Technology (NEXT)

Term: 2009-2011 (1st phase), 2011-2013 (2nd Phase ), 2013-2015 (3rd phase)

Purpose:

“Developing a revolutionary nitride transistor technology that simultaneously

provides extremely high-speed and high-voltage swing [Johnson Figure of Merit

larger (JFoM) than 5 THz-V] in a process consistent with large-scale integration in

enhancement/depletion (E/D) mode logic circuits of 1,000 or more transistors.”

Contractors: HRL Laboratories ($16,043,488)

Northrop Grumman + UCSB ($28,900,900)

TriQuint Semiconductor + Notre Dame + MIT ($16,188,131)

http://www.darpa.mil/Our_Work/MTO/Programs/Nitride_Electronic_NeXt-Generation_Technology_(NEXT).aspx

Purpose of DARPA NEXT program


GaN HEMT

InP HEMT, HBT

Target characteristics of DARPA NEXT program (1)

Before NEXT Requirements of NEXT

D-mode GaN HEMT:

fT = 300⇒400⇒500 GHz

fmax = 350⇒450⇒550 GHz

E-mode GaN HEMT:

fT = 200⇒300⇒400 GHz

fmax = 250⇒350⇒450 GHz

JFoM (fT×Vbr) > 5 (THz・V)

D-mode AlGaN/GaN HEMT (Lg = 60 nm):

fT = 190 GHz

fmax = 251 GHz

Vbr > 40 V

E-mode AlN/GaN HEMT (Lg = 80 nm):

fT = 111 GHz

fmax = 156 GHz

Ref. D-mode: M. Higashiwaki et al., APEX 1, 021103 (2008)

E-mode: M. Higashiwaki et al., IEEE TED 54, 1566 (2007)


Program Go/No-Go decision metrics

(1) Johnson Figure of Merit = (breakdown voltage) x (fT)

(2) Yield defined as fraction of devices tested that meet fT metric.

(3) Test sample: at least 100 devices on a single wafer.

(4) Test sample: at least 100 devices/wafers over a lot of at least 5 wafers.

(5) Yield defined as fraction of process control monitors (PCMs) tested that achieve at least 80% of designed frequency.

(6) PCM to be a 5-stage ring oscillator. Test sample: at least 20 PCMs on a single wafer.

(7) PCM to be a 51-stage ring oscillator. Test sample: at least 20 PCMs on a single wafer.

(8) PCM to be a 501-stage ring oscillator. Test sample: at least 20 PCMs/wafer over a lot of at least 5 wafers.

(9) The standard deviation of the stated parameter.

(10) Minimum test time for PCM under normal operating conditions until failure condition observed.

Test sample: 20 PCMs.

Failure condition: Failure of a single PCM or degradation of average frequency changes by 20%.

Target characteristics of DARPA NEXT program (2)

HRL Laboratories, LLC

Device structure (HRL)

• S/D electrodes: Non-alloy metal + n+-GaN re-growth

• Thin barrier layer to keep high aspect ratio

• D-mode: AlN (3.5 nm), E-mode: AlN (2.0 nm)

• AlGaN back barrier

K. Shinohara et al., IEDM Tech. Dig (2010)

A. L. Corrion et al., IEEE EDL 31, 1116 (2010)

AlN/GaN D/E-mode HEMTs

DC characteristics (HRL)

Idmax = 1.62 A/mm

Peak gm = 723 mS/mm

Idmax = 0.92 A/mm

Peak gm = 700 mS/mm

D-mode (Lg = 40 nm) E-mode (Lg = 80 nm)

D-mode: K. Shinohara et al., IEDM Tech. Dig (2010)

E-mode: A. L. Corrion et al., IEEE EDL 31, 1116 (2010)

Small-signal characteristics (HRL)


fT = 220 GHz

fmax = 400 GHz

fT = 112 GHz

fmax = 215 GHz

D-mode: K. Shinohara et al., IEDM Tech. Dig (2010)

E-mode: A. L. Corrion et al., IEEE EDL 31, 1116 (2010)

University of California, Santa Barbara (UCSB)

Ga and N-face (NRG & UCSB )

Polarization reverses direction with respect to the surface

Bulk GaN

in vacuum

+ + + + + + +

PSP

N-terminated surface

----------

PSP

+ + + + + + +

Ga-terminated surface

----------

Top figure taken from M. J. Murphy et al.,

MRS Internet J. Nitride Semicond. Res. 4S1, G8.4 (1999) Courtesy: Ms. Nidhi & Prof. Mishra (UCSB)

Better electron

confinement during pinch-off

→ larger Rds

Why do N-polar GaN HEMTs? (NRG & UCSB )

dsmgddsdsgdgs

mT

RRgCRRRCC

gf

1

2

GaN buffer

GaN

AlGaN

2DEG Gate can be placed very close to the

2DEG

More gate control due to charge

centroid shifted towards the gate

Low ohmic contact resistance Natural Back-barrier

N-face

AlGaNGaN

EF

EC

VP

N-polar nitrides are the best choice for high frequency applications

Psp-

+

Contacting the 2DEG through GaN

(lower bandgap) instead of AlGaN

InN based contacts feasible. Metal

to InN contact resistance ~ 5 Ω-μm

Already achieved RC = 23 Ω-μm by

InGaN regrowth on GaN

Courtesy: Ms. Nidhi & Prof. Mishra (UCSB)

Device structure (NRG & UCSB)

Gate first process:

• Refractory metal gate

• SiN sidewall spacer

Graded InGaN regrowth:

• Grade from GaN to InN

• Very little growth on sidewalls

Gate

AlGaN

GaN

Source Drain

High K dielectric

n+ GaN

graded to InN

SiN

n+ GaN

graded to InN

GaN

N-polar GaN HEMT structure


Excellent DC characteristics achieved by self-aligned technology

DC characteristics ofD-mode N-polar GaN HEMTs (NRG & UCSB )

Idmax = 2 A/mm Peak gm = 434 mS/mm

-7 -6 -5 -4 -3 -2 -1 00.0

0.4

0.8

1.2

1.6

2.0

IDS

gm

VGS

(V)I D

S (

A/m

m)

0

100

200

300

400

500

gm (m

S/m

m)

LG = 130 nm

LSD

= 1.0 m

VDS

= 2.5 V

0.0 0.5 1.0 1.5 2.0 2.50.0

0.4

0.8

1.2

1.6

2.0

I DS (

A/m

m)

VDS

(V)

LG = 130 nm

VGS

: 2V ... -6V


Small-signal characteristics ofD-mode N-polar GaN HEMTs (NRG & UCSB )

RG 560 Ω/mm

CGD 168.4 fF/mm

RG 26 KΩ/mm

CGD 92.8 fF/mm

fMAX value is state-of-the-art for the

voltages relevant for a self-aligned

structureFurther gate design is needed

to improve RG while keeping

CGD low to prevent fT drop

0.1 1 10 100

0

10

20

30

40

fT = 100 GHz

fMAX

= 126 GHz

LG = 130 nm

WG = 50 m

LSD

= 0.5 m

VD = 6 V

VG = -4 V

Gain

(dB

)

Frequency (GHz)

h21

U

fT/fMAX:

137/27 GHz

100/126 GHz Courtesy: Ms. Nidhi & Prof. Mishra (UCSB)

Device structure ofE-mode N-polar GaN HEMTs (NRG & UCSB )

Under sidewall

20 40 60 80 100

-4

-3

-2

-1

0

1

2

3

4

GaN

channel

SiN sidewall

EF

n(x)n

(x10

19 c

m-3)

Depth (nm)

En

erg

y (

eV

)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

∫ n(x)dx

= 4.5×1012 cm-2

AlN removed under sidewall

Under gate

0 10 20 30 40 50 60-5

-4

-3

-2

-1

0

1

2

3

4

5

GaN:SiGaN

channel

AlNAlN

SiN

Depth (nm)E

nerg

y (

eV

)

EF

Top AlN depletes 2-DEG under gate

0 20 40 60 80 100

-4

-3

-2

-1

0

1

2

3

4

InN

n+ Graded InGaN

(In: 0% to 65%)

GaN:SiAlN

GaN

channel

EF

En

erg

y (

eV

)

Depth (nm)

Under S/D

contacts*

U. Singisetti et al., APEX 4, 024103 (2011)

Courtesy: Dr. Singisetti & Prof. Mishra (UCSB)

• Idmax=0.74 A/mm, peak gm = 260 mS/mm at Vds = 3.0 V

• Vth = 0.7 V at Vds = 3.0 V.

• High Ron = 2.7 W-mm, due insufficient InN growth

DC characteristics ofE-mode N-polar GaN HEMTs (NRG & UCSB )



Small-signal characteristics ofE-mode N-polar GaN HEMTs (NRG & UCSB )

fT = 120 GHz, fmax = 11 GHz



University of Notre Dame

Device structure (TriQuint and Notre Dame)

InAlN/AlN/GaN D/E-mode HEMTs

Y. Tang et al., IEDM Tech. Dig (2010)

D-mode: non-recessed gate

E-mode: recessed gate

DC characteristics (TriQuint and Notre Dame)

Idmax = 1.9 A/mm

Peak gm = 840 mS/mm


Idmax = 1.84 A/mm

Peak gm = 920 mS/mm Y. Tang et al., IEDM Tech. Dig (2010)



fT = 94 GHz

fmax = 174 GHz

fT = 94 GHz

fmax = 176 GHz

Small-signal characteristics (TriQuint and Notre Dame)

Ring oscillator (TriQuint and Notre Dame)


D/E-mode InAlN/GaN HEMT ring oscillators

a) 5-stage and b) 51-stage

5-stage circuit

Inferred stage delay

15.3 ps/stage @ 6.533 GHz

Massachusetts Institute of Technology (MIT)

Device structure (MIT)

D-mode AlGaN/AlN/GaN HEMTsSi/Ge/Ti/Al/Ni/Au alloyed ohmic

Novel T-gate process

J. W. Chung et al., IEDM Tech. Dig (2010)

D-mode AlGaN/GaN HEMT (Lg = 55 nm)

DC and small-signal characteristics (MIT)

Id = 1.0 A/mm @ Vg =0V

Peak gm = 500 mS/mm

fT = 225 GHz

fmax = 120 GHz


Current fT and fmax of GaN HEMTs (until Dec 2010)

D-mode E-mode

fT (GHz) fmax (GHz) fT (GHz) fmax (GHz)

HRL 220 400 112 225

UCSB 137 126 120 11

Notre Dame 94 174 94 176

MIT 225 120 NA NA

DARPA

required

value

(Phase I)

300 350 200 250

Evolution of fT in GaN HEMTs


Delay time analysis (HRL)

K. Shinohara et al., IEDM Tech. Dig (2010)

Drain delay has to be decreased

Self-aligned device structure is essential!!

How to make GaN HEMT faster

Total delay = Transit delay + Drain delay + Charging delay

• Transit delay: Transit time for passing through the region under the gate

• Drain delay: Delay time related to the drain depletion region

• Charging delay: Channel charging + parasitic charging

Transit delay can be decreased by reduction of Lg

Charging delay can be decreased by reduction of parasitic R and C

Drain delay is almost proportional to Vd (td = 0.05 ps×Vd)

Self-aligned device structure is the only solution for this problem

Summary

R&D activities of high-frequency GaN HEMTs in USA

DARPA NEXT program (2009-2013)

Current status

D-mode: fT = 225 GHz, fmax = 400 GHz

E-mode: fT = 120 GHz, fmax = 225 GHz

Self-aligned device structure is necessary to decrease drain delay

Conceivable tasks:

• Fabrication process in itself

• Suppression of increase in parasitic gate capacitance

• Suppression of decrease in breakdown voltage

Requirements by 2011

D-mode: fT = 300 GHz, fmax = 350 GHz

E-mode: fT = 200 GHz, fmax = 250 GHz

JFoM (fT×Vbr): > 5 (THz・V)

plasma-assisted mbe growth of inn film and …...米国における窒化物半導体開発動向 -...

Documents