Pratik Shah 373 River Oaks Circle, Apt. 302, San Jose, CA - 95134 +1 (916) 996 – 4027 pratikshah14@outlook.com Linkedin URL: https://www.linkedin.com/in/pratikshah14 OBJECTIVE: Actively looking for a job in the field of VLSI Design and Verification

EDUCATION:

Master of Science Electrical Engineering San Jose State University December, 2015 GPA 3.41/4 Bachelor of Electronics Engineering Pune University, India May, 2013 First Class RELATED COURSEWORK:

Digital System Design and Synthesis, VLSI Design and Technology, SOC Design & System Verilog, Digital Design DSP/ Communication, ASIC CMOS Design, Computer Architecture, High Speed CMOS Design, Digital Logic Design, Test and Measurement Techniques, Technical Writing, Computer Networks, Semiconductor Devices, Engineering Management, Linear Systems Theory, Probability, Random Variables & Stochastic Processes SKILLS:

Programming Languages: Perl, Python, C, Verilog, System Verilog, Shell script, Matlab

Hardware skills: RTL & Gate Level Analog Circuit Design, Debugging & Verification of Digital Design,

Simulation, Synthesis, Static and Dynamic Timing analysis, Digital Circuit and ASIC design, SOC Design, VLSI, FPGA, Logic Design, Fault Detection, Image processing, Buses – PCI Express, AHB, API, etc, Embedded Systems

Tools: Synopsis Design Compiler, Synopsis Design Vision, Xilinx ISE, Cadence Virtuoso, Model Sim,

Eclipse, MATLAB, Altera Quartus II, Altera Mega Wizard Operating systems: Linux/UNIX, Windows 98/2000/XP/Vista/7, MS DOS Communication: Multilingual: English / Hindi / Marathi: Experience in creating & giving professional

PowerPoint Presentations: Excellent at communicating complex technical concepts

PROJECT EXPERIENCE: Secure Hash Algorithm (SHA 3) on Xilinx FPGA (Vivado, Xilinx)

Implementing SHA 3 algorithm using Verilog on Artix 7

Vivado Xilinx simulator is used to simulate the design on Nexys 4 development board

Pipelining is used to increase the speed of the design

Power optimization is done by implementing the design using state machine

This algorithm is compared with SHA 2 for research purposes

A 8-bit Scalar Processor (Verilog, VCS)

Implemented an 8–bit scalar microprocessor using Verilog to precisely describe the functionality of the scalar processor and support a subset of MIPS instructions

Performed synthesis and timing analysis and the design was tested using Toshiba tc240c library on VCS

Configured Processor with suitable delays and to avoid latches during RTL synthesis

Simulated the design on Model Sim

Signed Sequential Multiplier (Quartus II, Modelsim)

Designed a parameterized sequential multiplier using Booth’s algorithm

Implemented and verified the designed module using Quartus II, Modelsim

Simulated the design in VCS as well

Pratik Shah 373 River Oaks Circle, Apt. 302, San Jose, CA - 95134 +1 (916) 996 – 4027 pratikshah14@outlook.com Linkedin URL: https://www.linkedin.com/in/pratikshah14 Secure Hash Algorithm (SHA – 256) Crypto-processor (Cadence Virtuoso)

Coordinated with a team of three to successfully design and implement a 256 bit crypto processor at transistor level in Cadence using 45nm technology

Design reads digital data from a text file which converts it into multiple blocks of voltage signals of 512 bit each

Symbols created using Verilog-A. This symbol was wired to our main processor block to form the primary inputs. The outputs are unique 8 words of 32 bit each thus resulting in a total of 256 bits

The circuit was implemented in LabVIEW which showed positive

5-stage pipelined MIPS CPU (Quartus II, Modelsim)

Designed a 5 stage pipelined MIPS CPU using Altera Quartus II simulator

Successfully tested the design using the instruction given in the test bench

Altera Mega Wizard utilized in the implementation of this project

Multiply-and-Accumulate (MAC) Engine (Quartus II, Modelsim)

Parallel MAC designed with the help of Look-up tables in Verilog

A Serial MAC designed implementing rounding and saturation logic for the result

Designed in Altera Quartus II using the Altera Mega Wizard

Tested successfully with color space converter for luminance

16-bit Fast Fourier Transform (FFT) Calculator (Quartus II, Modelsim)

Successfully designed a 16 point FFT engine using the Butterfly Processor and Complex Multiplier

Designed a Verilog model and a C model of the design

Successfully implemented the C model using NIOS II processor

Performance enhancement was achieved by implementing a Hardware Accelerator on the Altera FPGA DE1 board Bus Arbitrator for a SOC (System Verilog, VCS)

Designed an Arbitrator scheme in System Verilog for the utilization of the bus by the given number of master & slaves

Priorities assigned taking into consideration the minimum percentage utilization given for each master

Data written and read successfully with all the conditions meeting at the clock frequency of 200 Mhz

Synthesized design successfully using Synopsis tool Block Test Bench for Bug detection in Atmel 8271 AVR Timer/Counter (System Verilog, VCS)

Test bench designed in System Verilog to detect Timers/Counters with bugs from a series of 40 designs

Used System Verilog Tasks, Functions, Assertions and Sequences extensively

WORK EXPERIENCE:

Student Assistant Lead at University IT Help Desk (August, 2014- Present)

Solve numerous technical problems for the campus populations

Assigned to monitor and control a computer lab consisting of 35 systems

Actively involved in several on-campus student activities

Display strong communication & listening skills when addressing client technical issues in person and over the phone

ACTIVITIES & ACHIEVEMENTS:

“Metering ASIC’s” Paper Presentation, 1st Prize, Bhujbal Knowledge City, Meteorite’10 State Level Competition

Karmaveer Lions, State Level Football Tournament- 2nd Prize

“Robotic Soccer Tournament” 1st Prize, Bhujbal Knowledge City, Meteorite’12 State Level Competition

Worked with “ Help Age India “ – A social activist NGO