radar presentation from freescale

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Gao Lei Automotive FAE Manager China

Introduction to Freescale Radar

Microcontroller Solutions

FTF-AUT-F0077

M A Y . 2 0 1 4

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Overview

ADAS Trends and Need for Radar Systems

Radar Fundamentals

Freescale Radar Solutions

MRD2001 Packaged Radar Chipset

MPC5775K Microcontroller

Summary and Conclusions

ADAS MRD2001 MPC577xK

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Market Trends

Automotive Safety catches public eyes. In 2010, 1.24 million people were killed on

the worlds roads, the eighth leading cause of death globally (World Health Organization).

Within the developed regions, passive car safety systems, seat belts, airbags, and

crumple zones have proven essential in decreasing fatalities and serious injuries to

the occupants of cars and pedestrians.

New automotive safety regulation and standard. The automotive industry is under

pressure to provide new and improved vehicle safety systems like complex

advanced driver assistance systems (ADAS) with accident prediction and

avoidance capabilities.

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Advanced Driver Assistance Systems

Camera and Radar @>15kmh Cognition Algorithms to extract

features / classify objects

No display necessary F. Safety applied to longitudinal

motion (braking / Steering)

e.g.

Lane Keep Assist Adaptive cruise control

Automatic Emergency braking

Pedestrian protection

Rear/Side Camera, sat. Radar, Usonic @15kmh 3D Enviornmental Modeling

allowing self navigation

No Display Hard safety Longitudinal and

Lateral motion

Integration of Feature extraction

e.g.

Self-driving Auto

Sensor Fusion

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Accident Free Driving is Within Our Sight

Source Frank Gruson, Continental AG

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Applications for Automotive Radar Are Gro

wing

AEBS Advanced Emergency Braking

System

FCW Forward Collision Warning

LDW Lane Departure Warning

BUA Back up Aid

BSD Blind Spot Detection

Source ADASE

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Expected ADAS Regulations and NCAP Ratings

AEBS Advanced Emergency Braking System

FCW Forward Collision Warning

LDW Lane Departure Warning

BUA Back up Aid

BSD Blind Spot Detection

Source: Interpretation of Continental / Freescale Segment

FCW/LDW Availability if performances are

met (Source NHTSA)

FCW/LDW NCAP Tests

AEBS Mandatory for all

new cars

AEBS / LDW Mandatory for new trucks > 3.5t

FCW/AEBS/LDW/BSD Part of NCAP Star Rating

AEBS / LDW Mandatory for new trucks > 3.5t

BUA Mandatory for SUVs and Vans

2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Expected

Under Discussions

Decided

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1973 1980 1987 1990 1904 1995 1999 2009 1886

C. Hlsmeyer:

Patent 165546

1904

35 GHz, German project:

Daimler, BMW, Bosch, SEL,

VDO, AEG-Telefunken

1973

F. Ackermann

publication

Birthday for ACC

1980

project: PROMETHEUS

1B USD,

AICC: Autonomous Intelligent Cruise Control

1987-1994

76-77G band

proposed

1990

Mitsubishi

Diamante

ACC

(Lidar, Camera)

1995

Toyota

Denso

1996

Daimler

A.D.C

1998

Jaguar

Delphi

1999

Nissan

A.D.C

1999

76-77G band

regulated

1999

BMW

Bosch

2000

VW

Autocruise

2002

Audi

Bosch

2003

IFX

SiGe

2009

FSL

BiCMOS

2012

2012

main source: Hermann Winner, Die lange Entwicklung von ACC, 2003

Nissan

Omron/A.D.C

(Lidar)

2001

RADAR: 76-77 GHz ACC Development History

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Overview


Radar Fundamentals





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RADAR

relative velocity

vR 0

RaDAR (Radio Detection And Ranging)

RADAR

relative velocity

vR = 0

Distance R

Dt

Dt = 2 R / c0 Doppler Shift

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RaDAR (Radio Detection And Ranging)

RADAR RADAR

relative velocity

vR = 0 relative velocity

vR 0

Distance R

Dt

Dt = 2 R / c0 Doppler Shift

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FMCW (Frequency Modulated Continous Wave)

FMCW operation is independent of the speed or direction of travel of the target

high precision

FMCW is less complex, safer and lower cost (compared to pulse systems)

FMCW gives low false alarm rates

FMCW sees a higher percentage of valid targets

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FMCW Advanced System

Digital Beam Forming (DBF)

antenna arrays required

Dj is the phase difference of received IF signals from different antennae

atarget is the angle at which the target appears

w/r to the sensor axis

3 dB beamwidth Dq3dB = l/2L (L is defined by

footprint of antenna array)

Electronically Steerable Arrays (ESA)

adaptive beam forming

establised in military applications

Synthetic Aperture Radar (SAR)

multiple Rx and Tx antennae

reduced Dq3dB at same antenna footprint L

These Trends Drive More Tx and Rx Channels in Radar Chipsets

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Overview


Radar Fundamentals





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SiGe BiCMOS 77GHz Radar Chipsets S

yste

m In

teg

rati

on

Tranceiver Chipset

Industrys first 77GHz SiGe BiCMOS radar PLL + prog chirp

generator

Multi-channel 4 TX + 4 to 16 RX enables wide FOV, ESR,

multi-scan modes

Compatible with all leading MCU

Packaged Transceiver Chipset

Ultra-low power ~ 2.5W Scalable to 4 TX + 12 RX Supports fast modulation with

simultaneous active TX

High integration including baseband VGA + filters

Built-in system test enables compensation & calibration for

PCB, temperature variations

Optimized with Freescale MPC5775K radar processor

Single Channel TX

Industrys first 77 GHz radar IC supporting fast modulation

Single channel with integrated TX, PA, and VCO

Superior temperature stability

1 ch TX VCO

4 ch TX

+ PLL 4 ch RX

2012 2013 2014

MRD2001

FRDxX1050x

2 ch TX

3 ch RX + BB VCO

FRDxX1050x

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FRDxX1050x 77GHz Radar Transceiver Chipset

Differentiating Points

Highly integrated 77GHz automotive radar chipset supports up to 4Tx and 16 Rx channel configurations for 2D, 3D, DBF, and SAR automotive radar applications

Supports slow and fast modulation to 10 MHz / 100 ns

Fully integrated PLL and chirp generator programmed via SPI along with Tx power level, channel activation, & state machine control

Designed for integration with a multitude of microprocessors including the Freescale MPC567xK

VCO

PA

LO

Generation

DAC

PLL SPI,

Supply

Test

LO

Generation

VCO PLL

PA PA PA PA

SPI,

Supply,

Test

DAC,

Power

Control

Power

Splitter

4chTxPLL 4chRx

FRDxX1050x

Chipset

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Overview


Radar Fundamentals





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MRD2001 77GHz Packaged Radar Chipset The MRD2001 chipset is a scalable radar solution for high end and low end ADAS

applications, industrial safety, security, and robotics

Differentiating Points

Advanced packaging technology with BGA format

Scalable to 4 TX channels and 12 RX channels

Activate simultaneous Tx channels for electronic beam steering

Supports fast modulation at 100 MHz / 100 ns

Integrated baseband filter and VGA saves system bill-of-materials cost

Designed for integration with MPC577xK microprocessor

Typical Application Diagram

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Common Features for Packaged Parts

6 mm x 6 mm BGA package (0.5 mm

pitch)

Only most outer 2 rows are used for

control signals

Temperature Range -40C up to 125C

(ambient)

Temperature Sensor

Power/Peak Detector

SPI Control (max. guaranteed 10 MHz)

Tri-State Sense Output

(One Signal Line can be shared)

Software Addressing of Chips instead of dedicated hardwired chip select

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Overview


Radar Fundamentals





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Benefits of Integration

MPC5675K

System

MPC5775K

System

Performance MPC5775K offers top-performance for intense computational tasks with key integrated digital accelerators

Safe Built on proven safe technology it delivers a scalable, well documented, process compliant safe architecture and safe Software

Integration & Cost Right balance of memory, large number of Analogue IP designed for Radar, FFT accelerator. Drive Miniaturization and BOM saving

Flexible can be used in all applications and with all Front End Radar sensor technology and types.

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CPU Platform

266 MHz Power ISA Dual Issue core multi core system

Two z4 Cores in permanent delayed Lockstep for high safety integrity level

Two z7 cores for application execution I-cache 16 KB (2 ways) / D-Cache 16 KB (2 ways) Core Local D-memory (64kB at each core) with local MPU

Vector Floating Point Unit & SIMD (z7) 64 bit BIU with E2E ECC

Radar Processing Platform

Signal Processing Toolbox (SPT) FFT accelerator, SDMA, PDMA 8x Integrated -ADC with 5 MHz bandwidth and internal sampling clock of 320 MHz.

12-bit resolution DAC with maximum of 2Msps Low jitter 320Mhz PLL for RADAR

Memory

Up to 4 MBytes byte Flash with EE Emulation and ECC Up to 1.5 MBytes SRAM with ECC Safe Crossbar (E2E ECC) with system MPU

Vehicle & ECU communication

4 x FlexCAN (64 message buffers) 1 x FlexRay (Dual Channel 128 msg. buffers) 1 x Ethernet Controller (ENET) 4 x LINFlex (SCI) & 3x IIC 4 x dSPI (4cs std / 8cs in larger v package version only) 3 x eTimer 2 x FlexPWM (2x 12 channel) & 2x CTU Octal A/D (10 M samples/sec) SD Radar I/F 5MHz BW + 4x SAR 2 x SENT

System

Highly stable Oscillator for Radar ASIC to A/D synchronization SIPI (~300MBaud) for interprocessor or mc to ASIC communication Safe DMA Engines Autonomous Fault Collection and Control Unit CRC computing unit Junction temperature sensor Nexus Class 3+ debug interface (Aurora extension)

Qorivva MPC5775K MCU Overview

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RADAR Timing Generation

CTE

WGM

ADC ADC

ADC

DAC

SPT

A

C

Q

SRAM

CS

0 2 105

4 105

6 105

8 105

1 104

0.001

0.002

0.003

0.004

t

DACout(t)

G

P

I

O

acquisition

window events

chirp[N]

chirp[N+1]

Timing Table[N]

Timing Table[N+1]

fast

DMA

eDMA

eDMA Waveform[N]

Waveform[N+1]

run, hold, reset

ctep

Input signal from MRD2001

Control signal to MRD2001

Output signal to MRD2001

Sample received RADAR

echoes

10MSps/12bit

8x -ADC with 5 MHz bandwidth and an

internal sampling clock of

320 MHz 69dB SNR

A new best-in-class 12-bit

resolution DAC which

has maximum of 2Msps

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Configures and

controls SPT

Runs specialized

signal processing

tasks on SPE

Sample received RADAR

echoes

10MSps/12bit

RADAR Timing

Generation

Command list for

signal processing

Buffered ADC

samples

FFT data

Peak lists

Timing definition

SPT Operation Principle

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Range

FFT

Fast Chirp Sequence Doppler Radar

Chirps f(t)

t

Range Gate (Distance)

Dopple

r (S

peed)

ADC

1.N

Range

FFT

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Fast Chirp Sequence Doppler Radar

Range Gate (Distance)

Dopple

r (S

peed)

Doppler

FFT

PD

MA

SRAM

Peak List

Signal

Processing

z7 Cores

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Radar Algorithm Mapping

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Algorithm Partitioning

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SPT Features

Acquisition Block (SDMA)

Channel muxingSample re-ordering to simplify PCB routing

Sample DMAMerging ADC samples into memory words, arranging the data into packets, and distributing to memory locations

Programmable DMA (PDMA)

Transfers data between the system RAM/Flash/TCM to operand RAM or twiddle RAM (SPT internal RAMs) and vice-versa

Performs special packing and unpacking schemes on the fly, for reduced storage

Memory

Operand RAM stores the operands for operations like FFTs

Twiddle RAM stores constants like coefficients used in FFT operations

Work registers store single values for calculation (such as coefficients)

Hardware Accelerator

FFT

Radix4 and Radix2 butterfly and twiddle multiplication

Windowing for pre- and post-multiplication with coefficients

COPY

Primarily moves data from one location to another

Can transpose and pack complex data and manipulate real/imaginary parts

Command Sequencer

The command sequencer reads and interprets instructions in the command queue and triggers the operation specific scheduler depending on the instruction

CPU interaction

Debug Support

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Safety Features

As part of the Freescale SafeAssure program, the MCP5775K MCU has been designed with two high-performance Power Architecturee200z7 cores for signal processing and can help car manufacturers achieve a minimum ISO 26262 Automotive Safety Integrity Level-B (ASIL-B).

In addition to supporting the requirements of automotive functional safety applications, there are two e200z4 cores in a lockstep configuration specifically designed for decision-making and safety-critical requirements, helping to achieve ISO 26262 ASIL-D certification.

Some additional key safety features include online logic built-in self-test (LBIST) and memory built-in self-test (MBIST), End-to-End error-correcting code (ECC), clock and power generation supervisor, and a failure-handling modulewhich also enable customers to obtain ASIL-D certification.

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Radar is a critical element in ADAS solutions for future automobiles

The use of SiGe BiCMOS packaged radar solutions allows the

realization of low cost, multi-channel 77/79 GHz scalable chipsets

The MRD2001 chipset was specifically designed to interface with

the MPC5775K microprocessor to form a complete scalable radar

system (Tx and Rx) with few additional components

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Questions?

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Designing with Freescale

Tailored live, hands-on

training in a city near you

2014 seminar topics include

QorIQ product family update

Kinetis K, L, E, V series MCU product training

freescale.com/DwF

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2014 Freescale Semiconductor, Inc. | External Use

www.Freescale.com

radar presentation from freescale

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