slide set data converters ————————— oversampling and low...
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F. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SDF. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SD0
Slide Set
Data Converters
—————————
Oversampling And Low Order Σ∆ Modulators
F. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SDF. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SDF. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SD
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SummaryIntroduction
Noise shaping
First Order Modulator
Second Order Modulator
Circuit Design Issues
Architectural Design Issues
F. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SDF. MalobertiDATA CONVERTERS Springer2007
Chapter 6
OVERSAMPLING AND LOW ORDER SDF. MalobertiDATA CONVERTERS Springer2007
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OVERSAMPLING AND LOW ORDER SD
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Introduction
With oversampling the signal band occupies a small fraction of the Nyquistinterval.
The use an ideal digital filter possibly reduces the quantization noise powerin the signal band
V 2n,B =
∆2
12·
2fBfs
=V 2ref
12 · 22n·
1
OSR(1)
ENOB = n+ 0.5 · log2 · (OSR) (2)
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Rejection of the out-of-band noise
Oversampled A/D
DigitalFilter Decimator
fN fNfB
DfRf'N
2fN 2fN 2f'N
n-bit n1-bit n1-bitSampled-dataAnalog
fB fN fB
1 2 3 4
1 2 3 4
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Delta and Sigma-Delta Modulation
n-bitDAC
n-bitADC
∫
S+
-
AnalogInput
DigitalOutput
Clock
(a) (b)
time
Ampl
itude
maximum slopes
Delta modulators for increasing the effectiveness of the PCM transmission.
But, ... high pass response ...
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From Delta to Sigma-Delta Modulation
n-bitDAC
n-bitADCS ∫d
dt+
-
AnalogInput Digital
Output
Clock
n-bitDAC
n-bitADCS ∫+
-
AnalogInput
DigitalOutput
Clock
(a) (b)
Integration (sigma) of the difference (delta) gives the name Sigma-Delta.
The Sigma-Delta become popular for the shaping of the quantization noise.
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Noise shaping
The key advantage of the architecture is the noise shaping.Differently than a normal oversampled scheme
Noise Shaping A/D
DigitalFilter Decimator
fN fNfB
DfRf'N
2fN 2fN 2f'N
n-bit n1-bit n1-bit
Sampled-dataAnalog
fB fN fB
Is the reduction of noise at given frequencies.If the signal band is at low frequency it is desirable to reduce the noise atlow frequency→ high pass shaping of the noise.
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How to obtain noise shaping?
+
-A(z)
YXADC
DAC
S
YD
(b)
B(z)
+
-A(z)
X
S
B(z)
S
eQY
Encoder
(a)
Place the quantizer in a feedback loop.
The system has two inputs (signal and noise) and one output.
Goal is to have different suitable transfer functions (STF = signal TF, andNTF = Signal TF).
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STF and NTF estimation
[X − Y ·B(z)]A(z) + εQ = Y, (3)
Study in the z-domain (it can be also done in the time-domain)
Y =X ·A(z)
1 +A(z)B(z)+
εQ
1 +A(z)B(z). (4)
Y = X · S(z) + εQ ·N(z) (5)
B(z) can simply be equal to 1; A(z) should be integration-type.
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First Order Modulator
S+
-
AnalogInput
DigitalOutput
z-1
1-z-1S
+
-
z-1
1-z-1S
QuantizedOutput
eQ
X
YEncoder
DigitalOutput
n-bitADC
n-bitDAC
(a) (b)
YDY
X YD
The linear model of the modulator replaces the non-linear quantization bythe linear injection of the quantization noise.
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STF and NTF of the First Order Modulator
H(z) =z−1
1− z−1(6)
Y (z) = {X(z)− Y (z)}z−1
1− z−1+ εQ(z) (7)
Y (z) = X(z) · z−1 + εQ(z)(1− z−1) (8)
Y (z) = X · STF (z) + εQ(z) ·NTF (z). (9)
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The STF is a simple delay (more than what we desire).
The NTF is (1− z−1), that using the z → s transformation becomes
NTF (ω) = 1− e−jωT = 2je−jωT/2ejωT/2 − e−jωT/2
2j
NTF (ω) = 2je−jωT/2sin(ωT/2) (10)
that is a low pass response.
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The power of the shaped noise in a small band B is
V 2n = v2
n,Q
∫ fB0
4 · sin2(πfT )df ' v2n,Q
4π2
3f3BT
2 (11)
V 2n = V 2
n,Qπ2
3
[fBfs/2
]3
= V 2n,Q
π2
3·OSR−3. (12)
Assume to use a DAC that generates the quantized intervals
VDAC(i) = iVref
k; i = 0 · · · k. (13)
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The power of the quantization noise and the one of a sine wave are
V 2n,Q =
V 2ref
k2 · 12; V 2
sine =V 2ref
8, (14)
therefore,
SNRΣ∆,1 =12
8· k2 ·
3
π2·OSR3. (15)
assuming n′ = log2k
SNRΣ∆,1|dB = 6.02 · n′+ 1.78− 5.17 + 9.03 · log2(OSR) (16)
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Table 6.1 - SNR improvement with Multi-level Quantizers
ADC DAC nQ n′ ∆SNRThresholds Levels extra bits [dB]
1 2 1 0 02 3 1 6.023 4 2 1.58 9.544 5 2 12.045 6 2.32 13.976 7 2.58 15.567 8 3 2.81 16.848 9 3 18.03
15 16 4 3.91 23.52
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Example 6.1
Behavioral simulation of a first order modulator
tak
pa
Tu
ii
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Obtained output spectrum (vertical axis is in dB)
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Intuitive ViewsThe output of an integrator is bounded if its input is, on average, zero →the output equals in average the input.
The factor 2 in the NTF indicates a worsening of the noise performancesat high frequency.
Oversampling can be viewed as a staircase with small steps between bigsteps between (resolution increases but linearity remains the same).
D=V /2nFS
D
D + ed,i
D + ed,i+1
(a) (b)
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Therefore, remember the following ...
Warning!
The feedback of a Σ∆ mod-ulator does not relax the DAClinearity. Remind that themethod greatly reduces thenumber of DAC levels but nottheir accuracy requirement!
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Use of 1-bit Quantization
+
--
+
VinF1
F1
F2
F2
+Vref-Vref
DigitalOutput
0 50 100 150 200 250 300-1.5
-1
-0.5
0
0.5
1
1.5
(a)
(b)
C1 C2
DAC
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Second Order Modulator
The use of one ontegrator around the loop is beneficial; it may be that usingtwo is better ...
Two integrators around a loop can be unstable; a dumping is necessary!
S+
-
z-1
1-z-1S
QuantizedOutput
eQ
X YS
+
-
11-z-1
n-bitDAC
n-bitADCS ∫+
-
AnalogInput
DigitalOutput
Clock
(b)
∫S+
One or the other?
-
(a)
P R
Y = R+eQ
QuantizedOutput
YD
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The dumping embracing the quantizer is effective
R =P −Rsτ
→ Y = R+ εQ =P
1 + sτ+ εQ (17)
P − Ysτ
= Y − εQ → Y =P
1 + sτ+
sτεQ
1 + sτ(18)
The study of the second order modulator in the z domain yields:
{[X(z)− Y (z)]
1
1− z−1− Y (z)
}z−1
1− z−1+ εQ(z) = Y (z) (19)
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Y (z) = X(z) · z−1 + εQ(z)(1− z−1)2 (20)
just a delay for the signal and a more effective (second order) shaping forthe quantization noise.
NTF (ω) = (1− e−jωT )2 = −4e−jωT{sin(ωT/2)}2 (21)
that, in a small band B gives
V 2n = v2
n,Q
∫ fB0
16 · sin4(πfT )df ' v2n,Q
16π4
5f5BT
4 (22)
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V 2n = V 2
n,Qπ4
5
[fBfs/2
]5
= V 2n,Q
π4
5·OSR−5 (23)
Again, with k quantization intervals and a full range sine wave at the input.
SNRΣ∆2=
12
8· k2 ·
5
π4·OSR5 (24)
that gives (with n′ = log2k)
SNRΣ∆2|dB = 6.02n′+ 1.78− 12.9 + 15.05 · log2(OSR) (25)
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Circuit Design Issues
The most important limits of the basic blocks used are:
• Offset of the op-amp (or OTA).
• Finite op-amp gain.
• Finite op-amp bandwidth.
• Finite op-amp slew-rate.
• Non-ideal operation of the ADC.
• Non-ideal operation of the DAC.
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The offset of the first integrator is added to the input signal and gives riseto an equal offset at the digital output.
The offset of the second integrator is referred to the input of the modulatorby dividing it by the transfer function of the first block (an integrator). →The high-pass transfer function cancels out the effect.
The offset of the DAC is added to the input and causes, similar to the offsetof the first integrator.
The offset of the ADC is referred to the input by dividing it by the transferfunction of one or more integrators and does not limit the dc operation ofthe modulator. The feature enables the flexibility of positioning the ADCthresholds around the more convenient voltage level.
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Finite Op-Amp Gain
The basic block of a sigma delta modulator is the integrator of a difference.Use the switched capacitor technique we have
+
_
F1
F1F2F2
C1
C2
V1 Vout
-Vout/A0
A0
F1
F2
nT nT+TV2
With OTA (or op-amp) finite gain the virtual ground is not at ground.
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C2Vout(nT + T )
(1 +
1
A0
)= C2Vout(nT )
(1 +
1
A0
)+
+C1
[V1(nT )− V2(nT + T )−
Vout(nT )
A0
](26)
Vout(z − 1)
(1 +
1
A0
)=C1
C2
[V1 − zV2 −
zVout
A0
](27)
Vout
V1 − z−1 V2=C1
C2
[A0
A0 + 1 + C1/C2
]z−1
1− (1+A0)C2C1+C2+A0C2
z−1(28)
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NTF ' (1− zp1 · z−1)(1− zp2 · z−1) (29)
NTF =
(1− z−1A0 + 1
A0 + 2
)2
(30)
10−4 10−3 10−2 10−1 100−160
−140
−120
−100
−80
−60
−40
−20
0
20NTF of a Second Order Σ∆ with Op−Amp Finite Gain
Normalized Frequency
NTF
[dB]
A0=98
A0=998
A0=9998
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The finite gain affects the SNR only if the flat region contributes with asignificant fraction of noise power. The corner frequency is
espT =A0 + 1
A0 + 2(31)
fc =fs
2πln
{1−
1
A0 + 2
}'
fs
2π(A0 + 2)(32)
The finite gain does not affect the SNR if fB >> fc
π(A0 + 2) >> OSR (33)
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Example 6.2
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Comparison of the SNR with Gain 100 and Gain 100,000
A =1000
A =100K0
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OVERSAMPLING AND LOW ORDER SD32
Finite Op-Amp BandwidthIf the effect of the non-dominant poles is negligible, the step response ofthe integrator is an exponential that, for large finite gain A0, is
Vout(t+ nT ) = Vout(nT ) + VstepU(nT )(1− e−tβ/τd) (34)
εb = Vstepe−Tsβ/(2τd) (35)
S+
-
(1-eb,2)z-1
1-z-1S
eQ
S+
-
1-eb,1 1-z-1
Vin Vout
Vout(z) =Vinz
−1(1− εb,1)(1− εb,2) + εQ(1− z−1)2
1− z−1(εb,1 + 2εb,2 − εb,1εb,2) + z−2εb,2(36)
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OVERSAMPLING AND LOW ORDER SD33
Finite Op-Amp Bandwidth
The finite op-amp bandwidth changes the signal and the noise transferfunction because if the denominator with two poles.
The effect is not very relevant when considered alone. The limit is moresignificant when it is considered together the finite gain and the limitedslew-rate.
The study of the limits is conveniently done with behavioral simulators andsuitable behavioral models.
F. MalobertiDATA CONVERTERS Springer2007
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OVERSAMPLING AND LOW ORDER SD34
Finite Op-Amp Slew-Rate
T/2
tslew
tsett1
timeVin(0-)
DVin(0)
DV
0
A B
T/2
tsett2
F1
F1 F2
F2 C
C
F1 F2
tslew =∆Vout
SR− τ. (37)
∆V = SR · τ ; (38)
εSR = ∆V e−(T/2−tslew)/τ (39)
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OVERSAMPLING AND LOW ORDER SD35
Example
Determine the minimum slew-rate required for the op-amps used in a single-bit second-order Σ∆. Study the combined effect of slew-rate and finitebandwidth.
± 1 V fs = 50 MHz, Vin = –6 dBFS.
———————–
The maximum output changes of first and second integrator is 0.749 V and3.21 V; therefore:
SR1 >∆Vout,1
T/2= 74.9V/µs; SR2 >
∆Vout,2
T/2= 321V/µs
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Results of simulations
105
106
107−140
−120
−100
−80
−60
−40
−20
0PSD with SR of the First Op−Amp 200 V/µs
Frequency [Hz]
PSD
[dB]
SNR = 71.9dB, OSR=64Rbit= 11.65 bits,OSR=64
105
106
107−140
−120
−100
−80
−60
−40
−20
0PSD with SR of the First Op−Amp 73 V/ µs
Frequency [Hz]
PSD
[dB]
SNR = 70.3dB, OSR=64Rbit= 11.39 bits,OSR=64
(a) (b)
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ADC Non-ideal Operation
The static and dynamic limitations of a real ADC degrade the modulatorperformances.
ADCout = Vin,ADC + εQ + εADC, (40)
Shaping of the Σ∆ modulator acts on both εQ and εADC . Therefore,εADC < εQ.
DNL and INL of less than 1 LSB is easily verified: the number of thresholdsis small and the dynamic range is large.
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DAC Non-ideal Operation
The DAC errors are not shaped by the NTF : they are added to the inputand transferred to the output through the STF.
A switched capacitor DACs divides a total capacitance into parts. One limitassociated is the kT/C noise.
Since the kT/C noise is white oversampling limits its power in the band ofinterest.
v2n,kT/C =
kT
OSR · Cin<
V 2ref
8 · 22n(41)
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Architectural Design Issues - Integrator Dynamic RangeThe integrator voltage swing depends on signal amplitude and quantizationnoise.
The dynamic range of operational amplifiers and quantizer must accom-modate both the signal and the noise.
Integrator outputs that exceed the dynamic range are clipped thus causinga loss of feedback control.
S+
-
z-1
1-z-1S
eQ
S+
-
11-z-1
(b)(a)
+
_
F1
F1F2F2 Sat
±Vsat
C1
C2
Vin
es,Q
es,2es,1
X YVout
Vvg
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The input capacitance is charged to Qres, the virtual ground starts movingand when the left terminal of C1 reaches zero the fraction QresC2/(C1 +
C2) is transferred into C2 leaving a fractionQresC1/(C1+C2) in the inputcapacitance.
εs =Qres
C1 + C2(42)
εs,1 is transferred to the output multiplied by z−1; εs,2 is shaped by a first-order high-pass transfer function; εs,Q is shaped by the NTF.
Y = Xz−1 + εs,1z−1 + εs,2(1− z−1) + (εQ + εs,Q)(1− z−1)2 (43)
V 2n =
V 2n,1
OSR+ V 2
n,2π2
3 ·OSR3+
[V 2n,Q +
∆2
12
]π4
5 ·OSR5(44)
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ExampleLoss of resolution caused by the hard saturation of the op-amp outputs andthe quantizer.
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Chapter 6
OVERSAMPLING AND LOW ORDER SD42
103 104 105 106−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0PSD with Ideal Integrator
Frequency [Hz]
PSD
[dB]
SNR = 67.6dB @ OSR=64Rbit = 10.94 bits @ OSR=64
103 104 105 106−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0PSD with Saturation of the First Integrator at 1.85
Frequency [Hz]
PSD
[dB]
SNR = 64.4dB @ OSR=64Rbit = 10.40 bits @ OSR=64
103 104 105 106−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0PSD with Saturation of the Second Integrator at 2.5 V
Frequency [Hz]
PSD
[dB]
SNR = 67.5dB @ OSR=64Rbit = 10.91 bits @ OSR=64
103 104 105 106−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0PSD with Saturation in Both Integrators
Frequency [Hz]
PSD
[dB]
SNR = 60.2dB @ OSR=64Rbit = 9.71 bits @ OSR=64
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OVERSAMPLING AND LOW ORDER SD43
−1
0
1
First Integrator Output
Ampl
itude
0 1000 2000 3000 4000 5000 6000 7000 8000
Second Integrator Output
−1.5 −1 −0.5 0 0. 5 1 1.50
10
20
30
40
50
60
70
80
90 First Integrator Output
Voltage [V]
Occ
urre
nces
0
10
20
30
40
50
60
70
80Second Integrator Output
Occ
urre
nces
−1 −0.5 0 0. 5 10
10
20
30
40
50
60
70
80 First Integrator Output
Voltage [V]
Occ
urre
nces
0
20
40
60
80
100
120
140Second Integrator Output
Occ
urre
nces103 104 105 106−200
−180−160−140−120−100−80−60−40−20
0 PSD with Saturation in Both Integrators
Frequency [Hz]
PSD
[dB]
SNR = 77.3dB @ OSR=64Rbit = 12.54 bits @ OSR=64
−1
0
1
Ampl
itude
−1 −0.5 0 0.5 1Voltage [V]
−1.5 −1 −0.5 0 0.5 1 1.5Voltage [V]
0 1000 2000 3000 4000 5000 6000 7000 8000
F. MalobertiDATA CONVERTERS Springer2007
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OVERSAMPLING AND LOW ORDER SD44
Dynamic Ranges Optimization
A suitable dynamic range in the op-amps (or OTAs) is essential for pre-serving the SNR and avoiding harmonic distortion.
The critical op-amp is the one used in first integrator (no shaping).
However, even the second integrator and the quantizer are important.
Carefully estimate the voltage swings and keep them within limits: small toavoid saturation; not so low to distinguish the electronic noise.
The above points affect the choice of the reference value.
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OVERSAMPLING AND LOW ORDER SD45
Scaling as used in switched capacitor filters
S+
-
z-1
1-z-1SS
+
-
11-z-1
(c)
(a)
+
_
F1
F1F2F2
C1
C1
Vin
eQ
Y
F2F2
C3
S+
-
z-1/b1-z-1
SS+
-
1/b1-z-1
(d)
(b)
+
_
F1
F1F2F2
C1
bC1
Vin
Y
bC3
b
Vout,1
Vout,1/b
eQ
F1 F1
F2F2F1 F1
VDAC
VDAC
11 b22
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OVERSAMPLING AND LOW ORDER SD46
Use a different architecture (two delayed integrators).
Chose A and B so that the STF and the NTF are ”good” and the (first) op-amp swing isreduces.
S+
-
B z-1
1-z-1SS
+
-
A z-1
1-z-1
eQ
YX
+-
2 z-1
1-z-1+
-0.5 z-1
1-z-1
Y
XADC
DAC
S SYD
(a)
(b)
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OVERSAMPLING AND LOW ORDER SD47
study with the linear model.
[(X − Y )
Az−1
1− z−1− Y
]Bz−1
1− z−1+ εQ = Y, (45)
Y =X ·ABz−2 + εQ(1− z−1)2
1− (2−B)z−1 + (1−B +AB)z−2. (46)
with B=2 and A = 1/2 the denominator is 1
Y = Xz−2 + εQ(1− z−1)2 (47)
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OVERSAMPLING AND LOW ORDER SD
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OVERSAMPLING AND LOW ORDER SD48
Example 6.5Histograms of the output voltages of the two integrators (A=1/2).
−2 −1 0 1 20
50
100
150First Integrator Output
Voltage [V]
Occ
urre
nces
−4 −2 0 2 40
20
40
60
80
100Second Integrator Output
Voltage [V]
Occ
urre
nces
−2 −1 0 1 20
50
100
150First Integrator Output
Voltage [V]
Occ
urre
nces
−1 −0.5 0 0.5 10
20
40
60
80
100Second Integrator Output
Voltage [V]
Occ
urre
nces
B=2
B=1/2
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OVERSAMPLING AND LOW ORDER SD
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OVERSAMPLING AND LOW ORDER SD49
Dynamic range optimization with multi-bit quantizerUse of feed-forward path.
S+
-2 z-1
1-z-1S
+
-1/2 z-1
1-z-1
Y
X k threshold
k+1 Outputs
DigitalOutput
P
Intuitive view: remember that the input of an integrator (the second) is in average zero.
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OVERSAMPLING AND LOW ORDER SD50
P =(X − Y )z−1
2(1− z−1)= X
z−1(1 + z−1)
2+εQz
−1(1− z−1)
2. (48)
Y = X[z−2 + 2 · z−1(1− z−1)
]+ εQ(1− z−1)2 (49)
P =(X − Y )z−1
2(1− z−1)= X
z−1(1− z−1)
2+εQz
−1(1− z−1)
2. (50)
STF = z−2 + 2(1− z−1); (51)
Notice: The STF is slightly changed (the high pass term can be possibly removed in thedigital domain).
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OVERSAMPLING AND LOW ORDER SD51
Example 6.6Hystogram of the first op-amp output with the feedforward branch (3-bit quantization)
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Spectrum of the output voltage of the first op-amp
Notice the small signal tone (high pass filter) and the first order shaped quantization noise.
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Sampled-data Circuit Implementation
+
_
F1
F1F2F2
C1
C1
Vin F2F2
C2
+
_
C2F1 F1
ADC
DAC
F2
F2
F2
C2
F1
F1
+
_
F1
F1F2
F2
C1
2C1
Vin
F2F2
2C2
+
_
C2
F1F1
ADC
DAC(a)
(b)
F2
The DAC can be realized with a separate SC structure or by sharing the input capacitor.
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OVERSAMPLING AND LOW ORDER SD54
Noise AnalysisThe noise generators are due to the on-resistance of the switches and the noise of theop-amp (described by an input referred noise generator).
F1
F1F2
F2F1
F1F2
F2
+_
+_
CU
2CU
2CU
CUF2
VDIG
VRef-VRef
VDAC
Vin
vn,A12
Ron RonRon Ron
vn,A22
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There are two different circuit configurations during the two phases
It is assumed that at the end of the phase (before sampling) the voltages across capacitorsreach the stationarity.
+_
CU
2CU
2CU
+_
+_
CU
2CU CU
2CUA1 A1 A2
PHASE 2 PHASE 1
(a) (b)
vn,R2
Ron vn,A12
vn,R2
Ron
vn,R2
Ron vn,A12
vn,A22
vn,R2
RonCLCL CL
gm vn,A12 2
1/gm CL
2CU vn,R2
Ron
gm vn,A2 2
CL
Cin vn,R2
Ron
Cf
gm vx2 2 vx
vx vout
vout
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The input referred noise is proportional to 1/gm
v2n,A1 = γA1
4kT
gm,A1; v2
n,A2 = γA24kT
gm,A2(52)
Estimate the transfer functions between noise input and output
HA1,in2 =vn,Cin2
vn,A1=
1
1 + s(τ0 + τ02CU/CL + τR) + s2τ0τR(53)
after sampling
Vn,A1,in2 = γA1kT
CL(54)
another transfer function
HR,in2 =1 + sτ0
1 + s(τ0 + τ02CU/CL + τR) + s2τ0τR(55)
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Vn,R,in2 =kT
2CU(56)
vx =vout(Ron + 1
sCin) + vn,R
1sCf
Ron + 1sCf
+ 1sCin
(57)
gm(vn,A − vx) = voutsCL + (vout − vx)sCf (58)
vCin=CL(vx − vout)
Cin(59)
vCin=CL
Cf
−vn,A + (1 + sτ0)vn,R1 + (τ0/β + τ0Cin/CL + τR)s+ τ0τRs2
(60)
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v2n,1 = 2Ts
[2kT
CU+ γA1kT/CL
]v2n,2 = 2Ts
[kT
CU+ γA1kT/CL + γA2kT/CL
](61)
v2n,3 = 2Ts
[2kT
CADC+ γA2kT/CL
]
v2n,out = v2
n,1|z−2|2 + v2n,2
∣∣2z−1(1− z−1)∣∣2 + v2
n,3
∣∣(1− z−1)2∣∣2 (62)
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Use of a transistor level simulator
on
HR,in2
HA1,in2
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Summing up. the various noise generators cause, after the sampling, a noise voltagewhich spectrum is white (over the Nyquist interval).
It is necessary to distinguish between noise contribution at the end of phase 1 and at theend of phase 2.
All the noise terms are uncorrelated and must be superposed quadratically.
Table 6.2 - Noise Power Terms of the Second Order Σ∆ Modulator
Phase Source V 2n1 V 2
n2 V 3n1
[V 2] [V 2] [V 2]Φ2 4kTRon kT/CU kT/(2CU) kT/CADCΦ2 γAi4kT/gm – γA1kT/CL γA2kT/CLΦ1 4kTRon kT/CU kT/(2CU) –Φ1 γAi4kT/gm γA1kT/CL γA2kT/CL –
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Noise at the output of the modulatorAfter the sampling the noise is transferred to the output with a transfer function that de-pends on the injection point.
S+
-
2z-1
1-z-1S
YS
+
-
1/2 z-1
1-z-1
vn,1 vn,2 vn,3
DAC1 DAC2
ADC
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Quantization Error and DitheringΣ∆ modulators are good for busy signal (approximating the quantization error with anoise is acceptable).
Constant or very slow inputs can give rise to repetitive patterns (idle channel tones orpattern noise.).
0 50 100 150−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Quantization Error
time
Ampl
itude
37
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A key goal is to avoid repetitive patterns that determine tones that can fall in the band ofthe signal. The amplitude of tones limits the SFDR.
The use of high-order modulators is beneficial.
Other solutions follow the ... ...................
Call upUse multi-bit quantizers or dither-
ing to destabilize the tonal behaviorof Σ∆ modulators especially whenthe input may contain a dominant dccomponent.
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Dither is a suitable signal capable to destroy the limit cycles.
Dither must be effective against the tones and should not alter the signal.
Inject a sine wave or a square wave whose frequency is out of the signal band. (Theamplitude of the dither must be as low as possible.)
Noise-like signal whose contribution does not degrade the SNR.
ModulatorS+
+
XS
+
-S
+-
Modulator S+
+
XS
+
-S
+-
dith dith
eQ eQ
Y Y
(a) (b)
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Single-bit or Multi-bit?Disadvantages of using single-bit quantizers.
High SNR with a 1-bit Σ∆ entails the use of high order modulators (design of a stablearchitecture or high OSR).Bandwidth of the op-amps (or OTAs) higher than the clock frequency.The usable reference voltages of 1-bit modulators is a small fraction of the supply voltage.Assume that the linear region of the op-amp is αVDD and that a−6 dBFS sine wave givesrise to a ±βswingVref maximum swing at the first integrator
|Vref | <αVDD
2βswing(63)
The slew-rate of the op-amp must ensure an accurate settling. The output changes of thefirst integrator (whose gain is G) can be 2∆.
SR =2G(VRef − Vov)
γTs/2. (64)
Iout =2VRef(Cin + CL)
γTs/2. (65)
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Disadvantages of using multi-bit quantizers.In multi-bit the analog section is more complicated than the single bit counterpart.The multi-bit DAC is normally a capacitive MDAC with, normally, the subtraction and theDAC functions obtained by the same capacitive array.
+
--
+
Vin
C2
-VrefVref
C1/4C1/4C1/4C1/4
1
1
2
2a 2b 2c 2d2e 2f 2g 2h1 1 1
t1
t2
t3
t4
2
2d
2c
2b
2a t1
t2
t3
t4
2
2h
2g
2f
2e
(a)
(b)
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The input capacitance C1 is divided into equal elements, pre-charged to the input signalduring phase Φ1 and, during phase Φ2, under the control of the thermometric codest1, · · · , t4, connected to +Vref or −Vref .
Sharing of the same array for the input injection and the DAC function (also used for asingle-bit architecture) reduces the feedback factor of the OTA.
The charge delivered by the reference voltage generator is a non-linear function of theinput signal
QRef(n) = k(n)[VRef − Vin(n)
](66)
Output resistance of the reference generator very small for avoiding distortion.
and, also, ....
MATCHING ACCURACY OF THE CAPACITANCES OF THE DAC MUST BE VERYHIGH (TO ENSURE THE EXPECTED RESOLUTION)
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Wrap-upThe limited benefit of the oversampling technique can be enhanced by shaping the quan-tization noise. The spectrum is reduced in the signal band and, possibly augmentedout-band.
A high-pass filtering of the quantization noise is achieved by closing the quantizer in afeedback loop.
The transfer function of the signal is such that the low-frequency components are un-changed. The noise transfer function significantly attenuates the in-band region.
The performances of real Σ∆ modulators greatly depend on the limitations due to thereal circuit.
First-order and second-order schemes with single-bit or multi-bit quantizers have beenstudied so far.
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