technical university tallinn estonia 1 otsustusdiagrammide kasutamisest digitaalsüsteemide...
TRANSCRIPT
Technical University TallinnESTONIA 1
Otsustusdiagrammide kasutamisest digitaalsüsteemide diagnostikas
Raimund Ubar
TTÜ, Arvutitehnika instituut
Tartu Ülikool, 23. mai 2003
Technical University TallinnESTONIA 2
Ülevaade:• Digitaalsüsteemide diagnostika põhiülesanded• Otsustusdiagrammid: BDD ja SSBDD• Boole’i operatsioonid (SS)BDD-dega• SSBDD-de omadused• Kõrgtaseme otsustusdiagrammid (DD-d)
– register-edastuste tase– käsusüsteemi tase
• Mitmedimensionaalsed otsustusdiagrammid
Otsustusdiagrammide digitaalsüsteemide diagnostika
Technical University TallinnESTONIA 3
Introduction – Test Tools
Test
System
Fault table
System model
Test generation
Fault simulation
Test result
Fault diagnosis
Go/No go Located defect
Test experiment
Test tools
Technical University TallinnESTONIA 4
Introduction – Test Tasks
Fault Diagnosis and Test Generation as direct and reverse mathematical tasks:
dy = F(x1, ... , xn) F(x1 dx1 , ... , xn dxn)
dy = F(X, dX)
Direct task:
Test generation: dX, dy = 1 given, X = ?
Reverse task:
Fault diagnosis: X, dy given, dX = ?
Fault simulation: X, dy = 1 given, dxk = ?
Fault Simulation is a special case of fault diagnosis
Technical University TallinnESTONIA 5
Binary Decision Diagrams
• 1959 - Lee C.Y. - Description of BF by graph-like structures• 1967 - Ehrenfeucht A., Orlowska E - Fast evaluation of BE• 1971 - Schneider B.N. - Representing BF by graphs (Abstract) > AG• 1974 - Dipl. Thesis, TTU (Vaher/Ubar) - Fast evaluation of BE• 1975 - Breitbart Y, Reiter A. - Fast evaluation of BE (Compiler design)• 1976 - Ubar R. - Test generation > AG• 1976 - Kuzmin V.A. - Complexity evaluation of BF by BP• 1977 - Kuznetsov O.P. - Realization of BF by programmes• 1977 - Akers S.B. - Test generation, introduced the name BDD• 1981 - Thayse A. - BDDs in other fields: CAD, program optimization, AI• 1986 - Bryant R.E. - manipulation of BDDs• 1990 - Bryant R.A. - the first BDD package
Technical University TallinnESTONIA 6
Binary Decision Diagrams
x1
x2
y
x3
x4 x5
x6 x7
0
1
7654321 )( xxxxxxxy Simulation:
7654321 xxxxxxx0 1 1 0 1 0 0
1y
Boolean derivative:
15427613
xxxxxxx
y
1
0
Functional BDD
Technical University TallinnESTONIA 7
Binary Decision Diagrams
D
C
q c
q’
D
S
C
q
BDDs for flip-flops
R
0
')'(
SR
qcRqScq
c
q’
S
R q’
R
U
D Flip-Flop
RS Flip-Flop
JK Flip-Flop
S
J
q
R c
q’
S
R q’
C
KK
J
U - unknown value
Technical University TallinnESTONIA 8
Elementary BDDs
Elementary BDDs:
1
x1x2x3
y x1 x2 x3&
x2x3
y x1
x1
x2
x3
1x1x2x3
y x1 x2 x3
+x1x2x3
y
x1
x2
x3
y x2 x3
Adder
NOR
AND
OR
Technical University TallinnESTONIA 9
Building a SSBDD for a Circuit
1
&
&x1
x2
x3
x21
x22y
a
b
322211 xxxxbay
a by
a x1
x21
b x22
x3
ay x22
x3
y x22
x3
x1
x21
DD-library:
Superposition of DDs
Superposition of Boolean functions:
Given circuit:
Compare to
SSBDD
Structurally Synthesized BDDs:
b a
Technical University TallinnESTONIA 10
Boolean Operations with BDDs
AND-operation:
1
&
&x1
x2
x3
x21
x22
y
a
b
1
&
&x5
x6
x51
x52
c
d
x4
g
e
y = e g x3
x1
x21
x22
x6
x4
x51
x52
y
OR-operation:
x3
x1
x21
x22y
x6
x4
x51
x52
y = e g
Technical University TallinnESTONIA 11
Boolean Operations with BDDs
Boolean function: Inverted function:
Dual function: Inverted dual function:
y = x1x2 x3 y = x1x2 x3 = (x1 x2) x3
x1 x2
x3
y x1 x3
x2
y
x1 x3
x2
y*
y*= (x1 x2) x3 y * = x1x2 x3
x1 x2
x3
y *
Technical University TallinnESTONIA 12
BDD and DNF/KNF
Boolean function: y = x1x2 x3 (x4 x5x6)
x1 x2
x3
x5 x6
x4
1
y
x3x5x6 = 1
x1 x2
x3
x5 x6
x4
y
x1x4x5 = 1
0
Each 1-path represents a term in the DNF, each 0-path represents a term in the KNF
Technical University TallinnESTONIA 13
Transformation Rules for SSBDDs
Commutative law:
y = x1 x2= x2 x1x1
x2
y x2
x1
y
Idempotent law:
Exchange of nodes:
BOOLEAN ALGEBRASSBDD
Node passing:
x1
x1
y
x1
x2
y y = x1 x1 x2 = = x1 x2
x2
x1
=
=
Technical University TallinnESTONIA 14
Transformation Rules for SSBDDs
Absorption law:
BOOLEAN ALGEBRASSBDD
Node passing:
x1
x1
y y y = x1 x1x2 = x1
x2
x1
x1 x2
=
Distributive law:x1
x1
y
x3
=x2 x1y
x3
x2
x1
y = x1x2 x1x3= = x1(x2 x3)
Technical University TallinnESTONIA 15
Transformation Rules for SSBDDs
Assotiative law:
BOOLEAN ALGEBRASSBDD
Superposition:
x1
z
y
y = x1 (x2 x3) = = (x1 x2) x3
=x2
x3
z
x1y
x2
x3
z
x3
y
x1
x2
z=
Technical University TallinnESTONIA 16
Transformation Rules for BDDs
Change-over switching of nodes:
x1
x3
y x2 x1
x2
y x3
=
Joint use of subgraphs:
x1
x2
y x3
=x2
x1
x2
y x3
Removing subgraphs:
x1
x1
y x2
=x3
x1y x2
x3
=
Technical University TallinnESTONIA 17
Representing by SSBDD a Circuit
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
6 73
1
2
5
7271
y
0
1
y = cyey = cy ey = x6,e,yx73,e,y deybey
y = x6x73 ( x1 x2 x71) ( x5 x72)
Structurally synthesized BDDfor a subcircuit (macro)
To each node of the SSBDD a signal path in the circuit corresponds
Technical University TallinnESTONIA 18
SSBDDs vs. BDDs
Advantages of SSBDDs compared to the BDDs:• Complexity explosion is avoided
– The number of nodes is linear with the circuit size (determined by the number of paths in macros)
• Test-specific structural features can be represented– Each node represent a signal path in the circuit– Faults of the circuit are directly represented in SSBDDs– Circuit’s dynamic (hazards, risk, delays) can be investigated with SSBDDs
• Processing speed can be increased due to special properties of SSBDDs– Test generation (search space can be reduced)– Fault simulation (the speed of fault analysis can be increased)– Fault diagnosis (minimization of experiments easily controlled)
Disadvantage: SSBDDs cannot be minimized
Technical University TallinnESTONIA 19
SSBDDs vs. BDDs
Increasing the Speed of Test Generation with SSBDDs
N A
B
Theorem:
In SSBDD there exists always a path between the two successors A and B of N,either from A to B or from B to A
1
2 3
4
5
9
6 7 8
11
10
0
1
Breake search here
Task: Activate a path to 1
Property of SSBDD:
Result: Tracing is forced in nodes 1,9,10 Output 0 Another trials possible from 2,3,4 Not needed
Technical University TallinnESTONIA 20
SSBDDs vs. BDDs
Increasing the Speed of Fault Simulation with SSBDDs
Theorem:
If a path in SSBDD is activated by a test pattern to 0 (or 1), then no faults can be detected by this pattern at nodes left in the oposite direction 1 (or 0)
&
&
&
&
&
&
&
1
2
3
4
5
6
7
71
72
73
a
b
c
d
e
y
Macro
Example:
6 73
1
2
5
7271
y
1
The activated path is shown in boldThe output value is 1No need of fault simulation in nodes 6 and 1
Technical University TallinnESTONIA 21
SSBDDs vs. BDDs
Increasing the Speed of Fault Location with SSBDDs
Theorem:
If a path in SSBDD is activated to 0 (or 1),and an error isobserved on the output,then no faultsat nodes leftin oposite direction 1 (or 0)can be the causes of the error
Errordetected
Error signal traced
C
Circuit under guided probing:
...Where to continue pinpointing?
SSBDD for the component C:
1
2 3
4
5
6 8 1
7
The activated path is shown in boldThe output value is 0Faults can be detected only in nodes 1,6,7
Technical University TallinnESTONIA 22
SSBDDs vs. Gate-Level Models
Advantages of SSBDDs compared to the Gate-Level Models:• Complexity reduction
– Faults domain: each node represent all the faults of the corresponding signal path (fault collapsing)
– Time domain: each node represent the delay of the corresponding signal path
• Hierarchical approaches are easy– SSBDD for a subcircuit can be represented as a macro
– No special manipulation procedures for different macros are needed
– No model libraries for different tools are needed
Technical University TallinnESTONIA 23
Extentions of BDDs• 1980 - Multi-Terminal DDs for uncertainty in sequential circuits (1993)
– Automatika I Telemehanika, No5, 1980
• 1981 - Word-Level DDs for Data-Paths– Nachrichtentechnik-Elektronik 31 (1981, H.1)
• 1983 - DDs with multi-output internal nodes– Proceedings of TTU No. 550
• 1983 - Vector DDs for output behaviour of microprocessors– Fault-Tolerant Computing Symposium, Milano
Recent papers on high-level DDs:• R.Ubar. Test Synthesis with Alternative Graphs. J.of IEEE Design and Test of Computers. Spring, 1996, pp.48-
59• R.Ubar. Combining Functional and Structural Approaches in Test Generation for Digital Systems. J. of
Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38, pp.317-329, 1998
• J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram
Representations. J. of Electronic Testing. Kluwer Acad. Publ. Vol. 16, No. 3, pp. 213-226, 2000. • R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with DDs.
IEEE ISCAS’2000 Conf., Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.
Technical University TallinnESTONIA 24
Generalization of MTBDDs for FSMs
1/0
3/0
5/0
6/1
4/1
2/1
x1 x1
x2 x2
x1
x1
Res
Res q’ x1
3.0
x2 4.1
5.0
6.1x1
1.0
*.0
q.y
1
1 1
2
3
4
5
6
*
3 42.1
5
6
8
9
10
12
11
13
7
1.02
0
0
0
1
1
1
State Transition Diagram:
New features:• representing vectors • multi-output internal nodes• multi-terminal BDDs
Technical University TallinnESTONIA 25
High-Level Decision Diagrams
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Superposition of High-Level DDs:
A single DD for a subcircuit
R2
R2 + M3
Instead of simulating all the components in the circuit, only a single path in the DD should be traced
M1
M2
Technical University TallinnESTONIA 26
Faults and High-Level Decision Diagrams
RTL-statement:
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Terminal nodes
RTL-statement faults: data storage, data transfer, data manipulation faults
Nonterminal nodes
RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding,control faults
K: (If T,C) RD F(RS1,RS2,…RSm), N
Technical University TallinnESTONIA 27
High-Level Decision Diagrams
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
y3
0 y2
2
A
2R’2y1
R’1
F(B,R’
3)
AR’1
0
0
Y,R 3 R2
0 0
1 12
2
0
3
R1
C1
2
0
C+R’
2
R’3 R’2
y1 R1 Function0 #0 Reset1 R’1 Hold2 F(B,R’3) Specialy2 R2 Function0 #0 Reset1 R’2 Hold2 A Load3 2R’2 Shifty3 Y,R3 Function0 #0 Reset1 R’3 Hold2 C+R’2 Adder
C FunctionAR’1 Multiplier
Register-Level Data Path:
Technical University TallinnESTONIA 28
High-Level Decision Diagrams
y30
C R’2
C
y2
2222
A
2R’2
y1
R’1
R’3 B
F(B,R’3)
A
A
AR’1
0
0
0
R’2
Y,R3 R20 0
1 1
0
0
0
22
0
3
R1
C
R’1
R’1
1
0
0
1
02
01
0 1
1
C+R’2
R’3 R’2
R’1
Representing transparency functions in Decision Diagrams
+ R3
R2
F R1
A
BC
Y
y2
A
y3
y1 s
Technical University TallinnESTONIA 29
DD Synthesis from Behavioral Descriptions
BEGINMemory state: MProcessor state: PC, AC, AXInternal state: TMPInstruction format: IR = OP. A. F0. F1. F2.Execution process: EXEC:
BEGIN DECODE OP (
0: AC AC + MA1: M[A] AC, AC 02: M[A] M[A]+ 1,
IF M[A]= 0 THEN PC PC + 13: PC A......................................7: IF F0 THEN AC AC + 1
IF F1 THEN IF AC = 0 THEN PC PC + 1 IF F2 THEN (TMP AC, AC AX, AX TM’)
ENDEND
Procedural description of a microprocessor
Technical University TallinnESTONIA 30
DD Synthesis from Behavioral Descriptions
Start
AC = AC + M [A] AC = AC + 1PC = A
M [A] = AC, AC = 0
M [A] = M [A] + 1
PC = PC + 1
1
2
3
4
6
5
AC = AX, AX = AC
7
PC = PC + 1
AC = AX, AX = AC
8
9
AC = AX, AX = AC
10
11
OP=0
OP=1
OP=2
OP=3...
OP=7
M[A]=0M[A]=1
F0=1
F0=0
F1=1F1=0
F2=0
F2=1
AC=0AC0
F2=1F2=0 F2=1
F2=0
Symbolic execution tree:
Technical University TallinnESTONIA 31
DD Synthesis from Behavioral Descriptions
No Input assertions Output assertions1 OP = 0 AC = AC+ M A
2 OP = 1 M A = AC, AC = 03 OP = 2, M A + 1 = 0 M A = M A +1, PC = PC + 14 OP = 2, M A + 1 0 M A = M A + 15 OP = 3 PC = A6 OP = 7, FO=0, F1=0, F2=0 NO CHANGE7 OP = 7, FO=0, F1=0, F2=1 AC = AX, AX = AC8 OP = 7, FO=0, F1=1, AC=0, F2=1 AC = AX, AX = AC9 OP = 7, FO=0, F1=1, AC=0, F2=0 NO CHANGE
Generation of nonprocedural descriptions via symbolic execution
Terminal contexts
Technical University TallinnESTONIA 32
DD Synthesis from Behavioral Descriptions
Input assertions Output assertions
OP = 0 AC = AC+ M A
OP = 1 M A = AC, AC = 0OP = 2,M A + 1 = 0
M A = M A +1,PC = PC + 1
OP = 2,M A + 1 0
M A = M A + 1
OP = 3 PC = AOP = 7,FO=0, F1=0, F2=0
NO CHANGE
OP = 7,FO=0, F1=0, F2=1
AC = AX, AX = AC
OP = 7, AC=0,FO=0, F1=1, F2=1
AC = AX, AX = AC
OP = 7, AC=0,FO=0, F1=1, F2=0
NO CHANGE
Decision Diagram for AC
OPAC AC+M [A]
#0
F0 F2
AC
AX
AC+1
0
1
2,3
7 0 0
1 1
Technical University TallinnESTONIA 33
High-Level Decision Diagrams
ABC
M
ADR
MUX1
MUX2
CC
COND
Control Path
Data Path
/
FF
yx
z
z1
z2
Digital system:A
01
0q
xA
B + C
A + 1
13 xC C + B
04 xA A + B+ C
B
04
1q
xA
B + C
B
C
14
2q
xA
1
0xB A + B
C
0 xC
xA1
xC3 0
3,4
02
q
1
01
0q 1
4xA
2
1
5xB
3
DD-model for a digital system:
Technical University TallinnESTONIA 34
High-Level Decision Diagrams
Digital system:A
01
0q
xA
B + C
A + 1
13 xC C + B
04 xA A + B+ C
B
04
1q
xA
B + C
B
C
14
2q
xA
1
0xB A + B
C
0 xC
xA1
xC3 0
3,4
02
q
1
01
0q 1
4xA
2
1
5xB
3
Begin
A = B + C
xA
A = A + 1 B = B + C
xA
B = B C = C
xB
C = C
xC
A = A +B + C
xC
C = A + B A = C + B
END
0
0
0
0
0
1
1
1
1
1
s0
s1
s2
s3
s4
s5
DD-model for a digital system:
Technical University TallinnESTONIA 35
Test Generation for Processors
I1: MVI A,D A IN
I2: MOV R,A R A
I3: MOV M,R OUT R
I4: MOV M,A OUT A
I5: MOV R,M R IN
I6: MOV A,M A IN
I7: ADD R A A + R
I8: ORA R A A R
I9: ANA R A A R
I10: CMA A,D A A
High-Level DDs for a microprocessor (example):
Instruction set:
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Technical University TallinnESTONIA 36
Test Generation for Processors
High-Level DD-based structure of the microprocessor (example):
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
OUT
R
A
IN
I
Technical University TallinnESTONIA 37
Test Generation for Processors
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Scanning test program for adder:
Instruction sequence T = I5 (R)I1 (A)I7 I4for all needed pairs of (A,R)
OUT I4
A I7
A
R
I1
IN(2)
IN(1)
R I5
Time:t t - 1 t - 2 t - 3
Observation Test Load
Technical University TallinnESTONIA 38
Test Generation for Processors
I R3
A
OUT4
I A2
R
IN5
R
1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Conformity test program for decoder:
Instruction sequence T = I5 I1 D I4
for all DI1 - I10 at given A,R,IN
Data generation:IN 110 A 101
Data
R 110 I1, I6 IN 110
I2, I3 I4, I5 A 101 I7 A + R 1011 I8 A R 111 I9 A R 00
Functions
I10 A 010
Data IN,A,R are generated so that the values of all functions were different
Technical University TallinnESTONIA 39
Vector Decision Diagrams
3,4
02
q
1
01
0q 1
4xA
2
15xB
3
A01
0q
xA
B + C
A + 113 xC C + B
04 xA A + B+ C
B04
1q
xA
B + C
B
C
14
2q
xA
10xB A + B
C
0 xC
xA1
xC3 0
M=A.B.C.q
Vector Decision Diagrams:
1
1
q
xA
0qA
i B’ + C’
#1
qB
i B’ + C’
#2
0qA
i A’ + 1
#4
2
1
xB
qC
i C’
#3
0qC
i A’ + B’
#5
3
1
xC
qA
i B’ + C’
#5
0qC
i A’ + B’
#5
4
1
xC
qC
i C’
#5
0
B
Ai A’ + B’+C’xA
0
q#5
B’
qB
i B’
#5
Concurrent simulation in space:
j – adressing variable
Technical University TallinnESTONIA 40
Two-Dimensional Decision Diagrams
I1 I3 t i1
i1
PC + 1
PC + 2
0 1 2
3
AB
AB
A1
A2
OUT = AB.DB (t)
t0, 2 i1
PC + 1
PC + 2
2 DB
AB
I22
t1, 3 i1
2AB
t4
i1 L
INP
4 DB
AB
A1
A2
2
3
i1
INP + 1
5 DB
AB
H
Instruction: SHLD I1.I2.I3= 0.4.2
(DB(t=3).DB(t=2)) L
((DB(t=3).DB(t=2)) + 1) H
I1 I2 I3
0 1 2 4 5 7
DDs for representingmicroprocessor output behaviour
i2 DB(t=2)
DB(t=3)
L
H
INP (H,L)
Concurrent simulation:
in space: i – adressing variable in time: t – adressing variable
i
t
space
time