technical university tallinn, estonia test generation gate-level methods functional testing:...

Technical University Tallinn, ESTONIA

Test generation

Gate-level methods Functional testing: universal test sets Structural test generation

Path activation conception Algorithms: D, Podem, Fan Test generation for multiple faults Test generation for sequential circuits

Random test generation Genetic algorithms for test generation

High-level and hierarchical methods Test generation for digital systems Test generation for microprocessors


Test generationUniversal test sets

1. Exhaustive test (trivial test)2. Pseudo-exhaustive test

Properties of exhaustive tests1. Advantages (concerning the stuck at fault model):

- test pattern generation is not needed- fault simulation is not needed- no need for a fault model- redundancy problem is eliminated- single and multiple stuck-at fault coverage is 100%- easily generated on-line by hardware

2. Shortcomings:- long test length (2n patterns are needed, n - is the number of inputs)- CMOS stuck-open fault problem


Test generation

Pseudo-exhaustive test sets:– Output function verification

• maximal parallel testability• partial parallel testability

– Segment function verification

Output function verification

4

4

4

4

216 = 65536 >> 4x16 = 64 > 16

Exhaustivetest

Pseudo-exhaustivesequential

Segment function verification

F &1111

01010011

Pseudo-exhaustive

parallel


Functional testing: universal test sets

Output function verification (maximum parallelity)

c0 a0 b0 c1 a1 b1 c2 a2 b2 c3 …1 0 0 0 0 0 0 0 0 0 02 0 0 1 0 0 1 0 0 1 03 0 1 0 0 1 0 0 1 0 04 0 1 1 1 0 0 0 1 1 15 1 0 0 0 1 1 1 0 0 06 1 0 1 1 0 1 1 0 1 17 1 1 0 1 1 0 1 1 0 18 1 1 1 1 1 1 1 1 1 1

Exhaustive test generation for n-bit adder:

Good news:Bit number n - arbitraryTest length - always 8 (!)

0-bit testing 2-bit testing1-bit testing 3-bit testing … etc

Bad news:The method is correctonly for ripple-carry adder


Testing carry-lookahead adder

General expressions:

iii baG iiiii babaP 1 nnnn CPGC

211211 )( nnnnnnnnnnnn CPPGPGCPGPGC

n-bit carry-lookahead adder:

01231232333 CPPPGPPGPGC

),,( 011011011110111 CbafCbaCbabaCPGC

01111222233330123 ))()(( CbabababababaCPPP


Testing carry-lookahead adder

01111222233330123 ))()(( CbabababababaCPPP

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 11 0 0 1 1 1 1 1 1 00 1 1 0 1 1 1 1 1 01 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 1 1 01 1 1 1 0 1 1 0 1 01 1 1 1 1 0 0 1 1 01 1 1 1 1 1 0 0

For 3-bit carry lookahead adder for testing only this part of the circuit at least 9 test patterns are needed (i.e. pseudoexhaustive testing will not work)

Increase in the speed implies worse testability

Testing 0

Testing 1

R


Test generation

Output function verification (partial parallelity)

x1

x2

x3

x4

F1(x1, x2)F2(x1, x3)F3(x2, x3)F4(x2, x4)F5(x1, x4)F6(x3, x4)

0011- -

010101

010110

00-11-000111

0011- 0F1

F3

F2

F4

F5

Exhaustive testing - 16Pseudo-exhaustive, full parallel - 4Pseudo-exhaustive, partially parallel - 6


Structural Test Generation

• A fault a/0 is sensitisized by the value 1 on a line a

• A test t = 1101 is simulated, both without and with the fault a/0

• The fault is detected since the output values in the two cases are different

• A path from the faulty line a is sensitized (bold lines) to the primary output

&

&

0

AB

C

D

11

0

1

0

1

1

a

1 01 0

0 1

1

0 1

Structural gate-level testing: fault sensitization:


Structural Test GenerationStructural gate-level testing: Path activation

&

&

&

&

&

&

&

12

345

6

7

71

72

73

a

b

c

d

e

y

Macro

DDD

D D

11

1

1

Fault sensitisation:x7,1= D

Fault propagation:x2 = 1, x1 = 1, b = 1, c = 1

Line justification:x7= D = 0: x3 = 1, x4 = 1b = 1: (already justified) c = 1: (already justified)

1))(( 721212,753,761,7

xxxxxxxxxxy

))(( 2,751,7213,76 xxxxxxxy Symbolic fault modeling:D = 0 - if fault is missingD = 1 - if fault is present

11

11

Test pattern


Test generationTest generation for a bridging fault:

&

&

&

&

&

&

&

12

345

6

7

71

72

73

a

b

c

d

e

y

Macro

DDD

D D

11

1

1

Fault manifestation:Wd = x6x7= 1: x6 = 0, x7 = 1, x7,1= D

Fault propagation: x2 = 1, x1 = 1, b = 1, c = 1Line justification:b = 1: x5 = 0

1

)())((

76521

76212,753,761,7

xxxxx

xxxxxxxxWxy d

yComponent F(x1,x2,…,xn)

Defect Wd

Activate a pathBridge between leads 73 and 6

Wd


Test generationMultiple path fault propagation:

1

1

1

1

1

1

1

1

x1

x2x3x4

yD

DD

00

1

1

1

1

1

1

1

1

x1

x2x3x4

yD

DD

00

D

D

10

0

Single path activation is not possible

Three paths simultaneously activated

DD


Test generationD - algorithm (Roth, 1966):

Select a fault site, assign DPropagate D along all available paths using D-cubes of gatesBacktracking, to find the inputs needed

123

4

D11

D

Example:1 2 3 4D 1 1 D1 D 1 D1 1 D D

123

4D1

D1

Fault site

PropagationD-cubesfor AND-gate


Test generationD - algorithm:

Singular cover for C = NAND (A,B):

a b c1 1 0x 0 10 x 1

Propagation D-cubes for C = NAND (A,B):

a b c1 D D D 1 DD D D

Intersection of cubes:Let have 2 D-cubes

A = (a1, a2,... an)B = (b1, b2,... bn)

where ai, bj 0,1,x,D,D)1) x ai = ai

2) If ai x and bi x then ai bi = ai if bi = ai or ai bi = otherwise3) A B = if for any i: ai bi =

Primitive D-cubes for NAND and c 0: a b c 0 x D x 0 D

&

&

&

1

3

2

5

4

6

Propagation of D-cubes in the circuit:

1 2 3 4 5 6D-drive:Primitive cube for x2 1 DPropagate D through G4 1 D D Propagate D through G6 1 D D 1 D Consistency operation:Intersect with G5 1 D 0 D 1 D


Test generationMultiple path fault propagation by DDs:

1

1

1

1

1

1

1

1

x1

x2x3x4

yD

DD

00

D

D

10

0

x21

x11 x31

x12

x22 x32

x41

x23 x33

x3

x24 x42

y

Functional DD

Structural DD

x2

x1

y

x3 x4

x1 x4 x3


Test generationPODEM - algorithm (Goel, 1981):

1. Controllability measures are used during backtracking

Decision gate:The “easiest” input will be chosen at first

Imply gate:The “most difficult” input will be chosen at first

2. Backtracking ends always only at inputs3. D-propagation on the basis of observability measures

& 0

& 1

0

1


Test generation FAN - algorithm (Fujiwara, 1983):

1. Special handling of fan-outs (by using counters)

PODEM: backtracking continuesover fan-outs up to inputs

FAN: backtracking breaks off,the value is chosenon the basis of values in counters

2. Heuristics is introduced into D-propagation

PODEM: moves step by step (without predicting problems)

FAN: finds bottlenecks and makes appropriate decisionsat the beginning, before starting D-propagation

1 (C = 6)

0 (C = 3)

0 (C = 2)

1

Chosen value:


Example: Test Generation with SSBDDs

&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

1 1 0 - 1

Testing Stuck-at-0 faults on paths:

Test pattern:

x11

x21

x12x31

x13

x22x32

Tested faults: x120, x210

x11y x21

x12 x31 x4

x13x22 x32

1

0



x11y x21

x12 x31 x4

x13x22 x32

&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

1 0 1 1 1

Test pattern:

1

0

Tested faults: x120, x310, x40




x11y x21

x12 x31 x4

x13x22 x32

&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

0 1 1 0 1

Test pattern:

1

0


Not tested: x131




&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

0 0 1 1 0


Test pattern:

x11

x21

x12x31

x13

x22x32


Not tested: x111

x11y x21

x12 x31 x4

x13x22 x32

1

0

1

1



&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

1 0 0 1 0


Test pattern:

x11

x21

x12x31

x13

x22x32

Tested faults: x211, x311, x130

x11y x21

x12 x31 x4

x13x22 x32

1

0

1

1



&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

1 0 1 0 0


Test pattern:

x11

x21

x12x31

x13

x22x32

Tested fault: x41

x11y x21

x12 x31 x4

x13x22 x32

1

0

1

1

Not yet tested fault: x321


Transformation of BDDs

x11y x21

x12 x31 x4

x13x22 x32

x1y x2

x4 x3

x2

SSBDD:

Optimized BDD:

x1y x2

x12 x31 x4

x13x22 x32

x1y x2

x12 x3 x4

x13x22 x32

x1y x2

x4 x3

x2 x3BDD:


Example: Test Generation with BDDs

&

&

&

1

&

x1x2

x3x4

y

x1 x2 x3 x4 y

D 1 0 - D

Testing Stuck-at faults on inputs:

Test pair D=0,1:

x11

x21

x12x31

x13

x22x32


x11y x21

x12 x31 x4

x13x22 x32

0

1x1y x2

x4 x3

x2

SSBDD:

BDD:


Test generation

Test generation by using disjunctive normal forms

32143121 xxxxxxxxy

x1 x2 x1 x3 x4 x1 x2 x3 y x1 x2 x3 x40 1 0 0 1 1 1 0 0 0 1 0 11 0 1 0 1 0 0 0 0 1 0 0 10 0 0 1 1 1 0 1 0 0 0 1 11 0 1 1 0 0 0 1 0 1 0 1 01 1 1 1 0 1 1 1 No test1 1 1 0 0 1 0 1 1 1 01 0 1 1 1 0 0 1 1 1 0 1 10 1 0 1 1 1 1 1 0 1 1


Multiple Fault Testing

Multiple faults fenomena:• Multiple stuck-fault (MSF) model is a straightforward extension of the

single stuck-fault (SSF) model where several lines can be simultaneously stuck

• If n - is the number of possible SSF sites, there are 2n possible SSFs, but there are 3n -1 possible MSFs

• If we assume that the multiplicity of faults is no greater than k , then the number of possible MSFs is

ki=1 {Cn

i}2i

• The number of multiple faults is very big. However, their consideration is needed because of possible fault masking


Multiple Fault TestingFault masking• Let Tg be a test that detects a fault g • A fault f functionally masks the fault g iff the multiple fault { f, g } is not

detected by any pattern in Tg

The test 011 is the only test that detects the fault c 0

The same test does not detect the multiple fault { c 0, a 1} Thus a 1 masks c 0

• Let Tg’ T be the set of all tests in T that detect a fault g • A fault f masks the fault g under a test T iff the multiple fault { f , g } is not

detected by any test in Tg’

&

&

0

1

1 0

1a

b

c

Example:

Fault a 1

Fault c 0


Multiple Fault TestingCircular fault masking

Example: • The test T = {1111, 0111, 1110, 1001,

1010, 0101} detects every SSF• The only test in T that detects the

single faults b 1 and c 1 is 1001

• However, the multiple fault {b1, c1} is not detected because under the test vector 1001, b 1 masks c 1, and

c 1 masks b 1

&

&

1/0

1

1

0/1

1/0

1

1

0

0/1

0/1

0/1

ab

cd

Multiple fault F may be not detected by a complete test T for single faults because of circular masking among the faults in F


Multiple Fault Testing

To test a path under condition of multiple faults, two pattern test is needed

As the result, either the faults on the path under test are detected or the masking fault is detected

Example:The lower path from b to output is

under testA pair of patterns is applied on b There is a masking fault c 11st pattern: fault on b is masked2nd pattern: fault on c is detected

&

&

10

11

11 11(00)

10(11)

11

01(00)

01

0100

ab

cd

Testing multiple faults by pairs of patterns

The possible results:01 - No faults detected00 - Either b 0 or c 1 detected11 - The fault b 1 is detected

1 faults

(11)


Test generation

Testing multiple faults by groups of patterns

32143121 xxxxxxxxy Multiple fault: x11, x20,

x31

Test x1 x2 x1 x3 x4 x1 x2 x3 y y’T1 0 1 0 0 1 1 1 0 0 0T2 1 1 1 0 1 0 1 0 1 1T3 1 0 1 0 1 0 0 0 0 1

x31x20

x11

T1 T2 T3

Fault masking Fault detectingAn example where the method of test pairs does not help


Test generationMethod of pattern groups on DDs

x1y x2

x1 x3 x4

x1x2 x3

&

&

&

1

&

x1x2

x3x4

y

Disjunctive normal forms are trending to explodeDDs provide an alternative

Test group for testing a part of circuit:x1 x2 x3 x4 y

1 1 0 - 1

0 1 0 - 0

1 0 0 - 0

-


Test generationTest generation for sequential circuits

Time frame model:

CC

CC CC CC

R

R R R

x

xxx yyy

yFault sensitization: Test pattern consists of an input pattern and a state

Fault propagation: To propagate a fault to the output, an input pattern and a state is needed Line justification: To reach the needed state, an input sequence is needed


Hierarchical Test Generation

• In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes

• These modes will usually contain:– a list of control signals such that the data on input lines is reproduced

without logic transformation at the output lines - I-path, or – a list of control signals that provide one-to-one mapping between data inputs

and data outputs - F-path • The I-paths and F-paths constitute connections for propagating test

vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points)

• In the hierarchical approach, top-down and bottom-up strategies can be distinguished


Hierarchical Test Generation Approaches

A

B

C

D

a

D

c

A = ax D: B = bx C = cx

A

B

C

D’

a’x

d’x

c’x

A = a’xD’ = d’xC = c’x

a,c,D fixedx - free

a’

c’

a

Bottom-up approach: Top-down approach:

a’,c’,D’ fixedx - free

System System

Module Modulec



Bottom-up approach: • Pre-calculated tests for components

generated on low-level will be assembled at a higher level

• It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing

• However, the bottom-up algorithms ignore the incompleteness problem

• The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test

• The approach would work well only if the the corresponding testability demands were fulfilled

A

B

C

D

a

D

c

A = ax D: B = bx C = cx

a,c,D fixedx - free

a System

Modulec



• Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions.

• This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules

• However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied

Top-down approach: A

B

C

D’

a’x

d’x

c’x

A = a’xD’ = d’xC = c’x

a’

c’

a’,c’,D’ fixedx - free

System

Module


Test Generation

R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4

y4

y3 y1 R1 + R2

IN + R2

R1 * R2

IN* R2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

Multiple paths activation in a single DDControl function y3 is tested

Data path

Decision Diagram

High-level test generation with DDs: Conformity test

Control: For D = 0,1,2,3: y1 y2 y3 y4 = 00D2 Data: Solution of R1+ R1 IN R1 R1* R1

Test program:


Test Generation

R2M3

e+M1

a

*M2

b

R1

IN

c

d

y1 y2 y3 y4

y4

y3 y1 R1 + R2

IN + R2

R1 * R2

IN* R2

y2

R2 0

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

Single path activation in a single DDData function R1* R2 is tested

Data path

Decision Diagram

High-level test generation with DDs: Scanning test

Control: y1 y2 y3 y4 = 0032 Data: For all specified pairs of (R1, R2)

Test program:


Test Generation

y3 0

C R’2

C

y2

2222

A

2R’2

y1

R’1

R’3 B

F(B,R’3)

A

A

AR’1

0

0

0

R’2

Y,R3 R20 0

1 1

0

0

0

22

0

3

R1

C

R’1

R’1

1

0

0

1

02

010 1

1

C+R’2

R’3 R’2

R’1

Transparency functions on Decision Diagrams:

Y = C y3 = 2, R2’ = 0C - to be testedR1 = B y1 = 2, R3’ = 0R1 - to be justified

+ R3

R2

F R1

A

BC

Y

y2

Ay3

y1 s

High-level path activation on DDs


Test Generation

DD synthesis for control path

State Condition Nstate Control signals q’ q y1 y2 y3 0 1 0 0 1 1 R2 = 0 2 1 2 0 1 R2

0 3 0 2 1 2 4 2 0 0 3 4 2 1 1 4 0 1 1 2

FSM state transitions and output functions

DD for the FSM:q’ 1001q y1 y2 y3

4200

1

2

0

R’2=01

0#21203021

4211

0112

3

4


Test Generation

y3 0

C R’2

C

y2

2222

A

2R’2

y1

R’1

R’3 B

F(B,R’3)

A

A

AR’1

0

0

0

R’2

Y,R3 R20 0

1 1

0

0

0

22

0

3

R1

C

R’1

R’1

1

0

0

1

02

010 1

1

C+R’2

R’3 R’2

R’1

+ R3

R2

F R1

A

BC

Y

y2

Ay3

y1 s

High-level DDs Data path

Control pathq’ 1001q y1 y2 y3

4200

1

2

0

R’2=01

0#21203021

4211

0112

3

4


Test Generation for Digital Systems

Test generation steps:

• Fault manifestation• Fault-effect propagation• Constraints justification

y3 =2

R’ 2 =0

y2 = 0

0 R 3 = D

A R’ 1

A = D 1

R’ 1 = D 2 B = D 2

R’3

=0

y1 =2

y3 = 0

0

C = D

q’=4

Fault manifestation

q’=2 q’=1 q’=0

R’ 2 = 0 y2 = 0

q’=1q’=2

Constraints justification

Faultpropagation

t t-1 t-2 t-3Time:

0

+ R3

R2

F R1

A

BC

Y

y2

Ay3

y1 s

High-level test generation for data-path (example):


Test Generation for Digital SystemsTest generation step:

Fault-effect propagation

y3 = 2

R’2 = 0

y2 = 0

0 R 3 =D

A R’ 1

A =D 1

R’ 1 =D 2 B =D 2

R’3

= 0

y1 = 2

y3 = 0

0

C =D

q’=4

Fault manifestation

q’=2 q’=1 q’=0

R’ 2 = 0 y2 = 0

q’=1

q’=2


Faultpropagation

t t-1 t-2 t-3Time:

0

+ R3

R2

F R1

A

BC

Y

y2

Ay3

y1 s

y3 0

C R’2

CR’2

Y,R3

1

0

0

2

0

C+R’2

R’3

q’ 1001

q y1 y2 y3

4200

1

2

0

R’2=01

0#21203021

42110112

3

4



y3 0

C R’2

CR’2

Y,R30

1

0

0

2

0

y1

R’1

R’3 B

F(B,R’3)

0R1

1

02

0

C+R’2

R’3y2

2A

2R’2

0R20

1

2

3

R’2

Path activation procedures on DDs:

y3 =2

R’ 2 =0

y2 = 0

0 R 3 =D

A R’ 1

A =D 1

R’ 1 =D 2 B =D 2

R’3

=0

y1 =2

y3 = 0

0

C =D

q’=4

Fault manifestation

q’=2 q’=1 q’=0

R’ 2 = 0 y2 = 0

q’=1

q’=2


Faultpropagation

t t-1 t-2 t-3Time:

0 q’ 1001q y1 y2 y3

4200

1

2

0

R’2=01

0#21203021

4211

0112

3

4

Test generation step: Line justification Time: t-1



t q’ y1 y2 y3 A B C R1 R2 R3 Y1 0 0 0 1 02 1 1 2 0 03 2 2 0 0 D2 D2 04 4 1 1 2 D1 D D D

Symbolic test sequence:

y3 =2

R’ 2 =0

y2 = 0

0 R 3 =D

A R’ 1

A =D 1

R’ 1 =D 2 B =D 2

R’3

=0

y1 =2

y3 = 0

0

C =D

q’=4

Fault manifestation

q’=2 q’=1 q’=0

R’ 2 = 0 y2 = 0

q’=1

q’=2


Faultpropagation

t t-1 t-2 t-3Time:

0

High-level test generation example:


Test Generation

I1: MVI A,D A INI2: MOV R,A R AI3: MOV M,R OUT RI4: MOV M,A OUT IAI5: MOV R,M R INI6: MOV A,M A INI7: ADD R A A + RI8: ORA R A A RI9: ANA R A A RI10: CMA A,D A A

Test program generation for a microprocessor (example):

Instruction set:

I R3

A

OUT4

I A2R

IN5

R1,3,4,6-10

I IN1,6

A

IN2,3,4,5

A + R7

A R8

A R9

A10

DD-model of themicroprocessor:


Test GenerationTest program generation for a microprocessor (example):

I R3

A

OUT4

I A2R

IN5

R1,3,4,6-10

I IN1,6

A

IN2,3,4,5

A + R7

A R8

A R9

A10


Scanning test for adder:Instruction sequence I5 I1 I7 I4

for all needed pairs of (A,R)

OUT I4

A I7

AR

I1

IN(2)

IN(1) R I5

Time: t t - 1 t - 2 t - 3Observation Test Load


Test GenerationTest program generation for a microprocessor (example):

I R3

A

OUT4

I A2R

IN5

R1,3,4,6-10

I IN1,6

A

IN2,3,4,5

A + R7

A R8

A R9

A10


Conformity test for decoder:Instruction sequence I5 I1 D I4

for all DI1 - I10 at given A,R,IN

Data generation:IN 0A 101DataR 110

I1, I6 IN 0I2, I3 I4, I5 A 101

I7 A + R 1011I8 A R 111I9 A R 0

Functions

I10 A 0Data IN,A,R are generated so that the values of all functions were different


Test Generation

Low-levelfault

constraints

Defect

Component

Low-level test generation and constraints satisfaction

Module

System

Functionalfault

activated

High-levelsymbolic

faultpropagation

High-levelconstraintsjustification

High-level symbolic fault manifestation

Hierarchical approach with functional fault model:

technical university tallinn, estonia test generation gate-level methods functional testing:...

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