techshanghai2016 - 从全局角度实现ic、封装和pcb的协同优化

John ParkMethodology Architect

January 2016

www.mentor.com© Mentor Graphics Corp.

Outline

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Brief overview of IC-Package-PCB co-design

A modern approach to IC-Package-PCB cross-domain planning, optimization and implementation platform


Historical “Over the Wall” Approachesto Electronic Product Design No Longer Work

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SpreadsheetChip Package BoardSpreadsheet

Increased downstream bottlenecks for package and board design— Primarily due to routing limitations/challenges

of high pin count flip-chips and BGAs Non-optimal package drives up cost and lowers

performance— Future package re-spin to reduce cost and

increase profit margin More complex, multi-die 2.5D/3D solutions


Cross-Domain Informal and Simple, File Exchange Based Flows Have Become Popular

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Microsoft tools used as EDA tools— No layout/design intelligence— Limited reuse of data in production flow

EDA vendor dependencies— Doesn’t work with/across multiple EDA

vendor solutions— Single database, disparate views— Limited support for cross-domain logical (Connectivity) validation


Next Generation Path Finding & Multi-Device Co-Design/Optimization Platform

Multiple die, interposers, packages and PCBs Adjacent-domain exploration (path finding) Single view for visualization & optimization Advanced connectivity management w/ pin mapping

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Chip Package Board


Single view of IC, Package and PCB Cross-domain Planning, Assembly & Optimization

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Board outline

Breakout routing

Board-level device(s)

IC floorplan

Package

Cross-domain connectivity


Cross-Domain Integration PlatformSingle Tool for Planning, Assembly & Optimization

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Single Design Tool to Manage and Optimize Cross-Domain Systems…Aggregates Ex isting Design Flows

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IC Design Package Design Board Design


Cross-Domain Solution Must Leverage New Model Formats

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Simple die abstract models can be used for static die(s).— Die extents, Pad locations and

Signal names

True co-design requires a more robust model of the IC.— Hide technology data (device

layers/FEoL) allowing support for multi-technology integration.

— Provide enough detail about the IC to enable intelligent IC-to-IC and Interposer-to-Package planning.

Historical Die Abstracts for Wire Bonding and Flip Chip

Virtual Die Model


Concurrent IC and Package optimization

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Editable LEF/DEF based Virtual Die Model— IO and Block placement/move

– IO site definition and snap— LEF level block editing (hard vs. soft)

– Move/restore bumps – Macro substitution

— Orientation/perspective handling— On-die connectivity (RDL & Interposer

routing) management— Full ECO (accept/reject) support

– Co-design to implementation


Multi-View Connectivity Management

Design domain connectivity models— Native, table based and graphical schematic editing modes— Multi-source netlists (flexible cut & paste) — Drag & drop on-the-fly connectivity definition

Cross-domain signal shorting & splitting with automated mapping System-level connectivity tracking and verification (golden netlist)

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Cross-design connectivity management

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Project can contain multiple designs— Complete layout hierarchy— Optimization across multiple

designs — Interface devices automate pin

mapping across designs— Net tracking across designs


WYSIWYG Ball-Map Planning & Part Building

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Support for modern package configurations — Multi-source, dynamic part definition

– Spreadsheet, AIF, corporate library and “on-the-fly” — Dynamic random arrays with variable pin pitches— Domain specific footprints


Rule Based I/O Assignment & Optimization

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Drag & drop method for ball-map planning

Smart-pins to drive assignment and optimization— User definable rules for signals, pins and I/O


Cross-domain Interconnect Optimization

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Visualize and optimize interconnect across system— IC(s), interposer(s), package(s) and PCB(s)…

Smart unraveling of interconnect paths— Layer reduction, improved signal quality


Streamlined & Automated Library Development

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Automatic generation of library data — Fully customizable, based on company standards— Flat and or hierarchical symbols— Semi-automatic symbol fracturing— Eliminates human error from part building


Example: Manage and Optimize IC(s) to Interposer to Package connectivity

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Board Centric Design Examples;Optimization based on PCB level requirements

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Summary

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To address todays design complexities, a holistic platform for planning, assembling and optimizing ICs, Packages and PCBs is required— Formalizes co-design process— Support for multiple die, packages and boards— Single, hierarchical view of ICs, Packages and PCBs— Virtual Die Model to support co-design dies— Multi-view connectivity management— Rule based pin (ball-map) optimization

Plug-and-play into existing implementation flows— EDA neutral flow


Potential Benefits of holistic, cross-domain planning & optimization

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Significant cost savings— Fewer layers on package and board— Eliminate cost based, package re-spins

Improved performance & quality of end-product(s)— Shorter interconnect with fewer vias— Reduced power & heat (better battery life)

Shorter time-to-market— Mechanical restrictions worked into the design up-front — Reduce downstream package & board design bottlenecks

Quick turn, accurate marketing feedback (path finding)— Fewer project failures— Find the “right” solution early— Reduces design redundancy


Flexible, Multi-Mode Physical Design

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Single layout tool that supports PCB, MCM, SiP, RF, hybrid & BGA designs. Easy to extend through MS COM model. Industry leading Routing technology.


Flexible Physical Design Solution

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Advanced Packaging— Single die and multi-die solution

– Wire-bond, flip-chip die attach support

– Automatic wire bonding– 3D spacing checks

– Die stacking, cavities and embedded (actives and passives)

– Supports ceramic and organic substrates

— Parameterized RF structures with direct link to 3rd party RF simulators


Cross-domain Electrical Modeling

Interposers, packages and PCBs have very different geometries that may require unique EM modeling engines.— Silicon level polygon style routing and geometries— Three dimensional (3D) geometries typical in packaging— Long transmission line structures on PCBs


Package Modeling & Analysis

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Accelerated 3D package modeling

Supports all package design styles Generates SPICE, IBIS, RLCG matrices & HTML report Directly integrated with layout Full 3D geometry view


Thermal Analysis

CFD based thermal modeling/analysis— Static and transient thermal models

for dies, package assemblies & boards

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techshanghai2016 - 从全局角度实现ic、封装和pcb的协同优化

Engineering