text: charles h. roth, jr. fundamentals of logic design of logic design 5th edition 2004 thomson...
TRANSCRIPT
Review units 1-9 1
數位邏輯數位邏輯((一一))
TextText Charles H Roth Jr Charles H Roth JrFundamentals of Logic DesignFundamentals of Logic Design
5th Edition5th Edition
2004 2004
THOMSON BROOKSCOLETHOMSON BROOKSCOLE
Review units 1-9 2
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Digital systemDigital systemThe physical quantities or signals can The physical quantities or signals can assume only assume only discretediscrete valuesvaluesGreater accuracyGreater accuracy
Analog systemAnalog systemThe physical quantities or signals may vary The physical quantities or signals may vary continuouslycontinuously over a specified rangeover a specified range
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Review units 1-9 4
Digital Systems and Switching CircuitsDigital Systems and Switching CircuitsDesign of digital systemsDesign of digital systems
System designSystem designBreaking the overall system into subsystemsBreaking the overall system into subsystemsSpecifying the characteristics of each subsystemSpecifying the characteristics of each subsystemEg digital computer Eg digital computer memory units arithmetic unit IO memory units arithmetic unit IO devices control unitdevices control unit
Logic designLogic designDetermining how to interconnect basic logic building blocks to Determining how to interconnect basic logic building blocks to perform a specific functionperform a specific functionEg arithmetic unit binary addition Eg arithmetic unit binary addition logic gates Fliplogic gates Flip--Flops Flops interconnectionsinterconnections
Circuit designCircuit designSpecifying the interconnection of specific components such as Specifying the interconnection of specific components such as resistors diodes and transistors to form a gate flipresistors diodes and transistors to form a gate flip--flop or other flop or other logic building blocklogic building blockEg FlipEg Flip--Flop Flop resistors diodes transistorsresistors diodes transistors
Review units 1-9 5
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Many of subsystems of a digital system take the Many of subsystems of a digital system take the form of a switching networkform of a switching network
Switching NetworksSwitching NetworksCombinational NetworksCombinational Networks
bullbull No memoryNo memorySequential NetworksSequential Networks
bullbull Combinational Circuits + MemoryCombinational Circuits + Memory
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Basic OperationsBasic OperationsThe basic operations of Boolean algebra are The basic operations of Boolean algebra are AND OR and NOT (complement or AND OR and NOT (complement or inverse)inverse)
NOT (Complement)NOT (Complement)
InverterInverter
10 =prime 01 =prime1 0 and 0 1 ==prime==prime XifXXifX
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Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
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ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
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ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
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Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
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Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
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Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
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Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
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MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
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MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
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MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
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MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
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Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
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Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
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Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
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Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
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Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
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Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
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Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 2
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Digital systemDigital systemThe physical quantities or signals can The physical quantities or signals can assume only assume only discretediscrete valuesvaluesGreater accuracyGreater accuracy
Analog systemAnalog systemThe physical quantities or signals may vary The physical quantities or signals may vary continuouslycontinuously over a specified rangeover a specified range
Review units 1-9 3
Review units 1-9 4
Digital Systems and Switching CircuitsDigital Systems and Switching CircuitsDesign of digital systemsDesign of digital systems
System designSystem designBreaking the overall system into subsystemsBreaking the overall system into subsystemsSpecifying the characteristics of each subsystemSpecifying the characteristics of each subsystemEg digital computer Eg digital computer memory units arithmetic unit IO memory units arithmetic unit IO devices control unitdevices control unit
Logic designLogic designDetermining how to interconnect basic logic building blocks to Determining how to interconnect basic logic building blocks to perform a specific functionperform a specific functionEg arithmetic unit binary addition Eg arithmetic unit binary addition logic gates Fliplogic gates Flip--Flops Flops interconnectionsinterconnections
Circuit designCircuit designSpecifying the interconnection of specific components such as Specifying the interconnection of specific components such as resistors diodes and transistors to form a gate flipresistors diodes and transistors to form a gate flip--flop or other flop or other logic building blocklogic building blockEg FlipEg Flip--Flop Flop resistors diodes transistorsresistors diodes transistors
Review units 1-9 5
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Many of subsystems of a digital system take the Many of subsystems of a digital system take the form of a switching networkform of a switching network
Switching NetworksSwitching NetworksCombinational NetworksCombinational Networks
bullbull No memoryNo memorySequential NetworksSequential Networks
bullbull Combinational Circuits + MemoryCombinational Circuits + Memory
Review units 1-9 6
Basic OperationsBasic OperationsThe basic operations of Boolean algebra are The basic operations of Boolean algebra are AND OR and NOT (complement or AND OR and NOT (complement or inverse)inverse)
NOT (Complement)NOT (Complement)
InverterInverter
10 =prime 01 =prime1 0 and 0 1 ==prime==prime XifXXifX
Review units 1-9 7
Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 3
Review units 1-9 4
Digital Systems and Switching CircuitsDigital Systems and Switching CircuitsDesign of digital systemsDesign of digital systems
System designSystem designBreaking the overall system into subsystemsBreaking the overall system into subsystemsSpecifying the characteristics of each subsystemSpecifying the characteristics of each subsystemEg digital computer Eg digital computer memory units arithmetic unit IO memory units arithmetic unit IO devices control unitdevices control unit
Logic designLogic designDetermining how to interconnect basic logic building blocks to Determining how to interconnect basic logic building blocks to perform a specific functionperform a specific functionEg arithmetic unit binary addition Eg arithmetic unit binary addition logic gates Fliplogic gates Flip--Flops Flops interconnectionsinterconnections
Circuit designCircuit designSpecifying the interconnection of specific components such as Specifying the interconnection of specific components such as resistors diodes and transistors to form a gate flipresistors diodes and transistors to form a gate flip--flop or other flop or other logic building blocklogic building blockEg FlipEg Flip--Flop Flop resistors diodes transistorsresistors diodes transistors
Review units 1-9 5
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Many of subsystems of a digital system take the Many of subsystems of a digital system take the form of a switching networkform of a switching network
Switching NetworksSwitching NetworksCombinational NetworksCombinational Networks
bullbull No memoryNo memorySequential NetworksSequential Networks
bullbull Combinational Circuits + MemoryCombinational Circuits + Memory
Review units 1-9 6
Basic OperationsBasic OperationsThe basic operations of Boolean algebra are The basic operations of Boolean algebra are AND OR and NOT (complement or AND OR and NOT (complement or inverse)inverse)
NOT (Complement)NOT (Complement)
InverterInverter
10 =prime 01 =prime1 0 and 0 1 ==prime==prime XifXXifX
Review units 1-9 7
Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 4
Digital Systems and Switching CircuitsDigital Systems and Switching CircuitsDesign of digital systemsDesign of digital systems
System designSystem designBreaking the overall system into subsystemsBreaking the overall system into subsystemsSpecifying the characteristics of each subsystemSpecifying the characteristics of each subsystemEg digital computer Eg digital computer memory units arithmetic unit IO memory units arithmetic unit IO devices control unitdevices control unit
Logic designLogic designDetermining how to interconnect basic logic building blocks to Determining how to interconnect basic logic building blocks to perform a specific functionperform a specific functionEg arithmetic unit binary addition Eg arithmetic unit binary addition logic gates Fliplogic gates Flip--Flops Flops interconnectionsinterconnections
Circuit designCircuit designSpecifying the interconnection of specific components such as Specifying the interconnection of specific components such as resistors diodes and transistors to form a gate flipresistors diodes and transistors to form a gate flip--flop or other flop or other logic building blocklogic building blockEg FlipEg Flip--Flop Flop resistors diodes transistorsresistors diodes transistors
Review units 1-9 5
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Many of subsystems of a digital system take the Many of subsystems of a digital system take the form of a switching networkform of a switching network
Switching NetworksSwitching NetworksCombinational NetworksCombinational Networks
bullbull No memoryNo memorySequential NetworksSequential Networks
bullbull Combinational Circuits + MemoryCombinational Circuits + Memory
Review units 1-9 6
Basic OperationsBasic OperationsThe basic operations of Boolean algebra are The basic operations of Boolean algebra are AND OR and NOT (complement or AND OR and NOT (complement or inverse)inverse)
NOT (Complement)NOT (Complement)
InverterInverter
10 =prime 01 =prime1 0 and 0 1 ==prime==prime XifXXifX
Review units 1-9 7
Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 5
Digital Systems and Switching CircuitsDigital Systems and Switching Circuits
Many of subsystems of a digital system take the Many of subsystems of a digital system take the form of a switching networkform of a switching network
Switching NetworksSwitching NetworksCombinational NetworksCombinational Networks
bullbull No memoryNo memorySequential NetworksSequential Networks
bullbull Combinational Circuits + MemoryCombinational Circuits + Memory
Review units 1-9 6
Basic OperationsBasic OperationsThe basic operations of Boolean algebra are The basic operations of Boolean algebra are AND OR and NOT (complement or AND OR and NOT (complement or inverse)inverse)
NOT (Complement)NOT (Complement)
InverterInverter
10 =prime 01 =prime1 0 and 0 1 ==prime==prime XifXXifX
Review units 1-9 7
Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 6
Basic OperationsBasic OperationsThe basic operations of Boolean algebra are The basic operations of Boolean algebra are AND OR and NOT (complement or AND OR and NOT (complement or inverse)inverse)
NOT (Complement)NOT (Complement)
InverterInverter
10 =prime 01 =prime1 0 and 0 1 ==prime==prime XifXXifX
Review units 1-9 7
Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 7
Basic OperationsBasic OperationsAND OperationAND Operation
Omit the symbol Omit the symbol ldquoldquordquordquo A A B=ABB=AB
AND GateAND Gate
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 8
Basic OperationsBasic OperationsOR operationOR operation
OR GateOR Gate
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 9
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
ExclusiveExclusive--OROR
Truth table and gate forTruth table and gate for
if and only if if and only if XX=1 or =1 or YY=1 and =1 and XX and and YYare not both 1are not both 1
011101110000
=oplus=oplus=oplus=oplus
YX oplus
1=oplusYX
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 10
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
The equivalence operation is defined byThe equivalence operation is defined by
The truth table for is The truth table for is
if and only if if and only if
)(equiv
YX equiv
1)( =equivYX YX =
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 11
ExclusiveExclusive--OR and Equivalence OR and Equivalence OperationsOperations
Equivalence Equivalence is the is the complementcomplement of of exclusiveexclusive--OROR
Alternate symbol for the equivalence gateAlternate symbol for the equivalence gate
The equivalence gate is also called an The equivalence gate is also called an exclusiveexclusive--NOR NOR gategate
YXXYYX primeprime+=equiv )(
))(()()( YXYXYXYXYX +primeprime+=primeprime+prime=primeoplus)( YXYXXY equiv=primeprime+=
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 12
NAND and NOR GatesNAND and NOR GatesNAND gateNAND gate An An ANDAND gate followed by an gate followed by an NOTNOT gategate
nn--input NAND gatesinput NAND gatesnn=2=2nn=3=3 CBAABCF prime+prime+prime=prime= )(
nn XXXXXXF prime++prime+prime=prime= )( 2121
BAABF prime+prime=prime= )(
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 13
NAND and NOR GatesNAND and NOR GatesNOR gateNOR gate An An OROR gate followed by an gate followed by an NOTNOT gategate
nn--input NOR gatesinput NOR gatesnn=2=2nn=3=3 CBACBAF primeprimeprime=prime++= )(
nn XXXXXXF primeprimeprime=prime++= )( 2121
BABAF primeprime=prime+= )(
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 14
Boolean Expressions and Truth TablesBoolean Expressions and Truth Tables
Order in which the operations are performOrder in which the operations are performParenthesesParentheses ComplentationComplentation ANDAND ORORCircuits for expressionsCircuits for expressions
CBA +prime
BEDCA +prime+ ])([
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 15
Truth TableTruth TableIf an expression has If an expression has nn variables the number of different variables the number of different combinations of values of the variables is combinations of values of the variables is 22nn Therefore a truth Therefore a truth table for ntable for n--variable expression will have variable expression will have 22nn rowsrowsThere are functions of There are functions of nn variablesvariables )2(2
n
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 16
SumSum--ofof--products (SOP)products (SOP)An expression is said to be in An expression is said to be in sumsum--ofof--productsproducts form when all form when all products are the products are the products of only single variablesproducts of only single variables
ProductProduct--ofof--sums (POS)sums (POS)An expression is said to be in An expression is said to be in productproduct--ofof--sumssums form when all form when all sums are the sums are the sums of only single variablessums of only single variables
form SOPin (form SOPin
notisEFB)CDAareEDCBAECAEDCBA
++
prime++prime+prime+prime+prime
form POSin form POSin )( ))()((
EF is not D)B)(C(AareEDCBAECAEDCBA
++++primeprimeprime+prime++prime+prime+
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 17
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
ExampleExample Design a switching circuit with three Design a switching circuit with three inputs inputs A BA B and and CC and one output and one output f f TheThe input input ABAB and and CC represent the represent the firstfirst secondsecond and and third third bits respectively for a binary numberbits respectively for a binary number N f=1 N f=1 if if
andand f=0 f=0 if if SolSol--11
2011geN 2011ltN
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 18
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--1 (cont) 1 (cont) Derive an algebraic expression for Derive an algebraic expression for ff from the truth table by using the combinations from the truth table by using the combinations of values of of values of ABAB and and CC for which for which ff=1=1
The circuit is The circuit is
ABCCABCBACBABCAf +prime+prime+primeprime+prime=BCAABCAABBABCA +=+prime=+prime+prime=
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 19
Combinational Logic Design Using a Combinational Logic Design Using a Truth TableTruth Table
SolSol--2 2 First write First write ffrsquorsquo as a sum of products and then as a sum of products and then complement the result complement the result ffrsquorsquo is 1 for input combinations is 1 for input combinations ABCABC=000 001 010 so=000 001 010 so
CBACBACBAf primeprime+primeprime+primeprimeprime=prime
BCACBABA
CBACBACBACBACBACBAff
+=+prime++=
+prime+prime++++=
primeprimeprime+primeprime+primeprimeprime=primeprime=
gate] AND one and gates OR [Two ))((
gate) ANDinput -3 one and gates ORinput -3 Three ( ))()((
)()(
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 20
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMintermA A mintermminterm of of nn variables is a variables is a productproduct of of n n literals literals in which in which each variable appears exactly onceeach variable appears exactly once in in either either truetrue or or complementcomplement form form but not bothbut not bothMaxtermMaxtermA A maxtermmaxterm of of nn variables is a variables is a sumsum of of n n literals in literals in which which each variable appears exactly onceeach variable appears exactly once in either in either truetrue or or complementcomplement form form but not bothbut not both
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 21
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MintermMinterm and and MaxtermMaxterm for for threethree variablesvariables
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 22
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsMintermMinterm expansion orexpansion orStandard sum of products Standard sum of products When a function is written as a When a function is written as a sum of sum of mintermsminterms this is this is referred to as a referred to as a mminterminterm expansionexpansion or or standard sum of standard sum of productsproducts
ExamplesExamplesABCCABCBACBABCACBAf +prime+prime+primeprime+prime=)(
76543)( mmmmmCBAf ++++=
sum= )76543()( mCBAf
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 23
MintermMinterm and and MaxtermMaxterm ExpansionsExpansions
MaxtermMaxterm expansion orexpansion orStandard product of sumsStandard product of sumsWhen a function is written as a When a function is written as a product of product of maxtermsmaxterms this this
is referred to as a is referred to as a maxtermmaxterm expansionexpansion or or standard standard product of sumsproduct of sums
Example Example ))()(()( CBACBACBACBAf +prime+prime++++=
210)( MMMCBAf =
prod= )210()( MCBAf
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 24
MintermMinterm and and MaxtermMaxterm ExpansionsExpansionsComplement of a function Complement of a function f f ExampleExample
76543)( mmmmmCBAf ++++=)( 76543 prime++++=prime mmmmmf
7654376543 MMMMMmmmmm =primeprimeprimeprimeprime=
210210210 )( mmmMMMMMMf ++=prime+prime+prime=prime=prime210)( MMMCBAf =
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 25
Incompletely Specified FunctionsIncompletely Specified FunctionsIncompletely Specified FunctionIncompletely Specified FunctionA function contains donA function contains donrsquorsquot care termst care termsExample 1 Example 1 The output of The output of subcircuitsubcircuit NN11 drives the drives the input of the input of the subcircuitsubcircuit NN22 Assume that there are no Assume that there are no combinations of values for combinations of values for wxywxy and and zz which cause which cause ABAB and and CC to assume values of 001 or 110to assume values of 001 or 110
The function F is The function F is incompletely specifiedincompletely specified
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 26
Incompletely Specified FunctionsIncompletely Specified FunctionsExample 1(cont)Example 1(cont)
1 Assign 0 to both X1 Assign 0 to both Xrsquorsquoss
2 Assign 1 to the first X and 0 to the second 2 Assign 1 to the first X and 0 to the second ------ simplest solutionsimplest solution
3 Assign 0 to the first X and 1 to the second3 Assign 0 to the first X and 1 to the second
4 Assign 1 to both X4 Assign 1 to both Xrsquorsquoss
sum sum+= )61()730( dmFprod prodsdot= )61()542( DMF
BCCBAABCBCACBAF +primeprimeprime=+prime+primeprimeprime=
BCBAABCBCACBACBAF +primeprime=+prime+primeprime+primeprimeprime=
ABBCBAABCCABBCACBACBAF ++primeprime=+prime+prime+primeprime+primeprimeprime=
ABBCACBAABCCABBCACBAF +prime+primeprimeprime=+prime+prime+primeprimeprime=
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 27
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2Example 2 Design an Design an adderadder which adds two which adds two 22--bit binary numbers to give a 3bit binary numbers to give a 3--bit binary sum bit binary sum The circuit has 4 inputs and 3 outputs The circuit has 4 inputs and 3 outputs
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 28
Examples of Truth Table Examples of Truth Table ConstructionConstruction
Example 2(cont)Example 2(cont)The output functions are The output functions are
sum
sum
sum
===
)14121196431()()1512986532()()15141311107()(
mDCbAZmDCBAYmDCBAX
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 29
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Half AdderHalf Adder
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 30
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
Full AdderFull Adder
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 31
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic equation for the The logic equation for the full adderfull adder
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 32
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
The logic circuit of full adderThe logic circuit of full adder
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 33
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel AdderAdds two 4Adds two 4--bit unsigned binary numbersbit unsigned binary numbers
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 34
Design of Binary Adders and Design of Binary Adders and SubtractersSubtracters
44--Bit Parallel AdderBit Parallel Adder
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Unit 5 Unit 5 KarnaughKarnaugh MapsMaps
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 36
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMaps
ExampleExample
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 37
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
22-- variable variable KarnaughKarnaugh MapsMapsExampleExample
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 38
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
33--variable variable KarnaughKarnaugh MapsMaps
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 39
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Adjacent CellsAdjacent CellsTwo cell which Two cell which differ in just one variablediffer in just one variable are said to are said to be be adjacentadjacent 22k k adjacent calls can be combinedadjacent calls can be combined
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 40
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If F is given as a If F is given as a mintermminterm ((maxtermmaxterm) expansion the ) expansion the map by placing map by placing 11rsquorsquoss((00rsquorsquoss) in the squares which ) in the squares which correspond to the correspond to the mintermminterm ( ( maxtermmaxterm) and then by ) and then by filling in the remaining squares with filling in the remaining squares with 00rsquorsquoss((11rsquorsquoss))
ExampleExample 76420531)( MMMMMmmmcbaF =++=
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 41
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
If a function is given in If a function is given in algebraic formalgebraic form plot itplot itrsquorsquos s KarnaughKarnaugh MapMapExampleExample acbcabcbaf prime+prime+prime=)(
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 42
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample sum= )531(mF
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 43
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Simplify a function using Simplify a function using KarnaughKarnaugh MapMapExampleExample Simplify the Simplify the complement complement ofof
sum= )531(mF
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 44
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
IllIllustrateustrate the Consensus Theoremthe Consensus TheoremExampleExample zxxyyzzxxy prime+=+prime+
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 45
TwoTwo-- and Threeand Three-- Variable Variable KarnaughKarnaugh MapsMaps
Minimum sumMinimum sum--ofof--products is products is notnot uniqueuniqueExampleExample sum= )765210(mf
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 46
FourFour-- Variable Variable KarnaughKarnaugh MapsMaps44--Variable Variable KarnaughKarnaugh MapsMaps
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 47
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExampleExample dbaacddcbaf prime+prime+=)(
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 48
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsExample SimplifyExample Simplify sum= )1312105431(1 mf
sum= )151411108765320(2 mf
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 49
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsSimplify a function with donSimplify a function with donrsquorsquot caret careExampleExample
All the 1All the 1rsquorsquos must bes must becoveredcovered but the but the XXrsquorsquossare only used if they are only used if they
will simplify the will simplify the resulting expressionresulting expression
sum sum+= )13126()97531( dmf
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 50
FourFour-- Variable Variable KarnaughKarnaugh MapsMapsFind a minimum Find a minimum productproduct--ofof--sumssums
1 Find a minimum sum1 Find a minimum sum--ofof--products for Fproducts for Frsquorsquo2 Complement F2 Complement Frsquorsquo using using DeMorganDeMorganrsquorsquoss TheoremTheorem
Example Find a minimum productExample Find a minimum product--ofof--sums forsums foryxzywwyzzxf prime+primeprimeprime++primeprime=
xywzwxzyf prime+prime+prime=prime
))()(()( yxwzxwzyff prime+prime++prime+primeprime+=primeprime=
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 51
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
Cover Cover A switching function A switching function ff(x(x11xx22helliphellipxxnn) is said to ) is said to covercover another function another function gg(x(x11xx22helliphellipxxnn) if ) if f f assumes the assumes the value 1 whenever value 1 whenever gg doesdoesImplicantImplicant Given a function F of n variables a Given a function F of n variables a product term P product term P is an is an implicantimplicant of F of F iffiff for every for every combination of values of the n variables for which combination of values of the n variables for which P=1 F is also equal 1That is P=1 F is also equal 1That is P=1P=1 impliesimplies F=1F=1Prime Prime ImplicantImplicant A A prime prime implicantimplicant of a of a function F is a function F is a product term product term implicartimplicart which which is no is no longer an longer an implicantimplicant if any literal is deleted from itif any literal is deleted from itEssential Prime Essential Prime ImplicantImplicant If If a a mintermminterm is is covered by only onecovered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential prime essential prime implicantimplicant
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 52
ImplicantImplicant 函數函數ff在卡諾圖中任何單一個在卡諾圖中任何單一個11或或任何一組任何一組11可以被合併在一起而形成一個積可以被合併在一起而形成一個積項則被稱為項則被稱為FF的含項的含項Prime Prime ImplicantImplicant若一個積項不能再和其他若一個積項不能再和其他項合併消去變數則稱為質含項項合併消去變數則稱為質含項Essential Prime Essential Prime ImplicantImplicant某些最小項某些最小項((mintermminterm全及項全及項))只被單一個質含項包只被單一個質含項包含如果一個最小項只被一個質含項包含如果一個最小項只被一個質含項包含則包含此最小項的質含項稱為基本質含則包含此最小項的質含項稱為基本質含項含項
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 53
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
On a On a KarnaughKarnaugh MapMapAny single 1 or any group of 1Any single 1 or any group of 1rsquorsquos (2s (2k k 11rsquorsquos k=012s k=012helliphellip) ) which can be combined together on a map of the which can be combined together on a map of the function F function F represents a product termrepresents a product term which is which is called an called an implicantimplicant of Fof FA product term A product term implicantimplicant is called a prime is called a prime implicantimplicantif it cannot be combined with another term to if it cannot be combined with another term to eliminate a variableeliminate a variableIf If a a mintermminterm is covered by only oneis covered by only one prime prime implicantimplicant then that prime then that prime implicantimplicant is called an is called an essential essential prime prime implicantimplicant
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 54
Determination of Minimum Expansions Determination of Minimum Expansions Using Essential Prime Using Essential Prime ImplicantsImplicants
ExamplesExamplesf=f=wx+yzwx+yz g= g=wxywxyrsquorsquog=1 (w=1x=1y=0) implies f=1g=1 (w=1x=1y=0) implies f=11+01+0z=1 f covers gz=1 f covers gg is a product term g is a product term g is an g is an implicantimplicant of fof fg is g is not not a a prime prime implicantimplicant The literal y The literal yrsquorsquo is deleted is deleted from from wxywxyrsquorsquo the resulting term the resulting term wxwx is also an is also an implicantimplicantof fof fh=h=wxwx is a prime is a prime implicantimplicant The deletion of any The deletion of any literal (w or x) results a new product (x or w) which literal (w or x) results a new product (x or w) which is not covered by f [w=1 does not imply f=1 is not covered by f [w=1 does not imply f=1 (w=1x=0y=0z=0 imply f=0)](w=1x=0y=0z=0 imply f=0)]
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 55
55--Variable Variable KarnaughKarnaugh MapsMaps55--variable variable KarnaughKarnaugh MapMap
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 56
55--Variable Variable KarnaughKarnaugh MapsMapsExample Example Simplify the functionSimplify the function
sum= )31302826242322212015135410()( mEDCBAF
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Unit 7 MultiUnit 7 Multi--Level Gate CircuitsLevel Gate CircuitsNAND and NOR GatesNAND and NOR Gates
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 58
MultiMulti--Level Gate CircuitsLevel Gate CircuitsIncreasingreducing the number of levelsIncreasingreducing the number of levels
Increasing the number of levelsIncreasing the number of levelsReduce the required number of gatesReduce the required number of gatesReduce the number of gate inputsReduce the number of gate inputsIncrease gate delaysIncrease gate delays
Reducing the number of levelsReducing the number of levelsReduce gate delays speed up the operation Reduce gate delays speed up the operation of the digital systemof the digital system
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 59
MultiMulti--Level Gate CircuitsLevel Gate CircuitsExampleExample
4 levels4 levels6 gates6 gates
13 gate inputs13 gate inputs
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 60
Functionally CompleteFunctionally CompleteA A set of logic operationsset of logic operations is said to be is said to be functionally completefunctionally complete if if anyany Boolean function Boolean function can be expressed in terms of this set of can be expressed in terms of this set of operationsoperationsANDANDORORNOTNOT is is functionally completefunctionally completeAny Any set of logic gatesset of logic gates which which can realizecan realizeANDOR and NOT is also functionally ANDOR and NOT is also functionally completecompleteNANDNAND is functionally completeis functionally completeNORNOR is functionally completeis functionally completeANDORANDOR is is notnot functionally completefunctionally complete
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 61
Functionally CompleteFunctionally CompleteANDNOTANDNOT is functionally completeis functionally complete
ORNOTORNOT is functionally completeis functionally complete
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 62
Functionally CompleteFunctionally CompleteNANDNAND is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NAND gatesNAND gates
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 63
Functionally CompleteFunctionally CompleteNORNOR is functionally completeis functionally complete
Any switching function can be realized Any switching function can be realized using using onlyonly NOR gatesNOR gates
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 64
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 65
Design of TwoDesign of Two--level Circuits Using level Circuits Using NAND and NOR GatesNAND and NOR Gates
Example (cont)Example (cont)
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 66
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
ExampleExample Design a circuit with four inputs Design a circuit with four inputs and three outputs which realizes the functionsand three outputs which realizes the functions
SolSol Each function is realized individually Each function is realized individually The cost of the resulting circuit is The cost of the resulting circuit is 9 gates9 gates and and 21 gate inputs21 gate inputs
sum
sum
sum
===
)1514131273()()1513121173()(
)1514131211()(
3
2
1
mDCBAFmDCBAFmDCBAF
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 67
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
ABCDA)m((ABCD)F
CDCAB)m((ABCD)F
ACDABmDCBAF
+prime==
+prime==
+==
sumsumsum
1514131273
1513121173
)1514131211()(
3
2
1
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 68
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 69
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont) Sol (cont) Use the Use the common termscommon terms to to save gatessave gates FF11==ABAB++ACDACDFF22==ABCABCrsquorsquo++CDCD==ABCABCrsquorsquo++AArsquorsquoCDCD++ACDACDFF33==AArsquorsquoCDCD++ABAB
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 70
Design of TwoDesign of Two--Level MultipleLevel Multiple--Output CircuitsOutput Circuits
Sol (cont)Sol (cont)4 AND gates4 AND gates3 OR gates3 OR gatesIn realizing multipleIn realizing multiple--output output
circuits the use of a circuits the use of a minimum summinimum sum--ofof--productproductimplicantsimplicants for each function for each function does not necessarily lead to does not necessarily lead to a minimum cost solutiona minimum cost solution for for the circuit as a wholethe circuit as a whole
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Unit 08 Combinational Unit 08 Combinational Circuit Design and Circuit Design and
Simulation Using GatesSimulation Using Gates
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 72
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Propagation delay Propagation delay If the change in If the change in output is delayed by time with respect to output is delayed by time with respect to the input we say that this gate has a the input we say that this gate has a propagation delay of propagation delay of Propagation delay in an inverterPropagation delay in an inverter
ε
ε
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 73
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
Timing DiagramTiming DiagramExampleExample Assume that each gate has a Assume that each gate has a propagation delay of 20 propagation delay of 20 nsns (nanoseconds)(nanoseconds)
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 74
Gate Delays and Timing DiagramsGate Delays and Timing Diagrams
ExampleExample Circuit with and Circuit with and delay elementdelay element
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 75
Hazards in Combinational LogicHazards in Combinational LogicThe The unwanted unwanted switching transientsswitching transients may may appear in the appear in the outputoutput when when different pathsdifferent paths from from input to output have input to output have different propagation different propagation delaysdelays Static 1Static 1-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 00 when it when it shouldshould remain a remain a constant 1constant 1 we say that the circuit has a we say that the circuit has a staticstatic 11--hazardhazard
Static 0Static 0-- hazard hazard If in response to any single If in response to any single input input changechange and for some and for some combination of propagation delayscombination of propagation delays a circuit a circuit output output may may momentarilymomentarily go to go to 11 when it when it shouldshould remain a remain a constantconstant 00 we say that the circuit has a we say that the circuit has a staticstatic 00--hazardhazard
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 76
Hazards in Combinational LogicHazards in Combinational LogicDynamic hazardDynamic hazard If when If when output is output is supposed to change from 0 to 1 (or 1 to 0)supposed to change from 0 to 1 (or 1 to 0) the the output output may change three or more timesmay change three or more times we we say that the circuit has a say that the circuit has a dynamic hazarddynamic hazard
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 77
Hazards in Combinational LogicHazards in Combinational LogicExampleExample Circuit with a Circuit with a staticstatic 11--hazardhazardAssume that each gate has a propagation delay of 10 nsAssume that each gate has a propagation delay of 10 ns
If A=C=1If A=C=1then F=B+Bthen F=B+Brsquorsquo=1=1F should remainF should remain
a constant 1a constant 1 whenwhenB changesB changesfrom 1 to 0from 1 to 0
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 78
Hazards in Combinational LogicHazards in Combinational LogicProcedureProcedure for detecting hazards in a for detecting hazards in a twotwo--level ANDlevel AND--OR circuitOR circuit
11Write down the SOP expression for the Write down the SOP expression for the circuitcircuit2Plot each term on the map and loop it2Plot each term on the map and loop it3If any two adjacent 13If any two adjacent 1rsquorsquos are not covered by s are not covered by the same loopthe same loop a 1a 1--hazard exists for the hazard exists for the transition between the two 1transition between the two 1rsquorsquoss For an For an nn--variable map this transition occurs when variable map this transition occurs when one variable changes and the other one variable changes and the other nn--11variables are held constant variables are held constant
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 79
Hazards in Combinational LogicHazards in Combinational LogicEliminating hazardsEliminating hazardsAdd a loop to cover Add a loop to cover two adjacent 1two adjacent 1rsquorsquoss
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 80
Hazards in Combinational LogicHazards in Combinational LogicExampleExample A circuit with several 0A circuit with several 0--hazardshazards
F=(A+C)(AF=(A+C)(Arsquorsquo+D+Drsquorsquo)(B)(Brsquorsquo+C+Crsquorsquo+D)+D)A=0 B=1 D=0 C changes from 0 to 1A=0 B=1 D=0 C changes from 0 to 1Gate delay 3 ns for NOT 5 ns for ANDOR Gate delay 3 ns for NOT 5 ns for ANDOR
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 81
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 82
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont)
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 83
Hazards in Combinational LogicHazards in Combinational LogicExample (cont)Example (cont) Eliminating the 0Eliminating the 0--hazards by hazards by
looping additional prime looping additional prime implicantsimplicants that cover the that cover the adjacent 0adjacent 0rsquorsquos that are not covered by a common loops that are not covered by a common loop
))()()()()(( CBADBADCDCBDACAF prime+prime+prime+prime+prime++prime+primeprime+prime+=
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Unit 9Unit 9
Multiplexers Decoders Multiplexers Decoders and Programmable Logic and Programmable Logic
DevicesDevices
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 85
MultiplexersMultiplexersMultiplexers (Multiplexers (MUXMUX or data selector) or data selector)
A MUX has a group of data inputs and a group of A MUX has a group of data inputs and a group of control inputscontrol inputsThe control inputs are used to select The control inputs are used to select oneone of the of the data inputs and data inputs and connect it to the outputconnect it to the output terminalterminal
22--to 1 MUXto 1 MUXA=0 Z=IA=0 Z=I00
A=1 Z=IA=1 Z=I11
Z=AZ=ArsquorsquoII00+AI+AI11
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 86
MultiplexersMultiplexers44--toto--1 81 8--toto--1 21 2nn--toto--1 MUX1 MUX
Logic equation for 8Logic equation for 8--toto--1 MUX1 MUX
7654
3210
ABCIICABCIBAICBABCIAICBACIBAICBAZ
+prime+prime+primeprime+
prime+primeprime+primeprime+primeprimeprime=
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 87
MultiplexersMultiplexersLogic Diagram for 8Logic Diagram for 8--toto--1 MUX1 MUX
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 88
MultiplexersMultiplexersLogic equation for 2Logic equation for 2nn--toto--1 MUX1 MUX
where is a where is a mintermminterm of the n control of the n control variables and is the corresponding variables and is the corresponding data input data input
summinus
==
12
0
n
k kk ImZ
km
kI
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 89
MultiplexersMultiplexersQuadQuad Multiplexer Used to Select DataMultiplexer Used to Select Data
A=0 (zA=0 (z00zz11zz22zz33)=(x)=(x00xx11xx22xx33))A=1 (zA=1 (z00zz11zz22zz33)=(y)=(y00yy11yy22yy33))
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 90
MultiplexersMultiplexersQuadQuad Multiplexer with Multiplexer with BusBus Input and OutputInput and Output
A=0 Z=XA=0 Z=XA=1 Z=YA=1 Z=Y
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 91
ThreeThree--State BuffersState BuffersA gate A gate outputoutput can only be can only be connected connected to a to a limited limited number of other device inputsnumber of other device inputs without degrading the without degrading the performance of a digital systemperformance of a digital systemAA bufferbuffer may be used to may be used to increase the driving capabilityincrease the driving capabilityof a gate outputof a gate output
CF =
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 92
ThreeThree--State BuffersState BuffersA logic circuit will A logic circuit will not not operate correctly if operate correctly if the the outputs of two or more gatesoutputs of two or more gates or other or other logic devices logic devices are directly connected to are directly connected to each othereach otherUse of Use of threethree--state logicstate logic permits the permits the outputs of two or more gates or other outputs of two or more gates or other logic devices to be connected togetherlogic devices to be connected together
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 93
ThreeThree--State BuffersState BuffersThreeThree--state buffer (Tristate buffer (Tri--state buffer)state buffer)
Enable inputEnable input B=1 B=1 outputoutput C=A C=A whenwhen B=0 C B=0 C acts like acts like anan open circuitopen circuit C C is effectivelyis effectively disconnected from the disconnected from the buffer outputbuffer output so that no current can flow This is so that no current can flow This is referred to a referred to a HiHi--Z (highZ (high--impedance) state of the outputimpedance) state of the outputbecause the circuit offers a very high resistance or because the circuit offers a very high resistance or impedance to the flow of currentimpedance to the flow of current
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 94
ThreeThree--State BuffersState BuffersData Selection Using ThreeData Selection Using Three--State State Buffers Buffers
D=BD=BrsquorsquoA+BCA+BC
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 95
ThreeThree--State BuffersState BuffersCircuit with Two ThreeCircuit with Two Three--State BuffersState Buffers
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 96
ThreeThree--State BuffersState BuffersThreeThree--state Busstate BusA bus is driven by threeA bus is driven by three--state buffersstate buffers
44--Bit Adder with Bit Adder with four sourcesfour sources for for one one operandoperand
Use a 4Use a 4--toto--1 MUX to select one of several sources1 MUX to select one of several sourcesSet up a threeSet up a three--state busstate bus
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 97
ThreeThree--State BuffersState BuffersBiBi--directional IO Pindirectional IO Pin
Buffer is Buffer is enabledenabled OutputOutputBuffer is Buffer is disableddisabled InputInput
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 98
Decoders and EncodersDecoders and EncodersDecoderDecoder
Generates all of Generates all of mintermsmintermsExactly one of the outputs lines will be 1 for each combination Exactly one of the outputs lines will be 1 for each combination of the values of the input variablesof the values of the input variables
33--toto--8 Decoder8 Decoder
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 99
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder with Inverted Output10 Line Decoder with Inverted Output
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 100
Decoders and EncodersDecoders and Encoders44--toto--10 Line Decoder10 Line Decoder
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 101
Decoders and EncodersDecoders and Encodersnn--toto--22n n line decoderline decoder
Generate allGenerate all 22nn mintermsminterms (or (or maxtermsmaxterms) of ) of the the nn input variablesinput variablesOutputsOutputs
NoninvertedNoninvertedyyii=m=mi i i=012 i=012helliphellip22nn--11InvertedInvertedyyii=m=miirsquorsquo=M=Mi i i=012 i=012helliphellip22nn--11
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 102
Decoders and EncodersDecoders and EncodersUse Use decoderdecoder and and gatesgates to realize a to realize a functionfunctionExampleExample Realize the following functions using a Realize the following functions using a decoderdecoder
SolSol
9742
4211
)()(
mmmdcbafmmmdcbaf++=++=
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 103
Decoders and EncodersDecoders and EncodersSolSol
)()(
9742
4211
primeprimeprimeprime=
primeprimeprimeprime=mmmfmmmf
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 104
Decoders and EncodersDecoders and EncodersEncoderEncoderThe inverse function of a decoderThe inverse function of a decoder
88--toto--3 Priority Encoder3 Priority Encoder
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 105
ReadRead--Only MemoriesOnly MemoriesReadRead--Only Memory (ROM)Only Memory (ROM)Consists of semiconductor devices that interconnected to store Consists of semiconductor devices that interconnected to store
binary databinary data
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 106
ReadRead--Only MemoriesOnly MemoriesA ROM can realize A ROM can realize mm functions functions ((FF11FF22helliphellipFFnn) of ) of nn variablesvariablesA ROM consists of aA ROM consists of a decoderdecoder and a and a memory arraymemory array
mn times2 m
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 107
ReadRead--Only MemoriesOnly MemoriesMultipleMultiple--output combinational circuits output combinational circuits can be realized using ROMscan be realized using ROMsExampleExample Realize the following Realize the following functions using ROMfunctions using ROM
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 108
ReadRead--Only MemoriesOnly MemoriesSolSol
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 109
ReadRead--Only MemoriesOnly MemoriesExampleExample Design a Design a code convertercode converter that converts a 4that converts a 4--bit bit binary number to a hexadecimal digit and outputs the 7binary number to a hexadecimal digit and outputs the 7--bit ASCII bit ASCII codecode
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 110
ReadRead--Only MemoriesOnly MemoriesSol Sol Because the ROM needs Because the ROM needs only only fivefive outputs The ROM size is outputs The ROM size is 1616 words words by by 55 bits bits The decoder is a 4The decoder is a 4--toto--1616 decoderdecoder
4645 AAAA prime==
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer
Review units 1-9 111
ReadRead--Only MemoriesOnly MemoriesTypes of ROMsTypes of ROMs
MaskMask--programmable ROMsprogrammable ROMsProgrammable ROMs (Programmable ROMs (PROMsPROMs))Electrically Erasable Programmable ROMs Electrically Erasable Programmable ROMs ((EEPROMsEEPROMs E E22PROMs)PROMs)Flash memoriesFlash memoriesFlash memory has builtFlash memory has built--in programming and erase in programming and erase capability so that data can be written to it while it is capability so that data can be written to it while it is in place in a circuit without the need for a separate in place in a circuit without the need for a separate programmerprogrammer