thiet ke logic so
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HC VIN K THUT QUN SB MN K THUT XUNG S, VI X L KHOA V TUYN IN T
THIT K LOGIC S(Dng cho i tng o to chnh quy h qun s v dn s)
LU HNH NI B
H NI -2011
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LI GII THIUThit k logic s l mn hc k tip ca chng trnh in t s. Ni dung chnh ca chng trnh mn hc tp trung vo hai vn kin thc chnh. Th nht l bi ton thit k v mt chc nng cho cc khi s c mt tch hp ln c LSI, VLSI v ln hn. Vn th hai l gii thiu cn bn v cc cng ngh gip hin thc ha thit k chc nng thnh sn phm ng dng, trong tp trung chnh vo cng ngh FPGA, mt nn tng cng ngh mi v ang pht trin rt mnh hin nay. Khc vi bi ton tng hp v phn tch trong in t s ch yu l bi ton cho cc mch c SSI, MSI, cc bi ton y c hng ti cc ng dng c th thc tin vi quy m ln hn v buc phi s dng cc cng c tr gip thit k trn my tnh v ngn ng thit k VHDL Chng trnh Thit k logic s nhm vo trang b kin thc c s ngnh cho tt c cc i tng sinh vin thuc chuyn ngnh k thut in t vin thng, iu khin t ng. Trc khi hc mn ny cc sinh vin ny phi hc qua cc mn c s ngnh gm Cu kin in t, in t s, K thut Vi x l trong hai mn u l bt buc. Thit k logic s l mt mn hc mang tnh thc hnh cao nn trong cu trc chng trnh s dnh nhiu thi gian hn cho thc hnh th nghim cng nh bt buc sinh vin khi kt thc mn hc phi thc hin cc n bi tp thit k c va v ln theo nhm di dng Bi tp ln hoc n mn hc. Kin thc v k nng ca sinh vin s gip ch rt ln cho cc bi ton chuyn ngnh v n tt nghip sau ny bi trong cc ng dng x l s ang dn chim vai tr quan trng trong cc h thng k thut. Bn cnh nhng cng c truyn thng l Vi x l, my tnh th thit k phn cng trn FPGA hoc trn nn cc cng ngh tng t ang l mt hng pht trin mang li hiu nng vt tri v kh nng ng dng thch nghi tt hn. Gio trnh chnh thc cho mn hc c hon thin sau hn 2 kha o to cho sinh vin h o to dn s, qun s ti Hc vin K thut qun s. Nhm tc gi xin chn thnh cm n s ng h nhit tnh ca lnh o Khoa V tuyn in t, lnh o b mn K thut xung s, vi x l, cc ng nghip trong khoa v b mn c nhiu kin ng gp qu bu gp phn hon thin ni dung cho gio trnh, cm n anh ch em nhn vin ca b mn gp nhiu cng sc cho cng vic ch bn cho gio trnh. Nhm tc gi cng gi li cm n ti 3
ton b cc sinh vin cc kha o to bng qu trnh hc tp, nghin cu thc t c nhng kin ng gp gip tc gi iu chnh v khung chng trnh v ni dung ngy hp l v hiu qu hn. V thi gian hn ch v l mt mn hc mi do vy chc chn s cn nhiu nhng khim khuyt trong gio trnh. Nhm tc gi rt mong tip tc nhn c nhng kin ng gp ca ngi s dng, mi kin c th gi v B mn K thut Xung s, Vi x l Hc vin KTQS hoc vo hm th in t [email protected].
H ni 12-2011
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Mc lcLI GII THIU ........................................................................................ 3 DANH SCH CC K HIU VIT TT .............................................. 11 Chng 1: CC KIN THC C S ..................................................... 15 1. Cc khi nim chung .......................................................................... 16 1.1. Transitor ....................................................................................... 16 1.2. Vi mch s tch hp ..................................................................... 17 1.3. Cng logic .................................................................................... 18 1.4. Phn t nh .................................................................................. 20 1.5 Mch logic t hp ......................................................................... 23 1.6. Mch logic tun t ....................................................................... 24 1.7 Cc phng php th hin thit k. .............................................. 25 2. Yu cu i vi mt thit k logic ..................................................... 27 3. Cc cng ngh thit k mch logic s ................................................ 28 4. Kin trc ca cc IC kh trnh ........................................................... 31 4.1. Kin trc PROM, PAL, PLA, GAL............................................. 31 4.2. Kin trc CPLD, FPGA ............................................................... 36 Cu hi n tp chng 1 ........................................................................ 39 Chng 2: NGN NG M T PHN CNG VHDL ......................... 41 1. Gii thiu v VHDL........................................................................... 42 2. Cu trc ca chng trnh m t bng VHDL ................................... 43 2.1. Khai bo th vin......................................................................... 44 2.2. M t thc th .............................................................................. 45 2.3. M t kin trc ............................................................................. 48 2.4. Khai bo cu hnh ........................................................................ 53 3. Chng trnh con v gi .................................................................... 56 5
3.1. Th tc ......................................................................................... 56 3.2. Hm.............................................................................................. 58 3.3. Gi ............................................................................................... 59 4. i tng d liu, kiu d liu .......................................................... 62 4.1. i tng d liu ......................................................................... 62 4.2. Kiu d liu ................................................................................. 63 5. Ton t v biu thc .......................................................................... 70 5.1. Ton t logic ................................................................................ 70 5.2. Cc php ton quan h ................................................................. 71 5.3. Cc php ton dch ...................................................................... 72 5.4. Cc php ton cng tr v hp .................................................... 74 5.5. Cc php du................................................................................ 74 5.6. Cc php ton nhn chia, ly d .................................................. 75 5.7. Cc php ton khc ...................................................................... 76 6. Pht biu tun t ................................................................................ 76 6.1. Pht biu i ................................................................................ 76 6.2. Pht biu xc nhn v bo co ..................................................... 79 6.3. Pht biu gn bin........................................................................ 80 6.4. Pht biu gn tn hiu .................................................................. 81 6.5. Lnh r nhnh v lnh lp............................................................ 83 7. Pht biu ng thi ............................................................................ 87 7.1. Pht biu khi .............................................................................. 88 7.2. Pht biu qu trnh ....................................................................... 89 7.3. Pht biu gn tn hiu ng thi .................................................. 92 7.4. Pht biu generate ........................................................................ 95 7.5. Pht biu ci t khi con ............................................................ 97 8. Phn loi m ngun VHDL................................................................ 99 9. Kim tra thit k bng VHDL. ......................................................... 101 6
9.1. Kim tra nhanh .......................................................................... 102 9.1. Kim tra t ng nhiu t hp u vo ..................................... 104 Bi tp chng 2 .................................................................................. 111 Bi tp .................................................................................................. 111 Cu hi n tp l thuyt ....................................................................... 116 Chng 3: THIT K CC KHI MCH DY V T HP THNG DNG ................................................................................................................. 117 1. Cc khi c bn ................................................................................ 118 1.1. Khi cng n gin ................................................................... 118 1.2. Khi tr ...................................................................................... 119 1.3. Khi cng thy nh trc. ......................................................... 121 1.4. Thanh ghi ................................................................................... 125 1.5. B cng tch ly ......................................................................... 127 1.6. B m ....................................................................................... 129 1.7. B dch ....................................................................................... 131 1.8. Thanh ghi dch ........................................................................... 133 2. Cc khi nh .................................................................................... 136 2.1. B nh RAM ............................................................................. 136 2.2. B nh ROM ............................................................................. 139 2.3. B nh FIFO .............................................................................. 141 2.4. B nh LIFO.............................................................................. 142 3. My trng thi hu hn .................................................................... 143 4. Khi nhn s nguyn........................................................................ 145 4.1. Khi nhn s nguyn khng du dng phng php cng dch 146 4.2. Khi nhn s nguyn c du...................................................... 150 4.3. Khi nhn dng m ha Booth c s 4 ..................................... 155 5. Khi chia s nguyn ......................................................................... 158 5.1. Khi chia dng s khi phc phn d .................................. 159 7
5.2. Khi chia dng s khng khi phc phn d ....................... 162 5.3. Khi chia s nguyn c du ....................................................... 164 6. Cc khi lm vic vi s thc .......................................................... 169 6.1. S thc du phy tnh ................................................................ 169 6.2. S thc du phy ng .............................................................. 170 6.3. Ch lm trn trong s thc du phy ng........................... 173 6.4. Php cng s thc du phy ng ............................................. 176 6.5. Php nhn s thc du phy ng ............................................. 181 6.6. Php chia s thc du phy ng .............................................. 183 Bi tp chng 3 .................................................................................. 186 Bi tp ............................................................................................... 186 Cu hi n tp l thuyt .................................................................... 194 Chng 4: THIT K MCH S TRN FPGA ................................... 195 1. Tng quan v kin trc FPGA ......................................................... 196 1.2. Khi nim FPGA ....................................................................... 196 1.3. ng dng ca FPGA trong x l tn hiu s ............................. 198 1.4. Cng ngh ti cu trc FPGA .................................................... 199 1.5. Kin trc tng quan ................................................................... 200 2. Kin trc chi tit Xilinx FPGA Spartan-3E. .................................... 201 2.1. Khi logic kh trnh ................................................................... 204 2.2. Khi iu khin vo ra............................................................... 221 2.3. H thng kt ni kh trnh ......................................................... 224 2.4. Cc phn t khc ca FPGA ...................................................... 227 3. Quy trnh thit k FPGA bng ISE .................................................. 237 3.1. M t thit k ............................................................................. 238 3.2. Tng hp thit k ....................................................................... 239 3.3. Hin thc ha thit k ................................................................ 244 3.4. Cu hnh FPGA ......................................................................... 250 8
3.5. Kim tra thit k trn FPGA ...................................................... 250 4. Mt s v d thit k trn FPGA bng ISE ...................................... 251 4.1. Thit k khi nhn thng tin UART .......................................... 253 4.2. Thit k khi iu khin PS/2 cho Keyboard, Mouse ............... 267 4.3. Thit k khi tng hp dao ng s NCO ................................. 270 4.4. Thit k khi iu khin LCD1602A ........................................ 282 4.5. Thit k iu khin VGA trn FPGA. ....................................... 294 Bi tp chng 4 .................................................................................. 308 1. Bi tp c s ................................................................................. 308 2. Bi tp nng cao............................................................................ 309 3. Cu hi n tp l thuyt ................................................................ 312 PH LC ................................................................................................ 313 Ph lc 1: THNG K CC HM, TH TC, KIU D LIU CA VHDL TRONG CC TH VIN CHUN IEEE. ........................................ 314 1. Cc kiu d liu h tr trong cc th vin chun IEEE ............... 314 2. Cc hm thng dng h tr trong cc th vin chun IEEE ........ 315 3. Cc hm phc v cho qu trnh m phng kim tra thit k ........ 319 4. Cc hm bin i kiu d liu dng trong VHDL ....................... 322 Ph lc 2: THC HNH THIT K VHDL ...................................... 325 Bi 1: M phng VHDL trn ModelSim .......................................... 326 Bi 2: Xy dng b cng tr trn c s khi cng bng ton t...... 338 Bi 3: Khi dch v thanh ghi dch ................................................... 344 Bi 4: B cng bit ni tip dng 1 FA (serial-bit adder) .................. 353 Ph lc 3: MCH PHT TRIN NG DNG FPGA ...................... 364 1. Gii thiu tng quan ..................................................................... 364 2. Cc khi giao tip c trn mch FPGA ........................................ 366 2.4. Khi giao tip Keypad .................................................................. 367 2.5. Khi 8x2 Led-Diod ....................................................................... 367 9
2.6. Khi Switch................................................................................... 367 2.7. Khi giao tip 4x7-seg Digits ....................................................... 367 2.9. Khi giao tip USB ....................................................................... 368 2.10. Khi giao tip PS/2 ..................................................................... 368 Ph lc 4: THC HNH THIT K MCH S TRN FPGA ........ 371 Bi 1: Hng dn thc hnh FPGA bng Xilin ISE v Kit SPARTAN 3E ................................................................................................................. 372 Bi 2: Thit k khi giao tip vi 4x7Seg -digits ............................. 397 Ph lc 5: CC BNG M THNG DNG ..................................... 407 1. M ASCII iu khin .................................................................... 408 2. M ASCII hin th ........................................................................ 410 3. Bng m k t cho LCD 1602A ................................................... 414 TI LIU THAM KHO ....................................................................... 415
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DANH SCH CC K HIU VIT TTAES ALU ASIC BJT BRAM CLA CLB CMOS : Advance Encryption Standard : Arithmetic Logic Unit : Aplication Specific Intergrated Circuit : Bipolar Junction Transitor : Block RAM : Carry Look-Ahead Adder : Configurable Logic Block : CMOS (ComplementarySymmetry Metal-Oxide Sermiconductor) : Complex Programmable Logic Device : Digital Clock Manager Thut ton m ha AES Khi thc thi s hc logic Vi mch tch hp vi chc nng chuyn dng. Transitor lng cc Khi nh truy cp ngu nhin trong FPGA Khi cng thy nh trc Khi Logic kh trnh trong FPGA Cng ngh bn dn dng trn cp b PN transitor trng.
Vi mch kh trnh phc tp( c ln) Khi qun l v iu chnh DCM xung nhp h thng trong FPGA : Double Data Rate Truyn d liu vi tc gp DDR i tc cung nhp h thng : Data Encryption Standard Thut ton m ha DES DES : Digital Frequency Synthesis Khi tng hp tn s DFS : Delay Locked Loop Khi lp kha tr DLL : Dynamic RAM RAM ng DRAM : Design Rule Check Kim tra cc vi phm trong thit DRC k : Device Under Test i tng c kim tra DUT 2 E PROM : Electric-Eraseable Programmable PROM c th xa bng in ROM : Electronic Design Interchange Chun cng nghip m t EDIF Format cc khi in t. :Embbed Develovepment Kit T hp phn mm thit k h EDK nhng trn FPGA CPLD 11
PROM c th xa oc Khi chn knh m rng trong FPGA : Field Effect Transitors Transitor dng hiu ng trng FET : First In First Out B nh c d liu vo trc s FIFO c c ra trc. Khi chn knh m rng trong FiMUX : Wide-Multiplexer FPGA : Field-Programmable Gate Array IC kh trnh cp ngi dng FPGA cui : Floating Point Unit Khi x l s thc du phy FPU ng : Generic Array Logic IC kh trnh trn cng ngh GAL CMOS : Hardware Description Language Ngn ng m t phn cng HDL : Inter-Integrated Circuit Giao tip I2C truyn d liu I2C gia cc IC : Integrated Circuit Vi mch tch hp IC : Institute of Electrical and Vin k thut in v in t IEEE Electronics Engineers : Input/Output Buffer Khi m vo ra trong FPGA IOB Thit k c ng k s hu IP Core : Intellectual Property core tr tu : Integrated Software Enviroment T hp phn mm thit k ISE FPGA ca Xilinx : Last In First Out Khi nh LIFO, d liu vo sau LIFO cng s ra trc nht : Large scale integration Vi mch tch hp c ln LSI : Look-Up Table Bng tham chiu trong FPGA LUT Transitor trng dng tip gio MOSFET : Metal-oxide-sermiconductor Field-Effect-Transitors kim loi bn dn : Medium scale integration Vi mch tch hp c trung MSI Khi nhn chuyn dng trong MULT18 : Dedicated Multiplier 18 x18 FPGA : Native Circuit Database nh dng sau qu trnh nh x NCD EPROM : Eraseable Programmable ROM F5MUX : Wide-Multiplexer 12
NCF NGD PAL PAR PCF PLA PLD PROM PS/2
: Native Constraint File : Native Generic Database : Programmable Array Logic : Place and Route : Physical Constraint File : Programmable Logic Array : Programmable Logic Device : Programmable Read-Only Memory : IBM Personal System 2
cng v Sp t kt ni ca Xilinx ISE. Tp ci t iu kin rng buc c bn ca thit k. nh dng sau qu trnh Translate ca Xilinx ISE Mng logic kh trnh Sp t v kt ni (trong qu trnh hin thc ha FPGA Tp quy nh cc rng buc vt l ca thit k trn ISE Mng cc khi logic kh trnh Vi mch kh trnh B nh ROM kh trnh Chun giao tip cho cc ngoi vi nh chut, bn phm trn my tnh ca IBM B nh truy cp ngu nhin Thut ton m ha RSA
RAM RSA
RTL SDK
: Read Only Memory : Ronald Rivest, Adi Shamir & Leonard Adleman Cryption Schema : Register Tranfer Level : Software Development Kit
: Shift-Register 16 bit SHL16 SLICEL : SLICE Logic SLICEM : SLICE Memory
SoC SPI SPLD
: System On a Chip : Serial Peripheral Interface : Simple Programmable Logic
M t lp thanh ghi truyn ti T hp cc chng trnh h tr thit k phn mm nhng ca Xilinx Thanh ghi dch 16 bit Phn t Logic trong FPGA Phn t Logic c kh nng thc hin chc nng nh trong FPGA H thng tch hp trn mt chp n. Chun kt ni ngoi vi ni tip
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SRAM SSI UART UCF
ULSI VGA VHDL VLSI WSI XPS XST
Device : Static Random Access Memory RAM tnh : Small scale integration Vi mch tch hp c nh : Universal Asynchronous Receiver Chun truyn tin d b ni tip Transceiver : User Constraint File Tp quy nh cc iu kin rng buc cho thit k bi ngi dng. : Ultra large scale intergration : Video Graphic Array Chun kt ni vi mn hnh my tnh : Very Hi-speed Integrated Circuit Ngn ng m t vi mch s tch Hardware Description Language hp : Very large scale integration Vi mch tch hp c rt ln : Wafer scale intergration : Xilinx Platform Studio Chng trnh phn mm h tr xy dng h nhng trn FPGA : Xilinx Synthesis Technology Chng trnh tng hp thit k ca Xilinx
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Chng 1 CC KIN THC C SChng m u c nhim v cung cp cho ngi hc nhng kin thc, khi nim c bn v thit k cc khi s, trong c nhng kin thc c nhc li vi nhng b xung ph hp vi mc ch mn hc. Ngi hc c gii thiu qua v cch thc thit khi lm vic vi tn hiu s c thit k ch to, phn loi cc dng vi mch s v cc tham s c bn cn quan tm khi thit k hay lm vic vi vi mch s. Chng ny cng gii thiu qua v s pht trin ca mt lp cc IC kh trnh phn cng t PROM cho ti FPGA. Mc ch ca phn ny gip cho ngi hc c mt ci nhn tng quan v lch s ca thit k logic s trc khi tp trung vo cc vn kin thc chnh cc chng sau l ngn ng m t phn cng VHDL v cng ngh FPGA.
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1. Cc khi nim chung1.1. Transitor L linh kin bn dn c kh nng lm vic nh mt cng tc bt tt hoc dng khuch i tn hiu. Transitor l phn t c bn ca mi vi mch s tch hp, t cc cng logic n gin AND, OR, NOT... n cc loi phc tp nh cc mch iu khin ngoi vi, vi iu khin, vi x l Transitor c lm t vt liu bn dn (sermiconductor), l vt liu va c kh nng dn in va c kh nng lm vic nh nhng vt liu cch in, kh nng ny thay i ty theo kch thch t bn ngoi nh nhit , nh sng, trng in t, dng in Cht bn dn dng cu to transitor thng l Germany (Ge) hoc Silicon (Si) c kch tp mt lng nh Photpho(P) hoc Boron (B) vi mc ch tng mt electron (kiu N) t do hoc tng mt l trng (kiu P) tng ng trong tinh th bn dn. Cu trc nguyn l ca cc dng transitor c trnh by hnh di y:
Hnh 1-1. Cu trc transitor lng cc BJTS, n cc FETs, diode Transitor lng cc BJT (Bipolar Junction Transitor) s dng nhiu trong thp k 80s, c im ca BJT l tc chuyn mch nhanh nhng nhc im l mc tiu th nng lng ln ngay c trong trng thi ngh v chim nhiu din tch. Sau BJTs dn c thay th bng transitor n cc FETs(Field Effect Transitors) lm vic trn hiu ng trng v knh dn ch dng mt loi bn dn loi p hoc n. MOSFETs (Metal-oxide-sermiconductor Field-Effect-Transitors) l transitor FETs nhng dng cc Cng metal (v sau lp metal c thay bng polysilicon) ph trn mt lp oxide cch in v lp ny ph trn vt liu bn 16
dn, ty theo loi vt liu bn dn m transitor ny c tn gi l NMOS (knh dn n) v PMOS (knh dn p). CMOS (Complementary-Symmetry Metal-Oxide Sermiconductor) l transitor to thnh t vic ghp cp b PMOS v NMOS, c nhiu u im so vi cc dng transitor c nh hiu in th lm vic thp, chng nhiu cao, tiu tn t nng lng v cho php tch hp trong IC s vi mt cao. CMOS l cng ngh transitor c s dng rng ri nht hin nay. 1.2. Vi mch s tch hp Cn c gi l IC Intergrated Circuits, chip, l cu trc mch in c thu nh bng cch tch hp ch yu t cc transitor vi mt cao, ngoi ra cn c th c cc linh kin in th ng khc trn mt khi bn dn mng. Cc vi mch tch hp u c mt s lng tn hiu u vo v u ra thc hin mt chc nng c th no . Trong khun kh gio trnh ny ch yu nghin cu v vi IC s, tc l dng IC ch lm vic vi cc tn hiu s.
...
Hnh 1-2: a) M hnh Vi mch s tch hp b) Vi mch tch hp thc t Vi mch tch hp ra i t nhng nm 1960s v c ng dng rng ri trong thc t, v ang to ra cuc cch mng trong lnh vc in t. V d v vi mch tch hp nh cc IC a dng (general purposes IC) h 7400, 4000, cc dng vi x l 80x86 dng trong my vi tnh, chp x l dng cho in thoi di ng, my nh k thut s, cc vi iu khin dng trong cc thit b dn dng, ti vi, my git, l vi sng Cc vi mch ny c mt tch hp t hng vi chc n hng trm triu, v hin nay n hng t transitor trong mt ming bn dn c kch thc xp x kch thc ng xu. Mt tch hp c nh ngha l tng s nhng phn t tch cc (transitor hoc cng logic) cha trn mt n v
...a)
IC
b)
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din tch ca khi tinh th bn dn. Theo mt tch hp chia ra cc loi vi mch sau: - Vi mch c nh SSI (Small scale integration), c hng chc transitor trong mt vi mch. - Vi mch c va MSI (Medium scale integration), c hng trm transitor trong mt vi mch. - Vi mch c ln LSI (Large scale integration), c hng ngn n hng chc ngn transitor trong mt vi mch. - Vi mch cc ln VLSI (Very large scale integration), c hng vn, hng triu, hng chc triu transitor v ln hn trong mt vi mch, ti thi im hin nay xut hin nhng vi mch c tch hp n hng t transitor. - Vi mch siu ln ULSI (Ultra large scale intergration), vi mch c tch hp vi mc hng triu transitor tr ln. - WSI (Wafer-scale-Intergration) l gii php tch hp nhiu vi mch chc nng trn mt tm silicon (wafer) tng hiu sut cng nh gim gi thnh sn phm, v d h vi x l nhiu nhn c tch hp bng WSI. - SoC (System-on-a-Chip) Khi nim ch mt h tnh ton, x l m tt c cc khi chc nng s v c tng t c thit k tch hp vo trong mt chip n. Trong khun kh chng trnh ny s dnh thi lng chnh cho vic nghin cu c bn v cng ngh, phng php, qu trnh thit k cc vi mch c LSI, VLSI. 1.3. Cng logic Cng logic hay logic gate l cu trc mch in (s khi hnh ) c lp rp t cc linh kin in t thc hin chc nng ca cc hm logic c bn y = f(xn, xn-1,..., x1, x0). Trong cc tn hiu vo xn-1, xn-2,..., x1, x0 ca mch tng ng vi cc bin logic xn-1, xn-2,..., x1, x0 ca hm . Tn hiu ra y ca mch tng ng vi hm logic y. Vi cc cng c bn thng gi tr n 4.x0 y x1-------
LOGIC GATE
xn
Hnh 1-3. M hnh cng logic c bn
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Gi tr ca cc tn hiu vo v ra ch c hai mc l mc thp (Low - L) v mc cao (High - H) tng ng vi vi hai gi tr 0 v 1 ca cc bin logic v hm logic. V d: Mt cng NOT loi CMOS (hnh 1.4) tng ng hm NOT hai bin Q = not A.
Hnh 1-4. Mch in cng NOT Trn s d nhn thy rng, ch khi A c mc tch cc cao th transitor trn ng cn transitor di m, Q c mc tch cc thp, khi A c mc tch cc thp th transitor trn m v di ng nn Q c mc tch cc cao, nh vy mch in vi s trn thc hin vai tr ca cng NOT. Cc mch logic u c biu din bng cc h hm logic v do c th pht biu l: Mi mch logic u c th xy dng t cc cng logic c bn. i vi cc cng logic c bn th c hai tham s thi gian c bn:
Hnh 1.5. Tham s thi gian ca cng NOT Thi gian tr lan truyn Tpd (Propagation delay) l thi gian ti thiu k t thi im bt u xy ra s thay i t u vo X cho ti khi s thay i ny to ra ra thay i xc nh ti u ra Y, hay ni mt cch khc cho ti khi u ra Y n nh gi tr. 19
Tcd (Contamination delay) l khong thi gian k t thi im xut hin s thay i ca u vo X cho ti khi u ra Y bt u xy ra s mt n nh. Sau giai on mt n nh hay cn gi l giai on chuyn tip tn hiu ti u ra s thit lp trng thi xc nh vng bn. Nh vy Tpd > Tcd v khi nhc n tr ca cng th l ch ti gi tr Tpd. 1.4. Phn t nh 1.4.1. D-Latch v D flip-flop Latch v Flip-Flop l cc phn t nh quan trng trong thit k VLSI, s cu to chi tit v m t c trnh by k trong phn K thut s. phn ny ch nhc li nhng tnh cht c bn nht ca cc Flip-Flop v b xung thm cc tham s thi gian thc ca cc phn t ny. Bng 1-1 D-Flip flop v D-latch D-flip flop D-latch D Q Clock D Q Qprev Clock D Q Q Rising edge 1 1 x 0 X Qprev Rising edge 0 0 x 1 D Non-rising x Qprev D-Latch l phn t nh lm vic theo mc xung, c th khi tn hiu Clock bng 1 th gi tr Q u ra bng gi tr u vo, khi tn hiu Clock = 0 th gi tr u ra khng i. Ni mt cch khc D-latch lm vic nh mt ca ng m gia tn hiu Q v D tng ng vi mc in p ca xung Clock. D-flip-flop l phn t nh lm vic theo sn xung, c hai dng sn l sn ln (rising edge) khi xung thay i t 0->1 v sn xung (falling edge) khi xung thay i t 1->0. Khi khng c yu cu g c bit th Flip-flop lm vic vi sn xung ln thng c s dng. Khc vi D-latch gi tr u ra ca FlipFlop ch thay vo thi im sn xung . Vi cch lm vic nh vy gi tr u ra s khng thay i trong sut thi gian mt chu k xung nhp d cho tn hiu u vo thay i. D Flip-flop rt hay c dng trong mch c nh v vy i khi ni n phn t nh thng ngm hiu l D Flip-flop.SET CLR
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In Clk
Out
In Out Clk
In Clk
Out
In Out Clk
Latch
Flip-Flop
Hnh 1-6. th thi gian ca D Flip-flop v D Latch i vi D-flip-flop v D-latch nh th c hai tham s thi gian ht sc quan trng l Tsetup, v Thold. y l tham s thi gian i vi d liu u vo cng Din m bo vic truyn d liu sang cng ra Qout l chnh xc, c th i vi Flip-flop. Tsetup: l khong thi gian cn thit cn gi n nh u vo trc sn tch cc ca xung nhp Clock Thold: L khong thi gian ti thiu cn gi n nh d liu u vo sau sn tch cc ca xung nhp Clock.Din Tsetup Thold CLK Tclk_q Qout
Hnh 1-7. Tham s thi gian ca D-Flip-Flop 1.4.2 Cc flip-flop khc - RS Flip-flop: Bng 1-2 RS Flip-flopR 0 0 1 1 S 0 1 0 1 Qnext Qprev 1 0 Chy uaSSET
Q
R
CLR
Q
21
RS Flip-flop c u vo l hai tn hiu Reset v Set. Set =1 th tn hiu u ra nhn gi tr 1 khng ph gi tr hin ti Q, Reset =1 th u ra Q = 0 khng ph thuc gi tr hin ti Q. i vi RS-flipflop khng ng b th gi tr Q thay i ph thuc R/S ngay tc th, cn i vi RS flip-flop ng b th tn hiu Q ch thay i ti thi im sn xung Clock. Trng thi khi R= 1, S= 1 l trng thi cm v kh u ra nhn gi tr khng xc nh, thc cht s xy ra s thay qu trnh chy ua hay t dao ng gi tr Q t 0 n 1 v ngc li vi chu k bng tr chuyn mch ca flip-flop. - JK-flip-flop Bng 1-3 JK Flip-flopJ 0 0 1 1 K 0 1 0 1 Qnext Qprev 0 1 NOT QprevJSET
Q
K
CLR
Q
-
Theo bng chn l JK-flip flip hot ng kh linh hot thc hin chc nng ging nh D-flip flop hoc RS flip-flop, trng thi kh J=0, K=1 l Reset, J=1, K=0 l Set. Tuy khng c u vo d liu D nhng JK flip-flop lm vic nh mt D-flip flip th tn hiu D ni vi J cn K cho nhn gi tr i ca J. T- flip-flop Bng 1-4 T Flip-flopT 0 0 1 1 Q 0 1 0 1 Qnext 0 1 1 0
Khi T bng 1 th gi tr Qnextbng o ca gi tr trc Qprev khi T = 0 th gi tr u ra khng thay i
22
1.5 Mch logic t hp Mch logic t hp (Combinational logic circuit) l mch m gi tr t hp tn hiu ra ti mt thi im ch ph thuc vo gi tr t hp tn hiu vo ti thi im . Hiu mt cch khc mch t hp khng c trng thi, khng cha cc phn t nh m ch cha cc phn t thc hin logic chc nng nh AND, OR, NOT i vi mch t hp tham s thi gian tr Tdelay l khong thi gian ln nht k t thi im xc nh tt c cc gi tr u vo cho ti thi im tt c cc kt qu u ra tr nn n nh. Trn thc t vi vi mch tch hp vic thi gian tr rt nh nn vic tm tham s tr ca mch c thc hin bng cch lit k tt c cc ng bin i tn hiu c th t tt c cc u vo ti tt c u ra sau da trn thng s v thi gian ca cc cng v tr ng truyn c th tnh c tr ca cc ng truyn ny v tm ra ng truyn c tr ln nht, gi tr chnh l Tdelay.
Hn h 1-8. tr ca mch t hp Minh ha cho tr trong mch t hp nh hnh 1-8. V l thuyt xc nh tr ca mch cn lit k tt c cc ng tn hiu t 4 u vo In1, In2, In3, In4 n 2 u ra Out1, Out2. i vi mi cp u ra u vo tn ti nhiu ng truyn khc nhau v vy tng s lng cc ng truyn ny thng rt ln. Chnh v th i vi nhng mch t hp ln th vic xc nh tr u phi thc hin bng s h tr ca my tnh. V d xc nh tr ca hai ng truyn 1 v 2 trn hnh v: ng 1 ln lt i qua cc cng NOT, AND_4, NOR, AND_3, OR. ng 2 ln lt i qua cng NOT, AND, OR_4, AND_4, OR_4. tr ca cc ng truyn ny tnh bng tr ca cc cng n i qua cng vi tr dy dn (TWrite). 23
T1 = TNOT + TAND_4 + TNOR + TAND_3 + T AND_3 + TWire1 (1.1) T2 = TNOT + TAND + TOR_4 + TAND_4 + T OR_4 + TWire2 (1.2) Do tr ca cng nhiu u vo ln hn tr ca cng t u vo nn mc d s cng i qua trn ng truyn nh nhau nhng ng truyn 2 s c tr ln hn ng 1. Cc ng truyn c tr ln nht c gi l Critical paths. Cc ng truyn ny cn c bit quan tm trong qu trnh ti u ha tr ca mch. 1.6. Mch logic tun t Mch logic dy (Sequential logic circuits) cn c gi l mch logic tun t l mch s m tn hiu ra ti mt thi im khng nhng ph thuc vo t hp tn hiu u vo ti thi im m cn ph thuc vo tn hiu vo ti cc thi im trc . Hiu mt cch khc mch dy ngoi cc phn t t hp c cha cc phn t nh v n lu tr ln hn mt trng thi ca mch. Tham s thi gian ca mch tun t c tnh khc vi mch t hp, s khc bit c quan h mt thit vi c im ca tn hiu ng b Clock. V d vi mt mch tun t in hnh di y. Mch to t hai lp thanh ghi s dng Flip-flop A v B, trc gia v sau thanh ghi l ba khi logic t hp Combinational logic 1, 2, 3, cc tham s thi gian c th nh sau: Td1, Td2, Td3. L thi gian tr tng ng ca 3 khi mch t hp 1, 2, 3. Tsa, Tsb l thi gian thit lp (Tsetup) ca hai Flipflop A, B tng ng Tclk-q. l khong thi gian cn thit d liu ti u ra Q xc nh sau thi im kch hot ca sn ClockDCombinational logic1CLR SET
QCombinational logic2
D
SET
QCombinational logic3
Q
CLR
Q
Tskew Td1 Tsa Tclk-q Td2 Tsb Tclk-q Td3
Hnh 1-9. Tham s thi gian ca mch tun t i vi mch ng b th s l l tng nu nh im kch hot (sn ln hoc sn xung) ca xung nhp Clock ti cc Flip-flop cng mt thi im. Tuy vy trn thc t bao gi cng tn ti tr gia hai xung Clock n hai Flip-flop khc nhau. Tskew l tr ln nht ca xung nhp Clock n hai Flip-flop khc 24
nhau trong mch. Thi gian chnh lch ln nht gia tn hiu xung nhp , thi gian tr ny sinh ra do tr trn ng truyn ca xung Clock t A n B. Trn thc t Tskew gia hai Flip-flop lin tip c gi tr rt b so vi cc gi tr tr khc v c th b qua, nhng i vi nhng mch c ln khi s lng Flip-flop nhiu hn v phn b xa nhau th gi tr Tskew c gi tr tng i ln. Nhng tham s trn cho php tnh ton cc c trng thi gian ca mch tun t l: - Thi gian tr trc xung nhp Clock ti u vo Tinput_delay = Td1 + Tsa (1.3) - Thi gian tr sau xung nhp Clock ti u ra. Toutput_delay = Td3 + Tclk_q (1.4) - Chu k ti thiu ca xung nhp Clock, hay l khong thi gian ti thiu m bo cho d liu trong mch c x l v truyn ti gia hai lp thanh ghi lien tip m khng xy ra sai st. Nu xung nhp u vo c chu k nh hn Tclk_min th mch s khng th hot ng theo thit k. Tclk_min = Tclk-q + Td2 + Tsb + Tskew (1.5) - T tnh c xung nhp ti a ca vi mch l Fmax = 1/ Tclk_min = 1/( Tclk-q + Td2 + Tsb + Tskew) (1.6) 1.7 Cc phng php th hin thit k. C hai phng php c bn c s dng m t vi mch s l m t bng s logic (schematic) v m t bng ngn ng m t phn cng HDL (Hardware Description Language). M t bng s : vi mch c m t trc quan bng cch ghp ni cc phn t logic khc nhau mt cch trc tip ging nh v d hnh v di y. Thng thng cc phn t khng n thun l cc i tng ha m cn c cc c tnh vt l gm chc nng logic, thng s ti vo ra, thi gian tr Nhng thng tin ny c lu tr trong th vin logic thit k. Mch v ra c th c m phng kim tra chc nng v pht hin v sa li mt cch trc tip.
25
D1
U1 U14 AND-2 U2 NOR
D2
AND-2
U3
U13 NOR U12
AND-2 D3 U4
NOR AND-2 U5 U11 AND-2 U6 AND-2 AND-2 U7 R AND-2 U8 NOR U10
SAND-2 U9 AND-2 U15 AND-2
SET
Q
R
CLR
Q
Hnh 1-10. M t mch s bng s u im ca phng php ny l cho ra s cc khi logic r rng thun tin cho vic phn tch mch, tuy vy phng php ny ch c s dng thit k nhng mch c nh, phc tp khng cao. i vi nhng mch c ln hng trm ngn cng logic th vic m t ha l gn nh khng th v nu c th cng tn rt nhiu thi gian, cha k nhng kh khn trong cng vic kim tra li trn mch sau . M t bng HDL: HDL cho php m t vi mch bng cc c php tng t nh c php ca ngn ng lp trnh. C ba ngn ng m t phn cng ph bin hin nay l: Verilog: Ra i nm 1983, do hai k s Phil Moorby v Prabhu Goel lm vic ti Automated Integrated Design Systems (sau ny thuc s hu ca Cadence). Verilog c IEEE chnh thc tiu chun ha vo nm 1995 v sau l cc phin bn nm 2001, 2005. y l mt ngn ng m t phn cng c cu 26
trc v c php gn ging vi ngn ng lp trnh C, ngoi kh nng h tr thit k logic th Verilog rt mnh trong vic h tr cho qu trnh kim tra thit k. VHDL: VHDL vit tt ca Very-high-speed intergrated circuits Hardware Description Language, hay ngn ng m t cho cc mch tch hp tc cao. VHDL ln u tin c pht trin bi B Quc Phng M nhm h tr cho vic thit k nhng vi mch tch hp chuyn dng (ASICs). VHDL cng c IEEE chun ha vo cc nm 1987, 1991, 2002, v 2006 v mi nhts 2009. VHDL c pht trin da trn cu trc ca ngn ng lp trnh Ada. Cu trc ca m t VHDL tuy phc tp hn Verilog nhng mang tnh logic cht ch v gn vi phn cng hn. AHDL: Altera HDL c pht trin bi cng ty bn dn Altera vi mc ch dng thit k cho cc sn phm FPGA v CPLD ca Altera. AHDL c cu trc ht sc cht ch v l ngn ng rt kh s dng nht so vi 2 ngn ng trn. B li AHDL cho php m t thc th logic chi tit v chnh xc hn. Ngn ng ny t ph bin tuy vy n cng c rt nhiu chng trnh phn mm h tr m phng bin dch. Bn cnh cc ngn ng trn th mt lot cc ngn ng khc v ang pht trin cng h tr kh nng m t phn cng, ng ch l System Verilog l phin bn m rng ca Verilog hng ca C++ nh h tr cc kiu d liu khc nhau, s dng Class v nhiu hm h thng bc cao. SystemC khng hon ton phi l mt HDL m l mt dng m rng ca C++ cho php h tr kim tra cc thit k bng VHDL hay Verilog.
2. Yu cu i vi mt thit k logic Yu cu i vi mt thit k IC bao gm: Yu cu chc nng: mch gm c cc u vo u ra nh th no, thc hin nhim v g Yu cu v mt cng ngh: Mch thit k s dng nn cng ngh bn dn no PLD, ASIC, FPGA Yu cu v mt ti nguyn: Gii hn v s lng cng, s lng transitors, v din tch quy i chun, v kch thc ca IC thit k. Yu cu v kh nng lm vic (performance): l yu cu v cc tham s thi gian ca mch bao gm tr cng vo, tr cng ra, tr logic vi mch t hp, cc xung nhp lm vic, s lng xung nhp cho mt chu trnh x l d liu, s lng d liu x l trn mt n v thi gian. 27
Yu cu v mc tiu hao nng lng (power consumtion). Yu cu v chi ph cho qu trnh thit k v ch to (design cost). Cc yu cu k trn c quan h mt thit vi nhau v thng thng chng khng th ng thi t c ti u. V d nng lng tiu th ca mch mun nh th s lng cng s dng hn ch v s hn ch tc lm vic, hoc vic s dng cc cng ngh r tin hn hoc dng cc cng cng xut thp cng l nhn t gim hiu nng lm vic ca mch. Trong thc t Cc IC phc v cc mc ch khc nhau th c yu cu khc nhau v ngi lp k hoch thit k ch to IC cn phi cn i gia cc tiu ch c mt phng n ti u nht. V d cng l vi x l nhng nu dng th khng c yu cu c bit v mt tiu hao nng lng do ngun cp l c nh, khi Chip phi c thit k c hiu sut lm vic ti a. Trong khi vi x l cho my tnh xch tay th cn phi thit k c mc tiu th nng lng thp nht c th hoc c th hot ng nhiu mc tiu th nng lng khc nhau nhm ko di thi gian s dng. Chip iu khin cho cc thit b di ng th cn phi ti u ht mc mc tiu tn nng lng bng cch thu gn thit k, gim thiu nhng tp lnh khng cn thit v s dng cc phn t tit kim nng lng nht
3. Cc cng ngh thit k mch logic sVi mch s n gin c th c thit k th cng (Manual IC design), nhng vi cc vi mch s c ln th qu trnh thit k buc phi s dng cc chng trnh h tr thit k trn my tnh (Design Automation) Manual design: Vi mch s c th c thit k bi cch ghp ni cc linh kin bn dn ri rc. S ra i cc IC a dng h 74XX hay 40XX cho php ngi s dng c th t thit k nhng mch s c nh v c va bng cch ghp ni trn mt bn mch in. Nh c cu trc chun ha, c th d dng ghp ni, to nhng mch chc nng khc nhau. Trn thc t nhng mch dng ny v vn ang c ng dng rng ri. im hn ch duy nht ca nhng thit k dng ny l chng ch ph hp cho nhng thit k SSI n gin do gii hn v mt tch hp v tc lm vic thp.
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IC Design
Manual Design
Design Automation
7400 Series (TTL)
4000 Series (CMOS)
Discrete components
Programable Device Based
Full-custom Semi-custom ASIC ASIC
SPLD
CPLD
Field PD (FPGA)
PROM (EPROM, E2PROM)
PLA
PAL
GAL
Hnh 1-11. Phn loi thit k vi mch s Design Automation My tnh l mt sn phm c trng nht ca nn cng nghip sn xut ch to bn dn nhng ngay sau khi ra i tr thnh cng c c lc cho vic thit k m phng IC ni ring v cc thit b khc ni chung. T ng ha thit k khng nhng gip n gin ha v rt ngn ng k thi gian thit k sn phm m cn em li nhng kh nng m qu trnh thit k th cng bi con ngi khng lm c l: Kh nng lm vic vi nhng thit k phc tp ti c hng nghn n hng t transitor. Kh nng x l nhng bi ton ti u vi nhiu tiu ch v nhiu iu kin rng buc phc tp. Kh nng t ng tng hp thit k t cc mc tru tng cao xung cc mc tru tng thp hn mt cch chnh xc, nhanh chng. n gin ha vic lu tr v trao i d liu thit k. Cc phn mm h tr thit k gi chung l CAD Tools, trong lnh vc thit k ASIC c 3 h thng phn mm ph bin ca Cadence, Synopsys, Magma Design Automation Inc. Trong thit k trn FPGA ph bin c Xilinx, Altera.
29
Trong t ng ha thit k IC thng phn bit thnh nhng quy trnh nh sau: Full-custom ASIC: l quy trnh thit k IC c mc chi tit cao nht nhm thu c sn phm c hiu qu lm vic cao nht trong khi vn t ti u v mt ti nguyn trn nn mt cng ngh bn dn nht nh. t c mc ch thit k khng nhng c ti u nhng mc cao m cn c ti u mc b tr transitor v kt ni gia chng, v dng hai khi logic cng thc hin hm OR nhng phn b hai v tr khc nhau th c cu trc bng cc mch transitor khc nhau, ph thuc vo cc thng s khc nh ti u vo u ra, v tr, nh hng cc khi lin kChnh v th Full-custom ASIC i khi cn c gi l random-logic gate networks ngha l mch to bi nhng cng khng ng nht. Semi-custom ASIC design: Phn bit vi Full-custom ASIC design, khi nim ny ch quy trnh thit k m mc chi tit khng t n ti a, thng thng thit k t chi tit n mc cng logic hoc cao hn. Do Full-custom ASIC c phc tp cao nn khng nhng chi ph cho qu trnh thit k rt ln mt khc thi gian dnh cho thit k c th ko di hng vi nm tr ln, trong thi gian c th c nhng cng ngh mi ra i, mi mt thay i nh ko theo vic phi lm li gn nh ton b thit k v pht sinh thm chi ph rt nhiu do vy li nhun sn phm bn ra thp hay thm ch thua l. Semi-custom ASIC cn bng gia chi ph thit k v li nhun thu c sn phm bng cch y nhanh v gim thiu chi ph cho qu trnh thit k, d nhin b li sn phm lm ra khng t c mc ti u l thuyt nh Full-custom design. C nhiu dng Semi-custom design nhng mt trong nhng kiu c bn m thng c s dng l thit k trn c s th vin cng chun (Standard Cell Library), th vin ny l tp hp ca cc cng logic nh AND, OR, XOR, thanh ghi v v chng c cng kch thc chiu cao nn c gi l cng chun. ASIC based on Programmable Device: Thit k ASIC trn c s IC kh trnh. Chp kh trnh (Programmable device) c hiu l IC cha nhng phn t logic c th c lp trnh can thip ti cu trc nhm thc hin mt chc nng no . Qu trnh ti cu trc thc hin thng qua ngn ng m t phn cng nn thng c gi ngn gn l lp trnh. IC kh trnh c chia thnh cc dng sau: SPLD (Simple Programmable Logic Device) Nhm nhng IC kh trnh PROM, PAL, PLA, GAL. c im chung ca nhm ny l cha mt s lng 30
cng tng ng t vi chc (PROM) n vi trm (PAL, GAL) cng, nhm ny s dng cu trc ca b nh ROM lu cu hnh IC, (v vy nhm ny cn gi l Memory-based PLD), cu trc ny bao gm mt mng ma trn AND v mt mng ma trn OR c th cu trc c. Trong cc chip dng ny li chia lm hai, th nht l loi ch lp trnh mt ln, v loi c kh nng ti lp trnh dng cc cng ngh nh EEPROM hay EPROM. Cu trc c th v nguyn l lm vic ca PROM, PAL, PLA, GAL, FPGA, CPLD s c ln lt c trnh by chi tit phn tip theo. CPLD (Complex Programmable Logic Device) CPLD l IC lp trnh phc tp thng c ghp t nhiu cc SPLD trn mt chip n. S cng tng ng ca CPLD t t hng nghn n hng chc nghn cng. FPGA (Field-Programmable Gate Array) l IC kh trnh cu trc t mng cc khi logic lp trnh c. Nu nh i vi cc PLD khc vic ti cu trc IC c thc hin trong iu kin ca nh my sn xut bn dn, qu trnh ny cn nhng mt n cho quang khc nn s dng lp nhng PLD ny c gi chung bng thut ng Mask-Programmable Device. FPGA phn bit chnh vi cc loi trn kh nng ti cu trc IC bi ngi dng cui hay chnh l ngi lp trnh IC.
4. Kin trc ca cc IC kh trnhTrong K thut s ta ch ra mi hm logic t hp u c th biu din di dng chun tc tuyn tc l di dng tng ca cc tch y , hoc chun tc hi, tc l dng tch ca cc tng y . Hai cch biu din ny l hon ton tng ng. Nguyn l ny cho php hin thc ha h hm logic t hp bng cch ghp hai mng ma trn nhn (AND) v ma trn cng (OR). Nu mt trong cc mng ny c tnh kh trnh th IC s c tnh kh trnh. Ta s ln lt nghin cu cu trc ca mt s loi IC hot ng trn nguyn l ny. 4.1. Kin trc PROM, PAL, PLA, GAL 4.1.1. PROM PROM (Programmable Read-Only Memory) c pht minh bi Wen Tsing Chow nm 1956 khi lm vic ti Arma Division ca cng ty American Bosch Arma ti Garden, New York. PROM c ch to theo n t hng t lc lng khng qun ca M lc by gi vi mc ch c c mt thit b lu 31
tr cc tham s v mc tiu mt cc an ton v linh ng. Thit b ny dng trong my tnh ca h thng phng tn la Atlas E/F v c gi b mt trong vng vi nm trc khi Atlas E/F tr nn ph bin. PROM l vi mch lp trnh u tin v n gin nht trong nhm cc vi mch bn dn lp trnh c (Programmable Logic Device). PROM c s u vo hn ch, thng thng n 16 n 32 u vo, v vy ch thc hin c nhng hm n gin. Cu trc ca PROM to bi ma trn to bi mng c nh cc phn t AND ni vi mng cc phn t OR lp trnh c.a b c Mng OR lp trnh c
T1
xT2
x x x
x x
T3
T4 T5
x
x x x x x
T6
T7 T8
x
x x x
Mng AND c nh x y z w
Hnh 1-12. Cu trc PROM Ti mng nhn AND, cc u vo s c tch thnh hai pha, v d a thnh pha thun a v nghch , cc chm () trong mng lin kt th hin kt ni cng, tt c cc kt ni trn mi ng ngang sau c thc hin php logic AND, nh vy u ra ca mi phn t AND l mt nhn t tng ng ca cc u vo. V d nh hnh trn thu c cc nhn t T1,T3 nh sau:
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Cc nhn t c gi tip n mng cng OR, mng ny X dng biu din kt ni lp trnh c. trng thi cha lp trnh th tt c cc im ni u l X tc l khng kt ni, tng t nh trn, php OR thc hin i vi ton b cc kt ni trn ng ng v gi ra cc u ra X, Y, Z,... Tng ng vi mi u ra nh vy thu c hm di dng tng ca cc nhn t, v d tng ng vi u ra Y: + (1.6)
Tnh kh trnh ca PROM c thc hin thng qua cc kt ni antifuse (cu ch ngc). Antifuse l mt dng vt liu lm vic vi c ch nh vt liu cu ch (fuse) nhng theo chiu ngc li. Nu nh cu ch trong iu kin kch thch (qu ti v dng in) th nng chy v ngt dng th antifuse trong iu kin tng t nh tc ng hiu th ph hp s bin i t vt liu khng dn in thnh dn in. trng thi cha lp trnh th cc im ni l antifuse ngha l ngt kt ni, khi lp trnh th ch nhng im ni xc nh b t to kt ni vnh vin. Qu trnh ny ch c thc hin mt ln v theo mt chiu v PROM khng th ti lp trnh c. Nhng IC dng PROM c kh nng ti lp trnh l UEPROM (UltravioletEraseable PROM) s dng tia cc tm v EEPROM (Electric-Eraseable PROM) s dng hiu in th ngng cao thit lp li cc kt ni trong ma trn lp trnh. 4.1.2. PAL PAL(Programmable Array Logic) ra i cui nhng nm 1970s. Cu trc ca PAL k tha cu trc ca PROM, s dng hai mng logic nhng nu nh PROM mng OR l mng lp trnh c th PAL mng AND lp trnh c cn mng OR c gn cng, ngha l cc thnh phn tch c th thay i nhng t hp ca chng s c nh, ci tin ny to s linh hot hn trong vic thc hin cc hm khc nhau. Ngoi ra cu trc cng ra ca PAL cn phn bit vi PROM mi u ra ca mng OR lp trnh c c dn bi khi logic gi l Macrocell. Hnh di y minh ha cho cu trc ca macrocell. Mi macrocell cha 1 Flip-Flop Register, hai b dn knh (Multiplexers) 2 v 4 u vo Mux2, Mux4. u ra ca Mux2 thng qua mt cng 3 trng thi tr li mng AND, thit k ny cho
33
kt qu u ra c th s dng nh mt tham s u vo, tt nhin trong trng hp th kt qu u ra buc phi i qua Flip-flop trc.a b c Mng OR c nh
x
x
x
T1
x
x
x
x
T2
x
x
x
x
T3
x
x
x
x
T4
xT5
x
x
x
x
x
Mng AND lp trnh cmacrocell
x
y macrocell
z macrocell
w macrocell
Hnh 1-13. Cu trc PAL u ra ca macrocell cng thng qua cng 3 trng thi c th lp trnh c ni vi cng giao tip ca PAL. Tn hiu iu khin ca Mux4 c th c lp trnh cho php dn tn hiu ln lt qua cc u vo 0,1,2,3 ca Mux4 v gi ra ngoi cng giao tip IO, ty thuc vo cu hnh ny m tn hiu ti IO c th b chn (khng gi ra), dn trc tip t mng OR, thng qua thanh ghi Register. Nh cu trc macrocell PAL c th c s dng khng nhng thc hin cc hm logic t hp m c cc hm logic tun t.
2DSET
Q
3 0 Mux4ENB
IO
CLR
Q
1 S0
S1 programmable
ENB
Mux2
0 1
Hnh 1-14. Cu trc Macrocell 34
4.1.3. PLA PLA (Programable Logic Array) ra i nm 1975 v l chp lp trnh th hai sau PROM. Cu trc ca PLA khng khc nhiu so vi cu trc ca PAL, ngoi tr kh nng lp trnh c hai ma trn AND v OR. Nh cu trc PLA c kh nng lp trnh linh ng hn, b li tc ca PLA thp hn nhiu so vi PROM v PAL v cc sn phm cng loi khc. Thc t PLA c ng dng khng nhiu v nhanh chng b thay th bi nhng cng ngh mi hn nh PAL, GAL, CPLDa b c Mng OR lp trnh c
x
x
x
T1
x
x
x
x
x
x
T2
x
x
x
x
T3
x
x
x
x
T4
xT5
x
x
x
x
x
Mng AND lp trnh c
macrocell
macrocell
macrocell
macrocell
x
y
z
w
Hnh 1-15. Cu trc PLA 4.1.4. GAL GAL (Generic Array Logic) c pht trin bi Lattice Semiconductor company vo nm 1983, cu trc ca GAL khng khc bit PAL nhng thay v lp trnh s dng cng ngh antifuse th GAL dng CMOS electrically erasable PROM, chnh v vy i khi tn gi GAL t c s dng thay v GAL c hiu nh mt dng PAL c ci tin.
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4.2. Kin trc CPLD, FPGA 4.2.1. CPLD Tt c cc chip kh trnh PROM, PAL, GAL, thuc nhm SPLD (Simple Programmable Logic Devices) nhng IC ny c u im l thit k n gin, chi ph thp cho sn xut cng nh thit k, c th chuyn d dng t cng ngh ny sang cng ngh khc tuy vy nhc im l tc lm vic thp, s cng logic tng ng nh do khng p ng c nhng thit k phc tp i hi nhiu v ti nguyn v tc . CPLD (Complex Programmable Logic Devices) c Altera tin phong nghin cu ch to u tin nhm to ra nhng IC kh trnh dung lng ln MAX5000, MAX7000, MAX9000 l h nhng CPLD tiu biu ca hng ny. Sau s thnh cng ca Altera mt lot cc hng khc cng bt tay vo nghin cu ch to CPLD, Xilinx vi cc sn phm XC95xx series, Lattice vi isp Mach 4000 serise, ispMarch XO
Logic block
Logic block
Logic block
Logic block
Programmable Interconnect matrixLogic block Logic block
Logic block
Logic block
Hnh 1-16. Cu trc CPLD Mt cch n gin nht c th hiu CPLD c cu trc bng cch ghp nhiu cc chp SPLD li, thng thng l PAL. Tuy vy v bn cht phc tp ca CPLD vt xa so vi cc IC nhm SPLD v cu trc ca cc CPLD cng rt
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a dng, ph thuc vo tng hng sn xut c th. Di y s trnh by nguyn l chung nht ca cc chip h ny. CPLD c to t hai thnh thnh phn c bn l nhm cc khi logic (Logic block) v mt ma trn kt ni kh trnh PIM (Programmable Interconnect Matrix). Logic block l cc SPLD c ci tin thng cha t 8 n 16 macrocells. Tt c cc Logic block ging nhau v mt cu trc. PIM l ma trn cha cc kt ni kh trnh, nhim v ca ma trn ny l thc hin kt ni gia cc LB v cc cng vo ra IO ca CPLD. V mt l thuyt th ma trn ny c th thc hin kt ni gia hai im bt k. CPLD thng thng s dng cc cng ngh lp trnh ca EEPROM, im khc bit l i vi CPLD thng khng th dng nhng programmer n gin cho PAL, PLA v s chn giao tip ca CPLD rt ln. thc hin cu hnh cho CPLD mi mt cng ty pht trin ring cho mnh mt b cng c v giao thc, thng thng cc chip ny c gn trn mt bo mch in v d liu thit k c ti vo t my vi tnh. Tuy vy cc quy trnh np trn ang dn b thay th bi giao thc chun JTAG (Join Test Action Group) chun, y cng l giao thc dng cu trc cho FPGA m ta s nghin cu k hn chng k tip. Nh k tha cu trc ca SPLD nn CPLD khng cn s dng b nh ROM ngoi lu cu hnh ca IC, y l mt c im c bn nht phn bit CPLD vi cc IC kh trnh c ln khc nh FPGA. 4.2.2. FPGA V cu trc chi tit v c ch lm vic ca FPGA s c dnh ring gii thiu trong chng sau. y ch gii thiu kin trc tng quan nht ca IC dng ny. FPGA c cu thnh t cc khi logic (Logic Block) c b tr di dng ma trn, chng c ni vi nhau thng qua h thng cc knh kt ni lp trnh c H thng ny cn c nhim v kt ni vi cc cng giao tip IO_PAD ca FPGA.
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IO_PAD
IO_PAD
IO_PAD
..
FPGA l cng ngh IC lp trnh mi nht v tin tin nht hin nay. Thut ng Field-Programmable ch qu trnh ti cu trc IC c th c thc hin bi ngi dng cui, trong iu kin bnh thng. Ngoi kh nng FPGA c mt tch hp logic ln nht trong s cc IC kh trnh vi s cng tng ng ln ti hng trm nghn, hng triu cng. FPGA khng dng cc mng lp trnh ging nh trong cu trc ca PAL, PLA m dng ma trn cc khi logic. im khc bit c bn th ba ca FPGA so vi cc IC k trn l c ch ti cu trc, ton b cu hnh ca FPGA thng c lu trong mt b nh ng (RAM), chnh v th m khi ng dng FPGA thng phi km theo mt ROM ngoi vi np cu hnh cho FPGA mi ln lm vic. Kin trc v cch thc lm vic ca FPGA s c nghin cu c th chng th 3 ca gio trnh ny.
IO_PAD IO_PAD IO_PAD
IO_PAD
LOGIC BLOCK
LOGIC BLOCK
..
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
..
IO_PAD
LOGIC BLOCK
.
LOGIC BLOCK
IO_PAD
LOGIC BLOCK
IO_PAD
Hnh 1-17. Kin trc tng quan ca FPGA
.
IP_COREs, RAM, ROM...
Interconnect wires
IO_PAD
..
LOGIC BLOCK
..
IO_PAD
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Cu hi n tp chng 11. Transitor khi nim, phn loi. 2. Khi nim, phn loi vi mch s tch hp. 3. Cng logic c bn, tham s thi gian ca cng logic t hp. 4. Cc loi Flip-flop c bn, tham s thi gian ca Flip-flop. 5. Khi nim mch logic t hp, cch xc nh tr trn mch t hp, khi nim critical paths. 6. Khi nim mch dy, cch tnh thi gian tr trn mch dy, khi nim RTL, phng php tng hiu sut mch dy. 7. Cc yu cu chung i vi thit k mch logic s. 8. Cc phng php th hin thit k mch logic s. 9. Cc cng ngh thit k mch logic s, khi nim, phn loi. 10. Trnh by s lc v cc cng ngh thit k IC s trn chip kh trnh. 11. Nguyn l hin thc ha cc hm logic trn cc IC kh trnh dng PROM, PAL, PLA, GAL. 12. Khi nim thit k ASIC, cc dng thit k ASIC. 13. Khi nim FPGA, c im FPGA.
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Chng 2 NGN NG M T PHN CNG VHDLChng 2 tp trung vo gii thiu v ngn ng m t phn cng VHDL, y l mt ngn ng m t phn cng c tnh ng dng cao nhng cng c c php khng quen thuc v d tip cn. Ni dung kin thc trnh by trong chng ny theo nh hng nh mt ti liu tra cu hn l bi ging. Ngi hc khng nht thit phi theo ng trnh t kin thc trnh by m c th tham kho tt c cc mc mt cch c lp, bn cnh l tra cu bng cc ti liu khc cng nh ti liu gc bng ting Anh. Cc v d c trong gio trnh u c gng trnh by l cc v d y c th bin dch v m phng c ngay v vy khuyn khch ngi hc tch cc thc hnh song song vi nghin cu l thuyt. Kt thc ni dung ca chng ny yu cu ngi hc phi c k nng s dng VHDL cp c bn, c kh nng thit k cc khi s va v nh nh Flip-flop, khi chn knh, phn knh, khi cng, dch, cc khi gii m bit trong chng trnh in t s, cng l cc khi nn tng cho cc thit k ln hn v phc tp hn chng tip theo.
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1. Gii thiu v VHDLVHDL vit tt ca VHSIC HDL (Very-high-speed-intergrated-circuit Hardware Description Language) hay ngn ng m t phn cng cho cc vi s mch tch hp tc cao. Lch s pht trin ca VHDL tri qua cc mc chnh nh sau: 1981: Pht trin bi B Quc phng M nhm to ra mt cng c thit k phn cng tin dng c kh nng c lp vi cng ngh v gim thiu thi gian cng nh chi ph cho thit k 1983-1985: c pht trin thnh mt ngn ng chnh thng bi 3 cng ty Intermetrics, IBM and TI. 1986: Chuyn giao ton b bn quyn cho Vin K thut in v in t (IEEE). 1987: Cng b thnh mt chun ngn ng IEEE-1076 1987. 1994: Cng b chun VHDL IEEE-1076 1993. 2000: Cng b chun VHDL IEEE-1076 2000. 2002: Cng b chun VHDL IEEE-1076 2002 2007: cng b chun ngn ng Giao din ng dng theo th tc VHDL IEEE-1076c 2007 2009: Cng b chun VHDL IEEE-1076 2009 VHDL ra i trn yu cu ca bi ton thit k phn cng lc by gi, nh s dng ngn ng ny m thi gian thit k ca sn phm bn dn gim i ng k, ng thi vi gim thiu chi ph cho qu trnh ny do c tnh c lp vi cng ngh, vi cc cng c m phng v kh nng ti s dng cc khi n l. Cc u im chnh ca VHDL c th lit k ra l: Tnh cng cng: VHDL l ngn ng c chun ha chnh thc ca IEEE do c s h tr ca nhiu nh sn xut thit b cng nh nhiu nh cung cp cng c thit k m phng h thng, hu nh tt c cc cng c thit k ca cc hng phn mm ln nh u h tr bin dch VHDL. c h tr bi nhiu cng ngh: VHDL c th s dng m t nhiu loi vi mch khc nhau trn nhng cng ngh khc nhau t cc th vin ri rc, CPLD, FPGA, ti th vin cng chun cho thit k ASIC. Tnh c lp vi cng ngh: VHDL hon ton c lp vi cng ngh ch to phn cng. Mt m t h thng chc nng dng VHDL thit k mc thanh ghi truyn ti RTL c th c tng hp thnh cc mch trn cc cng ngh bn dn khc nhau. Ni mt cch khc khi mt cng ngh phn cng mi ra i n 42
c th c p dng ngay cho cc h thng thit k bng cch tng hp cc thit k li trn th vin phn cng mi. Kh nng m t m rng: VHDL cho php m t hot ng ca phn cng t mc thanh ghi truyn ti (RTLRegister Tranfer Level) cho n mc cng (Netlist). Hiu mt cch khc VHDL c mt cu trc m t phn cng cht ch c th s dng lp m t chc nng cng nh m t cng trn mt th vin cng ngh c th no . Kh nng trao i, ti s dng: Vic VHDL c chun ha gip cho vic trao i cc thit k gia cc nh thit k c lp tr nn ht sc d dng. Bn thit k VHDL c m phng v kim tra c th c ti s dng trong cc thit k khc m khng phi lp li cc qu trnh trn. Ging nh phn mm th cc m t HDL cng c mt cng ng m ngun m cung cp, trao i min ph cc thit k chun c th ng dng nhiu h thng khc nhau.
2. Cu trc ca chng trnh m t bng VHDLCu trc tng th ca mt khi thit k VHDL gm ba phn, phn khai bo th vin, phn m t thc th v phn m t kin trc.
Khai bo th vin LIBRARY declaration
M t thc th ENTITY Declaration
M t kin trc ARCHITECTURE Hnh vi Behavioral Lung d liu DataFlow Cu trc Structure
Hnh 2-1. Cu trc ca mt thit k VHDL
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2.1. Khai bo th vin Khai bo th vin phi c t u tin trong mi thit k VHDL, lu rng nu ta s dng mt tp m ngun cha nhiu khi thit k khc nhau th mi mt khi u phi yu cu c khai bo th vin u tin, nu khng khi bin dch s pht sinh ra li. V d v khai bo th vinlibrary IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
Khai bo th vin bt u bng t kha Library Tn th vin (ch l VHDL khng phn bit ch hoa ch thng). Sau trn tng dng k tip s khai bo cc gi th vin con m thit k s s dng, mi dng phi kt thc bng du ;. Tng t nh i vi cc ngn ng lp trnh khc, ngi thit k c th khai bo s dng cc th vin chun hoc th vin ngi dng.Th vin IEEE gm nhiu gi th vin con khc nhau trong ng ch c cc th vin sau: - Gi IEEE.STD_LOGIC_1164 cung cp cc kiu d liu std_ulogic, std_logic, std_ulogic_vector, std_logic_vector, cc hm logic and, or, not, nor, xor cc hm chuyn i gia cc kiu d liu trn. std_logic, std_ulogic h tr kiu logic vi 9 mc gi tr logic (xem 4.2) - Gi IEEE.STD_LOGIC_ARITH nh ngha cc kiu d liu s nguyn SIGNED, UNSIGNED, INTEGER, SMALL INT cung cp cc hm s hc bao gm +, -, *, /, so snh , =, cc hm dch tri, dch phi, cc hm chuyn i t kiu vector sang cc kiu s nguyn. - Gi IEEE.STD_LOGIC_UNSIGNED Cung cp cc hm s hc logic lm vic vi cc kiu d liu std_logic, integer v tr v gi tr dng std_logic vi gi tr khng c du - Gi IEEE.STD_LOGIC_SIGNED Cung cp cc hm s hc logic lm vic vi cc kiu d liu std_logic, integer v tr v gi tr dng std_logic vi gi tr c du - Gi IEEE.NUMERIC_BIT Cung cp cc hm s hc logic lm vic vi cc kiu d liu signed, unsigned c l chui ca cc BIT. - Gi IEEE.NUMERIC_BIT Cung cp cc hm s hc logic lm vic vi cc kiu d liu signed, unsigned c l chui ca cc STD_LOGIC. 44
Gi IEEE.STD_LOGIC_TEXTIO cha cc hm, th tc vo ra READ/WRITE c ghi d liu cho cc nh dng STD_LOGIC, STD_ULOGIC t FILE, STD_INPUT, STD_OUTPUT, LINE. - Gi STD.TEXTIO cha cc hm vo ra READ/WRITE c ghi d liu vi cc nh dng khc nhau gm, BIT, INTEGER, TIME, REAL, CHARATER, STRING t FILE, STD_INPUT, STD_OUTPUT, LINE. - Gi IEEE.MATH_REAL, IEEE.MATH_COMPLEX cung cp cc hm lm vic vi s thc v s phc nh SIN, COS, SQRT hm lm trn, CIEL, FLOOR, hm to s ngu nhin SRAND, UNIFORM v nhiu cc hm tnh ton s thc khc. - Gi STD.ENV cung cp cc hm, th tc h thng phc v m phng gm stop dng m phng, finish thot chng trnh, resolution_limit tr v bc thi gian m phng. C th v chi tit hn v cc th vin chun ca IEEE c th tham kho thm trong ti liu ca IEEE (VHDL Standard Language reference), v xem thm phn Ph lc 1 cui sch lit k v phn loi y cc hm ca cc th vin chun.-
2.2. M t thc th Khai bo thc th (entity) l khai bo v mt cu trc cc cng vo ra (port), cc tham s tnh dng chung (generic) ca mt khi thit k VHDL.entity identifier is generic (generic_variable_declarations); port (input_and_output_variable_declarations); end entity identifier ;
Trong identifier l tn ca khi thit k.
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khai bo generic l khai bo cc tham s tnh ca thc th, khai bo ny rt hay s dng cho nhng thit k c nhng tham s thay i nh rng knh, kch thc nh, tham s b m v d chng ta c th thit k b cng cho cc hng t c di bit thay i, s bit c th hin l hng s trong khai bo generic (xem v d di y) Khai bo cng vo ra: lit k tt c cc cng giao tip ca khi thit k, cc cng c th hiu l cc knh d liu ng ca thit k phn bit vi cc tham s tnh trong khai bo generic. kiu ca cc cng c th l: - in: cng vo, 45
out: cng ra, inout vo ra hai chiu. buffer: cng m c th s dng nh tn hiu bn trong v output. linkage: C th lm bt k cc cng no k trn. V d cho khai bo thc th nh sau:entity adder is generic ( N : port ( A : B : cin : Sum : Cout : end entity adder ; natural := 32); in bit_vector(N-1 downto 0); in bit_vector(N-1 downto 0); in bit; out bit_vector(N-1 downto 0); out bit);
on m trn khai bo mt thc th cho khi cng hai s, trong khai bo trn N l tham s tnh generic ch di bit ca cc hng t, gi tr ngm nh N = 32, vic khai bo gi tr ngm nh l khng bt buc. Khi khi ny c s dng trong khi khc nh mt khi con khc th c th thay i gi tr ca N thu c thit k theo mong mun. V cc cng vo ra, khi cng hai s nguyn c 3 cng vo A, B N-bit l cc hng t v cng cin l bt nh t bn ngoi. Hai cng ra l Sum N-bit l tng v bt nh ra Cout. Khai bo thc th c th cha ch mnh khai bo cng nh sau:entity full_adder is port ( X, Y, Cin : in bit; Cout, Sum : out bit ); end full_adder ;
Khai bo thc th khng cha c khai bo generic ln khai bo port vn c xem l hp l, v d nhng khai bo thc th s dng m phng kim tra thit k thng c khai bo nh sau:entity TestBench is end TestBench;
V d v cng dng buffer v inout: Cng buffer c dng khi tn hiu c s dng nh u ra ng thi nh mt tn hiu bn trong ca kh thit k, in hnh nh trong cc mch dy lm vic ng b. Xt v d sau v b cng tch ly 4-bit n gin sau (accumulator):library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.STD_LOGIC_arith.ALL;
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----------------------------------------entity accumulator is port( data : in std_logic_vector(3 downto 0); nRST : in std_logic; CLK : in std_logic; acc : buffer std_logic_vector(3 downto 0) ); end accumulator; ----------------------------------------architecture behavioral of accumulator is begin ac : process (CLK) begin if CLK = '1' and CLK'event then if nRST = '1' then acc C(0), S =>Sum(1), Cout => C(1)); u2: full_adder port map (A => A(2), B => B(2),
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Cin => C(1), S =>Sum(2), Cout => C(2)); u3: full_adder port map (A => A(3), B => B(3), Cin => C(2), S =>Sum(3), Cout => CO); end structure; -----------------------------------------
v d trn mt b cng 4 bit c xy dng t 4 khi full_adder nhng vi cc kin trc khc nhau. Khi u tin dng kin trc hnh vi (behavioral), khi th hai l kin trc kiu lung d liu (dataflow), khi th 3 l kin trc kiu cu trc (structure), v khi cui cng l kin trc kiu hnh vi.
3. Chng trnh con v gi3.1. Th tc Chng trnh con (subprogram) l cc on m dng m t mt thut ton, php ton dng x l, bin i, hay tnh ton d liu. C hai dng chng trnh con l th tc (procedure) v hm (function). Th tc thng dng thc hin mt tc v nh bin i, x l hay kim tra d liu, hoc cc tc v h thng nh c ghi file, truy xut kt qu ra mn hnh, kt thc m phng, theo di gi tr tn hiu. Khai bo ca th tc nh sau:procedure identifier [(formal parameter list)] is [declarations] begin sequential statement(s) end procedure identifier;
v d:procedure print_header ; procedure build ( A : in constant integer; B : inout signal bit_vector; C : out variable real; D : file);
Trong formal parameter list cha danh sch cc bin, tn hiu, hng s, hay d liu kiu FILE, kiu ngm nh l bin. Cc i tng trong danh sch ny tr dng file c th c khai bo l dng vo (in), ra (out), hay hai chiu (inout), kiu ngm nh l in. Xt vi d y di y:----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use STD.TEXTIO.all; -----------------------------------------
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entity compare is port( res1, res2 : in bit_vector(3 downto 0) ); end compare; ----------------------------------------architecture behavioral of compare is procedure print_to_file( val1, val2 : in bit_vector(3 downto 0); FILE fout : text) is use STD.TEXTIO.all; variable str: line; begin WRITE (str, string'("val1 = ")); WRITE (str, val1); WRITE (str, string'(" val2 = ")); WRITE (str, val2); if val1 = val2 then WRITE (str, string'(" OK")); elsif WRITE (str, string'(" TEST FAILED")); end if; WRITELINE(fout, str); WRITELINE(output, str); end procedure print_to_file; FILE file_output : text open WRITE_MODE is "test_log.txt"; -- start here begin proc_compare: print_to_file(res1, res2, file_output); end behavioral; -------------------------------------------
Trong v d trn chng trnh con dng so snh v ghi kt qu so snh ca hai gi tr kt qu res1, res2 vo trong file vn bn c tn "test_log.txt". Phn khai bo ca hm c t trong phn khai bo ca kin trc nhng nu hm c gi trc tip trong kin trc nh trn th khai bo ny c th b i. Thn chng trnh con c vit trc tip trong phn khai bo ca kin trc v c gi trc tip cp begin end behavioral.
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3.2. Hm Hm (function) thng dng tnh ton kt qu cho mt t hp u vo. Khai bo ca hm c c php nh sau:function identifier [parameter list] return a_type;
v dfunction random return float; function is_even ( A : integer) return boolean;
Danh sch bin ca hm cng c cch nhau bi du ; nhng im khc l trong danh sch ny khng c ch r dng vo/ra ca bin m ngm nh tt c l u vo. Kiu d liu u ra ca hm c quy nh sau t kha return. Cch thc s dng hm cng tng t nh trong cc ngn ng lp trnh bc cao khc. Xt mt v d y di y:library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------entity function_example is end function_example; ----------------------------------------architecture behavioral of function_example is type bv4 is array (3 downto 0) of std_logic; function mask(mask, val1 : in bv4) return bv4; signal vector1 : bv4 := "0011"; signal mask1 : bv4 := "0111"; signal vector2 : bv4; function mask(mask, val1 : in bv4) return bv4 is variable temp : bv4; begin temp(0) := mask(0) and val1(0); temp(1) := mask(1) and val1(1); temp(2) := mask(2) or val1(2); temp(3) := mask(3) or val1(3); return temp; end function mask; -- start here begin masking: vector2 sum_t, CO => co_t); etalon: adder4_etalon port map (A => a_t, B => b_t, CI => ci_t, SUM =>sum_e, CO => co_e); END testbenchfull; -----------------------------------------
Khi kim tra ci t ng thi cc khi con l adder4_gen (DUT) v adder4_etalon (ETALON), cc khi ny c cc u vo d liu y ht nh nhau ly t cc tn hiu tng ng l a_t, b_t, ci_t. Cc u ra ca hai khi ny tng ng l sum_t, co_t cho DUT v sum_e, co_e cho ETALON. Khi kim tra t ng ny thc cht lp li chc nng ca khi kim tra nhanh nhiu ln vi nhiu t hp u vo, mt khc s dng kt qu tnh ton t khi thit k chun ETALON kim tra t ng tnh ng n ca kt qu u ra t khi DUT cn kim tra. lm c vic , mt xung nhp clk c to ra, chu k ca xung nhp ny c th nhn gi tr bt k, v d on m trn ta to xung nhp clk c chu k T = 2 x 50 ns = 100 ns. C xung nhp ny ta s to mt b m theo xung m l clk m s lng test, khi m 512 test th s thng bo ra mn hnh vic thc hin test xong. Ti mi thi im sn dng ca clk gi tr m ny tng thm 1 ng thi ti thi im t hp gi tr u vo thay i tun t qut ht 512 t hp gi tr khc nhau. u tin cc gi tr a_t, b_t, ci_t nhn gi tr khi to l 0, 0, 0. Ti cc sn dng ca xung nhp thay i gi tr ci_t trc, nu ci_t = 1 th tng a_t thm 1 n v, sau kim tra nu a_t = 1111 th s tng b_t thm 1 n v.
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Cc u ra sum_t, sum_e, co_t, co_e s c so snh vi nhau sau mi xung nhp, nu nh sum_t = sum_e v co_t = co_t th kt lun l adder4_gen lm vic ng (TEST OK) v ngc li l lm vic sai (TEST FAILURE) V s lng t hp u vo l ln nn khng th quan st bng waveform na, kt qu khi c thng bo trc tip ra mn hnh. Khi chy m phng ta thu c thng bo nh sau:#Test#1a = 0b = 0 CI = 0 sum = 0 CO = 0sum_e = 0CO_e = 0 OK #Test#2a = 0b = 0 CI = 1 sum = 1 CO = 0sum_e = 1CO_e = 0 OK #Test#3a = 1b = 0 CI = 0 sum = 1 CO = 0sum_e = 1CO_e = 0 OK #Test#4a = 1b = 0 CI = 1 sum = 2 CO = 0sum_e = 2CO_e = 0 OK #Test#5a = 2b = 0 CI = 0 sum = 2 CO = 0sum_e = 2CO_e = 0 OK #Test#6a = 2b = 0 CI = 1 sum = 3 CO = 0sum_e = 3CO_e = 0 OK #Test#7a = 3b = 0 CI = 0 sum = 3 CO = 0sum_e = 3CO_e = 0 OK #Test#8a = 3b = 0 CI = 1 sum = 4 CO = 0sum_e = 4CO_e = 0 OK #Test#9a = 4 b = 0 CI = 0 sum = 4 CO = 0sum_e= 4CO_e = 0 OK #Test#10a =4 b = 0 CI = 1sum = 5 CO = 0sum_e = 5CO_e = 0 OK #Test#11a =5 b = 0 CI = 0sum = 5 CO = 0sum_e = 5CO_e = 0 OK #Test#511a =15b = 14CI = 0sum =13CO = 1sum_e =13CO_e= 1OK #Test#512a =15b = 15CI = 1sum= 15CO = 1sum_e =15CO_e = 1 OK # ** Note: end simulation # Time: 61385 ns Iteration: 0 Instance: /adder4_testbench
Nu nh tt c cc trng hp u thng bo l OK th c th kt lun DUT lm vic ng, qu trnh kim tra hon tt. Lu rng khi thc hin kim tra t ng th ETALON khng phi lc no cng c chnh xc 100% nh trn v i khi rt kh vit c khi ny ny. Khi ta phi c phng n kim tra khc. im lu th hai l trn thc t vic kim tra vi mi t hp u vo (full_testbench) thng l khng th v s lng cc t hp ny trong a s cc trng hp rt ln v d nh nu khng phi b cng 4 bit m l b cng 32 bit th s lng t hp u vo l 232x2+1 = 265 l mt con s qu ln kim tra ht d bng cc my tnh nhanh nht. Khi qu trnh kim tra chia thnh hai bc: Bc 1 s tin hnh kim tra bt buc vi cc t hp c tnh cht ring nh bng 0 hay bng s ln nht, hoc cc t hp gy ra cc ngoi l, cc t hp gy pht sinh li. Nu kim tra vi cc t hp ny khng c li s chuyn sang bc th hai l RANDOM_TEST. B phn kim tra s cho chy RANDOM_TEST vi s lng u vo khng gii hn. Nu trong qu trnh ny pht hin ra li th t hp 109
gi tr gy ra li s c b xung vo danh sch cc t hp bt buc phi kim tra bc 1 v lm li cc bc kim tra t u sau khi sa li. Kim tra c coi l thc hin xong nu nh vi mt s lng rt ln RANDOM_TEST m khng tm thy li.
110
Bi tp chng 2 Bi tp1. Thit k full_adder trn VHDL, trn c s thit k b cng 4 bit tng t IC 7483.A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3
7483
Cin
Cout
2.
Thit k b gii m nh phn 2_to_4 c u ra thun, nghch tng t IC 74LS13974LS139Ya0 Aa Ba Ea Ya1 Ya2 Ya3
Ab Bb Eb
Yb0 Yb1 Yb2 Yb3
.
3.
Thit k b gii m nh phn 3_to_8 c u ra thun, nghch tng t IC 74LS138.Y0 A B C E E1 E2 Y1 Y2 Y3 Y4 Y5 Y6 Y7
74LS138
4.
Thit b chn knh 4 u vo 1 u ra MUX4_1 tng t IC 74153 nhng ch h tr mt knh chn (IC ny c hai knh chn ring bit nh hnh v)
111
I0a I1a Ya I2a I3a Ea
74LS153
I0b I1b I2b I3b Eb S0 S1 Yb
5. 6. 7.
Thit b phn knh 1 u vo 4 u ra DEMUX1_4. Thit k b cng/ tr 4 bit s dng ton t cng trn VHDL. Thit k b so snh hai s khng du 4 bit tng t IC 7485.A0 A1 A2 A3 B0 B1 B2 B3
7485
A>B A=B AB A=B A dataout dataout null; end case; end if; end process get_data; end behavioral; ----------------------------------------B cng n gin ch c cng a, b v sum adder.vhd: ----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------entity adder is generic (N : natural := 32); port( A : in std_logic_vector(N-1 downto 0); B : in std_logic_vector(N-1 downto 0); SUM : out std_logic_vector(N-1 downto 0) ); end adder; ----------------------------------------architecture behavioral of adder is276begin plus: process (A, B) begin sum clk1Mhz, rst => reset, din => data_in2, wr_en => wr_en2, rd_en => rd_en, dout => data_out, full => full, empty => empty); -- INST_TAG_END -- End INSTANTIATION Template ----counter: process (clk1Mhz, reset) begin if cnt_reset = '1' then cnt '0'); elsif clk1Mhz = '1' and clk1Mhz'event then if cnt_enable = '1' then cnt hcount, vcount => vcount, RED => RED, BLUE => BLUE, GREEN => GREEN); end Structural;Thit lp ci t cho u vo u ra ca thit k nh sau: (vgacomp.ucf). Thit lp ny c th khc nhau cho cc mch thc t khc nhau:NET "BLUE" LOC = P83; NET "GREEN" LOC = P89; NET "RED" LOC = P90; NET "RST" LOC = P29; NET "CLK_25MHz" LOC = P184; NET "HS" LOC = P78; NET "VS" LOC = P82; NET "CLK_25MHz" TNM_NET = "CLK_25MHz"; TIMESPEC TS_CLK_25MHz = PERIOD "CLK_25MHz" 35 ns HIGH 50 %; NET "BLUE" SLEW = FAST; NET "CLK_25MHz" SLEW = FAST; NET "GREEN" SLEW = FAST; NET "HS" SLEW = FAST;305NET "RED" SLEW = FAST; NET "VS" SLEW = FAST; OFFSET = OUT 35 ns AFTER "CLK_25MHz"; OFFSET = IN 35 ns VALID 35 ns BEFORE "CLK_25MHz" RISING;V d trn minh ha cho qu trnh iu khin VGA bng thit k VHDL, ngi hc c th trn c s thit k cc khi iu khin VGA hon chnh c kh nng hin th k t vn bn, i tng ha theo yu cu. Kt qu tng hp cho thy khi thit k chim mt lng ti nguyn Logic rt nh v c th hot ng vi tc ln ti c 200Mhz ngha l c th p ng c nhng mn hnh c phn gii ln v tc qut cao.Device utilization summary: --------------------------Selected Device : 3s500epq208-5 Number of Slices: 28 out of 4656 0% Number of Slice Flip Flops: 26 out of 9312 0% Number of 4 input LUTs: 49 out of 9312 0% Number of IOs: 7 Number of bonded IOBs: 7 out of 158 4% Number of GCLKs: 1 out of 24 4% Number of DCMs: 1 out of 4 25% ================================================== TIMING REPORT Clock Information: Clock Signal | Clock buffer(FF name) | Load | -------------+--------------------------+-------+ CLK | dcm_gen/DCM_SP_inst:CLKFX| 26 | -------------+--------------------------+-------+ Timing Summary: --------------Speed Grade: -5 Minimum period: 4.770ns (Maximum Frequency: 209.651MHz) Minimum input arrival time before clock: 3.838ns Maximum output required time after clock: 4.040ns Maximum combinational path delay: No path foundKt qu v mt thi gian tnh ca mch VGA sau khi kt ni v sp t nh sau:Data Sheet report: ----------------All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk -------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall|306Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| -------------+---------+---------+---------+---------+ clk | 3.744| | | | -------------+---------+---------+---------+---------+Vi m ngun trn quan st trn thc t s thu c hnh nh c dng sau sau trn mn hnh:Hnh 4.77. Kt qu trn mch FPGA ca khi iu khin VGA307Bi tp chng 41. Bi tp c s 1. Thit k, tng hp cc cng logic c bn trn FPGA kim tra trn mch th nghim. 2. Thit k, tng hp cc flip-flop D, JK, T, RS trn FPGA. Kim tra hot ng trn mch th nghim. 3. Tng hp cc khi m chia tn s t tn s ca b to dao ng ra tn s 1HZ, quan st kt qu bng Led Diod. 4. Thit k khi m nh phn 4 bit, tng hp v hin th trn Led 7 on. 5. Thit k, tng hp ng h s trn FPGA hin th gi ph thng qua 4 k t s ca led 7 on. S dng phm n t li gi pht, giy. 6. Thit k, tng hp b cng NBCD cho 2 s c 1 ch s trn FPGA hin th u vo v u ra trn led 7 on, trong u vo c ly t switch. 7. Thit k, tng hp b tr NBCD 1 s c 2 s cho 1 s c 1 ch s trn FPGA hin th kt qu v u ra trn led 7 on, trong u vo c ly t cc switch. 8. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc khi dch theo cc cch khc nhau: s dng ton t, khng dng ton t trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 9. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b cng theo cc cch khc nhau: s dng ton t, ni tip, ni tip bit, thy nh trc trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 10. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b nhn s nguyn khng du theo cc cch khc nhau: s dng ton t, cng dch tri, cng dch phi trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 11. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b nhn s nguyn khng du dng thut ton: s dng ton t, Booth2, Booth4 trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 12. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b chia s nguyn khng du theo cc cch khc nhau: s dng ton t, Booth2, Booth4 trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. 30813.14.15.16.17.18.S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp cc b chia s nguyn c du theo cc cch khc nhau: s dng ton t, Booth2, Booth4 trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp khi cng s thc du phy ng theo s thut ton chng III v theo cch s dng IP Core FPU trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp khi nhn s thc du phy ng theo s thut ton chng III v theo cch s dng IP Core FPU trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. S dng cc giao tip c bn (Switch, Led, 7-Seg) tng hp khi chia s thc du phy ng theo s thut ton chng III v theo cch s dng IP Core FPU trn FPGA. So snh kt qu thu c v mt ti nguyn v v mt din tch. Thit k tng hp khi FIFO trn FPGA bng cch s dng thut ton khi FIFO chng III v dng IP Core c sn, so snh kt qu tng hp theo tng cch. Xy dng khi nhn s dng Dedicated Multiplier, so snh kt qu tng hp vi cc b nhn s nguyn lm cc bi chng III. 2. Bi tp nng cao1. Thit k khi truyn nhn thng tin d b ni tip (UART) hin thc ha trn FPGA thc hin truyn v nhn k t chun thng qua Hyper Terminal. 2. Thit k khi truyn nhn thng tin qua chun I2C, hin thc ha v kim tra trn FPGA vi IC AD/DA PCF8591. 3. Thit k khi truyn nhn thng tin qua giao thc chun SPI bng VHDL, hin thc ho v kim tra trn FPGA. 4. Thit k hon chnh khi truyn nhn chun PS/2 giao tip vi bn phm chun. 5. Thit k hon chnh khi truyn nhn chun PS/2 giao tip vi chut my tnh. 6. Thit k hon chnh khi giao tip vi mn hnh LCD 1602A cc ch lm vic 4 bit v 8 bit. 3097. Thit k khi nhp liu t bn phm chun PS/2, d liu nhp vo c hin th ln mn hnh LCD1602A. 8. Thit k khi nhp liu t bn phm chun PS/2, d liu nhp vo c truyn thng qua cng giao tip RS232. 9. B tng hp tn s NCO, xut ra dng sng hnh sin vi tn s c th thay i c. 10. B iu ch, thu v bin i tn hiu AM n gin s dng khi NCO kt hp vi bin iu bin U0theo quy lut c gii tn thp hn nhiu so vi gii tn ca sng iu ch theo hnh v sau:11. Thit k khi kt xut tn hiu iu ch xung di rng PWM (pulse wide modulation) nh hnh v saut1 t2 t3 t4PWMT0T0T0T0Tn hiu u ra l tn hiu xung vung c chu k khng i l T0 nhng c rng xung (mc 1) thay i theo thi gian t1, t2, t3, t4theo mt quy lut ty (ph thuc thng tin iu ch). 12. Thit k khi kt xut tn hiu iu ch xung di rng PPM (pulse phase modulation) nh hnh v saut1 PPM Tt2 Tt3 Tt3310Tn hiu u ra l tn hiu xung vung c c rng xung (mc 1) khng i T nhng c lch pha so vi xung chun ln lt cc gi tr t1, t2, t3, t4theo mt quy lut ty (ph thuc thng tin iu ch). Quan st kt qu trn Osiloscope. 13. Thit k v kim tra khi m thi gian v nh thi vi xung vo chun 1Mhz (chia t DCM) c chc nng lm vic tng t nh Timer0 v Timer1 trong vi iu khin 89c51. Cu to ca b m/nh thi gm c thanh ghi cu hnh TCON, hai thanh ghi m THLx, THx (vi x = 0, 1) Timers c th hot ng ch 8 bit t ng khi to li hoc ch 16-bit. Cc Timers phi sinh ra tn hiu bo ngt mi khi m xong. Chi tit xem thm trong ti liu hng dn ca 89c51 14. Thit k v kim tra khi m thi gian v nh thi vi xung vo chun 1Mhz (chia t DCM) c chc nng lm vic tng t nh Timer2 trong vi iu khin 89c52, ngoi nhng chc nng nh Timer1 v timer 2 cn c h tr cng vo ra tc cao. Chi tit xem thm trong ti liu hng dn ca 89C52. 15. Nghin cu xy dng khi m ha theo thut ton AES, m t bng VHDL, tng hp v hin thc ha trn FPGA. Xem thm trong ti liu [36]. 16. Nghin cu xy dng khi m ha theo thut ton DES, m t bng VHDL v hin thc ha trn FPGA. Xem thm trong ti liu gii thiu trong [37] 17. Nghin cu xy dng khi m ha theo thut ton RSA-128bit vi yu cu tnh c bn l thc hin php ton tnh module ca ly tha AB theo s N, Chi tit v RSA xem trong ti liu [38]. Trong thit k s dng khi nhn MontGomery phn bi tp chng III. Hin thc ha, kim tra trn FPGA. 18. Nghin cu thut ton CORDIC (Coordinate Rotation Digital Computer) ng dng tnh ton cc hm SIN, COSIN. Xem thm ti liu gii thiu trong [35]. 19. Nghin cu thut ton CORDIC (Coordinate Rotation Digital Computer) ng dng tnh ton cc hm ARCTAN. Xem thm ti liu gii thiu trong [35]. 20. Nghin cu xy dng s hin thc ha cho bin i Fourier DFT (Discret Fourier Transform ) v s hin thc ha trn FPGA vi N= 4, 8, 16. 21. Nghin cu xy dng s hin thc ha thit k bin i Fourier nhanh cho dy gi tr ri rc FFT (Fast Fourier Transform) cho N = 16 v phn chia theo c s 2, c s 4 theo thi gian. 22. Thit k mch lc s theo s di y:311 s trn k hiu Z tng ng l cc Flip-flop gi chm, k hiu tam gic l cc khi nhn, k hiu sig-ma l cc khi cng, ton b khi hot ng ng b. bi l cc hng s ca b lc, x[n], y[n] l chui tn hiu ri rc vo v ra t b lc. 23. Hin thc giao thc VGA trn mch FPGA c kh nng truy xut hnh nh v vn bn. Trong thit k s dng cc khi c bn trnh by trong mc 4.5 v b xung y khi ROM cho k t v khi RAM lu nh i tng hin th. 3. Cu hi n tp l thuyt 1. nh ngha FPGA, u im ca FPGA vi cc chip kh trnh khc. 2. Nguyn l lm vic ca FPGA, kh nng ti cu trc, ti nguyn FPGA. 3. Trnh by kin trc tng quan ca FPGA, cc dng ti nguyn ca FPGA. 4. Trnh by kin trc tng quan ca Spartan 3E FPGA, cc ti nguyn ca FPGA ny. 5. Trnh by cu trc chi tit ca CLB, SLICE, LUT. 6. Trnh by cu trc v nguyn l lm vic ca Arithmetic chain, Carry Chain, vai tr ca cc chui ny trong FPGA 7. Trnh by cu trc ca Programable Interconnects trong FPGA 8. Trnh by cu trc ca IOB trong FPGA. 9. Trnh by c im, cu trc v cch s dng ca Distributed RAM v Shift Register trong FPGA. 10. Trnh by c im, cu trc v cch s dng ca Block RAM v Multiplier 18x18 trong Spartan 3E FPGA. 11. Quy trnh thit k trn FPGA. 12. Khi nim tng hp thit k. Cch thit lp cc iu kin rng buc cho thit k. 13. Cc bc hin thc thit k (Translate, Mapping, Place & Routing) 14. Cc dng kim tra thit k trn FPGA 312PH LC313Ph lc 1: THNG K CC HM, TH TC, KIU D LIU CA VHDL TRONG CC TH VIN CHUN IEEE.1. Cc kiu d liu h tr trong cc th vin chun IEEE Tn kiu BIT BITVECTOR STD_ULOGIC STD_LOGIC STD_ULOGIC_VE CTOR STD_LOGIC_VEC TOR X01 X01Z UX01 UX01Z UNSIGNED SIGNED SMALL_INT CONV_INTEGER CONV_INTEGER SIGNED UNSIGNED SIGNED UNSIGNED Gii thch Th vin IEEE.STD_LOGIC_1164 STD_ULOGIC STD_LOGIC_VECTOR 9 mc logic chun gm X, 0, 1, L, H, Z, W, - , U Ging STD_ULOGIC nhng c nh ngha cch thc cc gi tr hp vi nhau Chui STD_ULOGIC Chui STD_LOGIC Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, X) Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, X, Z) Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, U, X) Kiu con ca STD_LOGIC vi ch cc gi tr (0, 1, U, X, Z) Th vin IEEE.STD_LOGIC_ARITH Chui STD_LOGICc xem nh s khng du Chui STD_LOGIC c xem nh s c du Kiu INTEGER vi ch cc gi tr 0, 1 Th vin IEEE.STD_LOGIC_UNSIGNED STD_LOGIC_VECTOR INTEGER Th vin IEEE.STD_LOGIC_SIGNED STD_LOGIC_VECTOR INTEGER Th vin IEEE.NUMERIC_BIT Chui BIT c xem nh s c du Chui BIT c xem nh s khng du Th vin IEEE.NUMERIC_STD Chui STD_LOGICc xem nh s c du Chui STD_LOGIC c xem nh s khng du 3142. Cc hm thng dng h tr trong cc th vin chun IEEE Tn hm (i bin) Gi tr tr v Ghi chTh vin IEEE.STD_LOGIC_1164 AND( l : std_ulogic; r : std_ulogic ) UX01 NAND( l : std_ulogic; r : std_ulogic ) UX01 OR( l : std_ulogic; r : std_ulogic ) UX01 NOR( l : std_ulogic; r : std_ulogic ) UX01 XOR( l : std_ulogic; r : std_ulogic ) UX01 XNOR( l : std_ulogic; r : std_ulogic ) UX01 NOT( l : std_ulogic; r : std_ulogic ) UX01 AND( l, r : std_logic_vector ) std_logic_vector NAND( l, r : std_logic_vector) std_logic_vector OR( l, r : std_logic_vector) std_logic_vector NOR( l, r : std_logic_vector ) std_logic_vector XOR( l, r : std_logic_vector) std_logic_vector XNOR( l, r : std_logic_vector) std_logic_vector NOT(( l, r : std_ulogic_vector) std_logic_vector AND( l, r : std_ulogic_vector ) std_ulogic_vector NAND( l, r : std_ulogic_vector) std_ulogic_vector OR( l, r : std_ulogic_vector) std_ulogic_vector NOR( l, r : std_ulogic_vector ) std_ulogic_vector XOR( l, r : std_ulogic_vector) std_ulogic_vector XNOR( l, r : std_ulogic_vector) std_ulogic_vector NOT(( l, r : std_ulogic_vector) std_ulogic_vector rising_edge (SIGNAL s : std_ulogic) BOOLEAN falling_edge (SIGNAL s : std_ulogic) BOOLEAN Is_X ( s : std_ulogic_vector) BOOLEAN Is_X ( s : std_ulogic_vector) BOOLEAN Is_X ( s : std_ulogic) BOOLEAN Th vin IEEE.STD_LOGIC_ARITH 315+, - (L, R: SIGNED, SIGNED) +, - (L, R: UNSIGNED, UNSIGNED) +, - (L, R: UNSIGNED, SIGNED) +, - (L: SIGNED, R: INTEGER) +, - (L: UNSIGNED, R: INTEGER) +, - (L: STD_ULOGIC, R: SIGNED) +, - (L : STD_ULOGIC, R: UNSIGNED) +, - (L: SIGNED, R: UNSIGNED) +, - (L: INTEGER, R: SIGNED, UNSIGNED) +, - (L: STD_ULOGIC, R: SIGNED, UNSIGNED) * (L, R: SIGNED, SIGNED) * (L, R: UNSIGNED, UNSIGNED) * (L, R: UNSIGNED, SIGNED) * (L: SIGNED, UNSIGNED, R: SIGNED, UNSIGNED) =, = (L: SIGNED, UNSIGNED, R: SIGNED, UNSIGNED) =, = (L: INTEGER, R: SIGNED, UNSIGNED) SHL(ARG: SIGNED; COUNT: UNSIGNED) SHL(ARG: UNSIGNED; COUNT: UNSIGNED) SHR(ARG: SIGNED; COUNT: UNSIGNED) SHR(ARG: UNSIGNED; COUNT: UNSIGNED)SIGNED UNSIGNED SIGNED SIGNED UNSIGNED SIGNED UNSIGNED STD_LOGIC_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTOR SIGNED UNSIGNED SIGNED STD_LOGIC_VECTOR BOOLEAN BOOLEAN SIGNED UNSIGNED SIGNED UNSIGNEDTh vin IEEE.STD_LOGIC_UNSIGNED +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) +, - (L: STD_LOGIC_VECTOR, R: INTEGER) STD_LOGIC_VECTOR +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC) STD_LOGIC_VECTOR * (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN INTEGER) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN 316STD_LOGIC_VECTOR) SHL(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) SHR(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) Th vin IEEE.STD_LOGIC_SIGNED +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) +, - (L: STD_LOGIC_VECTOR, R: INTEGER) STD_LOGIC_VECTOR +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC) STD_LOGIC_VECTOR * (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN STD_LOGIC_VECTOR) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN INTEGER) SHL(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) SHR(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) Th vin IEEEE.NUMERIC_BIT +, - (L, R: UNSIGNED) UNSIGNED +, - (L, R: SIGNED) SIGNED +, - (L: NATURAL, R: SIGNED) SIGNED +, - (L: NATURAL, R: UNSIGNED) UNSIGNED +, - (L: INTEGER, R: SIGNED) SIGNED *, /, mod, rem (L, R: UNSIGNED) UNSIGNED *, /, mod, rem (L, R: SIGNED) SIGNED *, /, mod, rem (L: NATURAL, R: UNSIGNED) UNSIGNED *, /, mod, rem (L: INTEGER, R: SIGNED) SIGNED =, = (L: UNSIGNED, R: UNSIGNED) BOOLEAN =, = (L: SIGNED, R: SIGNED) BOOLEAN =, = (L: INTEGER, R: SIGNED) BOOLEAN =, = (L: NATURAL, R: UNSIGNED) BOOLEAN 317UNSIGNED sll, sla, srl, sra, ror, rol INTEGER UNSIGNED SIGNED sll, sla, srl, sra, ror, rol INTEGER SIGNED SHIFT_LEFT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_LEFT(L: SIGNED, R: NATURAL) SIGNED SHIFT_RIGHT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_RIGHT(L: SIGNED, R: NATURAL) SIGNED ROTATE_RIGHT(L: UNSIGNED, R: UNSIGNED NATURAL) ROTATE_RIGHT(L: SIGNED, R: NATURAL) SIGNED RESIZE(L: UNSIGNED, R: NATURAL) UNSIGNED RESIZE(L: SIGNED, R: NATURAL) SIGNED Th vin IEEEE.NUMERIC_STD +, - (L, R: UNSIGNED) UNSIGNED +, - (L, R: SIGNED) SIGNED +, - (L: NATURAL, R: SIGNED) SIGNED +, - (L: NATURAL, R: UNSIGNED) UNSIGNED +, - (L: INTEGER, R: SIGNED) SIGNED *, /, mod, rem (L, R: UNSIGNED) UNSIGNED *, /, mod, rem (L, R: SIGNED) SIGNED *, /, mod, rem (L: NATURAL, R: UNSIGNED) UNSIGNED *, /, mod, rem (L: INTEGER, R: SIGNED) SIGNED =, = (L: UNSIGNED, R: UNSIGNED) BOOLEAN =, = (L: SIGNED, R: SIGNED) BOOLEAN =, = (L: INTEGER, R: SIGNED) BOOLEAN =, = (L: NATURAL, R: UNSIGNED) BOOLEAN UNSIGNED sll, sla, srl, sra, ror, rol INTEGER UNSIGNED SIGNED sll, sla, srl, sra, ror, rol INTEGER SIGNED SHIFT_LEFT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_LEFT(L: SIGNED, R: NATURAL) SIGNED SHIFT_RIGHT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_RIGHT(L: SIGNED, R: NATURAL) SIGNED ROTATE_RIGHT(L: UNSIGNED, R: UNSIGNED NATURAL) ROTATE_RIGHT(L: SIGNED, R: NATURAL) SIGNED 318RESIZE(L: UNSIGNED, R: NATURAL) RESIZE(L: SIGNED, R: NATURAL)UNSIGNED SIGNED3. Cc hm phc v cho qu trnh m phng kim tra thit k Tn hm (i bin) Gi tr tr v Th vin IEEE.STD_LOGIC_TEXTIO READ(l : inout LINE, R: out std_ulogic ) std_ulogic trong R READ(l : inout LINE, R: out std_ulogic, Good: std_ulogic trong R Boolean ) READ(l : inout LINE, R: out std_ulogic_vector ) std_ulogic_vector trong R READ(l : inout LINE, R: out std_ulogic_vector, std_ulogic_vector Good: Boolean) trong R WRITE(l : inout LINE, R: in std_ulogic_vector ) LINE WRITE(l : inout LINE, R: in std_ulogic_vector, LINE Good: Boolean) READ(l : inout LINE, R: out std_logic_vector) std_logic trong R READ(l : inout LINE, R: out std_logic_vector, std_logic trong R Good: Boolean) WRITE(l : inout LINE, R: in std_logic_vector, LINE Good: Boolean) HREAD(l : inout LINE, R: out std_ulogic_vector) std_logic trong R HREAD(l : inout LINE, R: out std_ulogic_vector, std_logic trong R Good: Boolean) HWRITE(l : inout LINE, R: in std_ulogic_vector, LINE Good: Boolean) HREAD(l : inout LINE, R: out std_logic_vector) std_logic trong R HREAD(l : inout LINE, R: out std_logic_vector, std_logic trong R Good: Boolean) HWRITE(l : inout LINE, R: in std_logic_vector, LINE Good: Boolean) OREAD(l : inout LINE, R: out std_ulogic_vector) std_logic trong R OREAD(l : inout LINE, R: out std_ulogic_vector, std_logic trong R Good: Boolean) Ghi ch319OWRITE(l : inout LINE, R: in std_ulogic_vector, Good: Boolean) OREAD(l : inout LINE, R: out std_logic_vector) OREAD(l : inout LINE, R: out std_logic_vector, Good: Boolean) OWRITE(l : inout LINE, R: in std_logic_vector, Good: Boolean) Th vin STD.ENV STOP (STATUS: INTEGER) FINISH (STATUS: INTEGER) RESOLUTION_LIMIT ()LINE std_logic trong R std_logic trong R LINEPROCEDURE UNSIGNED Delay_length (Bc thi gian c s ca qu trnh m phng) Th vin IEEE.STD_TEXTIO READLINE (file f: TEXT; L: out LINE) String trong LINE READ(L:inout LINE; VALUE: out bit; GOOD : BIT trong VALUE out BOOLEAN) READ(L:inout LINE; VALUE: out bit) BIT trong VALUE READ(L:inout LINE; VALUE: out bit_vector; bit_vector trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out bit_vector) bit_vector trong VALUE READ(L:inout LINE; VALUE: out BOOLEAN; BOOLEAN trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out BOOLEAN) BOOLEAN trong VALUE READ(L:inout LINE; VALUE: out Charater; Charater trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out Charater) Charater trong VALUE READ(L:inout LINE; VALUE: out INTEGER; INTEGER trong GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out INTEGER) INTEGER trong 320READ(L:inout LINE; VALUE: out REAL; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out REAL) READ(L:inout LINE; VALUE: out STRING; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out STRING) READ(L:inout LINE; VALUE: out TIME; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out TIME) SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL); OREAD(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN) OREAD(L:inout LINE; VALUE: out bit_vector)VALUE REAL VALUE REAL VALUE STRING VALUE STRING VALUE TIME VALUE TIME VALUE STRING VALUE bit_vector VALUE bit_vector VALUEtrong trong trong trong trong trong trong trong trongHREAD(l : inout LINE, R: out bit_vector) Bit_vector trong R HREAD(l : inout LINE, R: out bit_vector, Good: Bit_vector trong R Boolean) WRITELINE (file f : TEXT; L : inout LINE) Ghi LINE ra file WRITE(L : inout LINE; VALUE : in bit) WRITE(L : inout LINE; VALUE : in bit_vector) WRITE(L : inout LINE; VALUE : in BOOLEAN) WRITE(L : inout LINE; VALUE : in CHARACTER) WRITE(L : inout LINE; VALUE : in INTEGER) WRITE(L : inout LINE; VALUE : in REAL) WRITE(L : inout LINE; VALUE : in TIME) SWRITE(L : inout LINE; VALUE : in STRING) OWRITE(l : inout LINE, R: in BIT_VECTOR) 321HWRITE (l : inout LINE, R: in BIT_VECTOR) 4. Cc hm bin i kiu d liu dng trong VHDL Tn hm (i bin) Gi tr tr v Th vin IEEE.STD_LOGIC_1164 TO_BIT(Arg: STD_ULOGIC) BIT TO_BITVECT