trb - testreadoutboard filetrb - testreadoutboard hades collaboration marcin kajetanowicz krzysztof...
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TRB - TestReadoutBoardTRB - TestReadoutBoard
HADESHADES Collaboration Collaboration
Marcin KajetanowiczMarcin Kajetanowicz
Krzysztof KorcylKrzysztof Korcyl
Marek PalkaMarek Palka
Piotr SalaburaPiotr Salabura
Michael TraxlerMichael Traxler
Radoslaw TrebaczRadoslaw Trebacz
Marek Palka, Radoslaw Trebacz,HADES Collaboration Meeting XVI
Marek Palka, Radoslaw Trebacz,HADES Collaboration Meeting XVI
32-bit100MHz
32-bit40MHz
32-bit40MHz
32-bit40MHz
32-bit40MHz
32-bit40MHz
16-bit40MHz
16-bit40MHz
32-bit40MHz
32-channels 32-channels
32-
cha
nn
els
32-c
ha
nn
els
Marek Palka, Radoslaw Trebacz,HADES Collaboration Meeting XVI
Marek Palka, Radoslaw Trebacz,HADES Collaboration Meeting XVI
Marek Palka, Radoslaw Trebacz,HADES Collaboration Meeting XVI
A wait state is a delay experienced by a processor when accessing external memory
Performance Performance in the HADAQ chainin the HADAQ chain
with no data, only headers and trailers: 19kHzwith no data, only headers and trailers: 19kHz
with 60 hits per event: 5 kHzwith 60 hits per event: 5 kHz
= 1MB/s= 1MB/s
Marek Palka, Radoslaw Trebacz,HADES Collaboration Meeting XVI
Main limitations:
checking the consistency of data slow processor
no DMA
TDC readout prototypeTDC readout prototype
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
TDC
TDC channnel
Uncorrelated generator
➢ Differential non linearityDifferential non linearity: set up: set up Code density test: Code density test:
Deliver to the TDC a large number of hits about 5M - to Deliver to the TDC a large number of hits about 5M - to get significant statistics from some uncorrelated source. get significant statistics from some uncorrelated source. If we then histogram recorded times ( 8 LSB bits) we If we then histogram recorded times ( 8 LSB bits) we should see equal contents - it would be for an ideal should see equal contents - it would be for an ideal TDC.TDC.
TDC readout prototypeTDC readout prototype Differential non linearity:Differential non linearity:
The differential non linearity represents difference between the actual The differential non linearity represents difference between the actual histogram bin contents of the two adjacent bins. This difference is histogram bin contents of the two adjacent bins. This difference is normalized to the expected contents of a bin (to express non linearity as normalized to the expected contents of a bin (to express non linearity as a fraction of the LSB). a fraction of the LSB).
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
TDC readout prototypeTDC readout prototype
Crosstalk: setupCrosstalk: setup The crosstalk is then ifThe crosstalk is then if unwanted interference from unwanted interference from
another adjacent communications channel appears. In another adjacent communications channel appears. In our case this communication channels are involved with our case this communication channels are involved with time channels -precisely time difference between two time channels -precisely time difference between two channels. channels.
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
TDC
TDC n-1 channnel
TDC n channnelTDC n+1 channnel
A
BC
TDC readout prototypeTDC readout prototype CrosstalkCrosstalk
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
Programming TDC:Programming TDC: Three steps:Three steps:
Fill input file (human readable) Fill input file (human readable) with correct values,with correct values,
Make file understood for TDC Make file understood for TDC interface interface (./makeTDCjam - parameters),(./makeTDCjam - parameters),
Program TDCs Program TDCs (./resetTDCdata.sh).(./resetTDCdata.sh).
TDC readout prototypeTDC readout prototype
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
Human readableTDC input file
Programming file
TDC A
makeTDCjam
TDC D
TDC C
TDC B
TDC readout prototypeTDC readout prototype
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
What we can program:What we can program: Setup register (646 bitsSetup register (646 bits)::
Time resolution,Time resolution,
Time windows,Time windows,
HPTDC mode,HPTDC mode,
HPTDC number…HPTDC number…
Control register (39 bits):Control register (39 bits):
Enable/disable channels,Enable/disable channels,
Using during start TDC.Using during start TDC.
TDC readout TDC readout prototypeprototype
FPGA on TRB boardFPGA on TRB boardCooperation with:Cooperation with: HADES bus interface,HADES bus interface, Etrax,Etrax, TDC,TDC, RAMs and FIFO.RAMs and FIFO.
FPGA
FIFO
RAM A
LVL1
LVL2
TDC A
TDC D
TDC C
TDC B
Etrax
RAM B
Data 32channel
Data 32channel
Data 32
channelD
ata 32channel
Data
Data
control
control
control
Ethernet
HADES DAQ
Data
LVL1 part
LVL2 part
HADES triggerbus
data/control
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany
TDC readout prototypeTDC readout prototype
Summary Summary 1.1. System is during tests and System is during tests and
improvements,improvements,2.2. In November there was RPC In November there was RPC
detector test with beam. It was detector test with beam. It was with full electronic chain with full electronic chain (detector, FEE, TRB),(detector, FEE, TRB),
3.3. TRB was fully integrated into TRB was fully integrated into the HADES-DAQ,the HADES-DAQ,
4.4. Crosstalk should be measured Crosstalk should be measured in more detail,in more detail,
5.5. New four boards has been New four boards has been built – we have some built – we have some problems with them.problems with them.
HADES Collaboration Meeting XVI4.- 8. April 2006, Dresden Germany