自己参照クロック技術とカスケード接続型時間差増幅器を用いた

参照クロック不要・高分解能オンチップタイミングジッタ測定回路 群馬大学大学院 針谷 尚裕 新津 葵一 櫻井 正人 平林 大樹 山口 隆弘 e-mail : t11801643@gunma-u.ac.jp 研究代表者 : 小林 春夫

Cro

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実装回路

C

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C

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結論

タイミングジッタ測定の原理

Cu

mu

lati

ve D

istr

ibu

tio

n

Fu

ncti

on

(C

DF

)

Dif

fere

nti

ate

0% 10% 50% 90% 100%

Pro

bab

ilit

y D

istr

ibu

tio

n

Fu

ncti

on

(P

DF

)

DT

Gaussian

Fitting

Obtain RMS

Value (s)

CUT(Clock

Under Test)

Ref.

Clock

Time Difference Between

CUT & Ref. Clock, DT

従来手法と提案手法の比較

3T-Delay

Latch OUT

Delay [ps]

0

40

80

120

160

200

1473 153115131491

Co

un

t o

f O

utp

ut

Pu

lse

Co

un

t o

f O

utp

ut

Pu

lse

REF

CUT

CUT

0

40

80

120

160

200

Conventional

(w/ Reference Clock)

Proposed

(w/ Self-Referenced Clock)

Latch OUT

T =500ps

2Broadened by

実装回路

CLK

(Period :T )

mbit Digital Code

(CDF)Latch CounterTDA

nT-delay

(n≥3)

DT in

Digital

Cascaded TDA

DT

Co

un

ter

Ou

tpu

t

CLK

(Period :T )

mbit Digital Code

(CDF)Latch Counter

nT-delay

(n≥3)

DT in

Digital

DT

Co

un

ter

Ou

tpu

t

w/o Time Difference Amplifier (TDA)

w/ Cascaded TDA

時間差増幅器によるジッタ増幅

時間差増幅器を用いたジッタ増幅により 28 fs 分解能を達成

ディジタル制御遅延線の分解能 : 4 ps

自己参照クロックによる分布の拡がり : x

4段のカスケード接続型時間差増幅器のゲイン : 約100

2

高ゲインの時間差増幅器は動作速度が低下

デューティサイクル補償 (670 MHz → 820 MHz)

Jitter

Amplification

by TDA

Time Resolution of

Digitally-Controlled

Delay Line

PDF of Jitter

(w/o TDA)

PDF of Jitter

(w/ TDA)

デューティサイクル補償の必要性

4-Stage Cascaded TDA (Gain : a4)

a-Gain

TDAaDTin a4DTin

Tout1

DTin

out1

in1

in2

out2Tout2

a4DTin

Pulse disappears

out1

out2

in1

in2

a-Gain

TDA

a-Gain

TDA

a-Gain

TDA

Rising EdgeFalling Edge

Non-overlapped

DTin

デューティサイクル補償の効果

in1

in2

Tout1

out1

in1’

in2’

out2Tout2

4-Stage Cascaded TDA (Gain : a4)

Duty Ctrl.

Duty Ctrl.

aDTin a4DTin

DTin

in1

in2

a4DTin

in1’

in2’

a-Gain

TDA

a-Gain

TDA

a-Gain

TDA

a-Gain

TDADTin

out1

out2

時間差増幅器のゲイン

DTin [ps]

DTout [ps]

500

-500

0

-5 5

ジッタ測定結果

0

1.5

2

Injected RMS Jitter [ps]

0 2.521.5

Me

as

ure

d R

MS

Jit

ter

[ps

]

2.5: 820MHz Clock: 410MHz Clock

テストチップ写真

Without TDA

(490 mm2)

With TDA

(1350 mm2)

Process : 65 nm CMOS

Supply Voltage : 1.2 V

35 mm

14 mm45 mm

30 mm

Cro

ssta

lk a

ncel

測定結果

ジッタ測定結果

0

1.5

2

Injected RMS Jitter [ps]

0 2.521.5

Me

as

ure

d R

MS

Jit

ter

[ps

]

2.5: 820MHz Clock: 410MHz Clock

Probability Distribution Function (PDF)

Time [ps]

-6 60-3 3

A T

imin

g J

itte

r P

DF

Me

as

ure

d

by T

he

Pro

po

se

d C

ircu

it

(Aft

er

Cali

bra

tio

n o

f T

DA

)

2.36 ps RMS1.67 ps RMS

Timing Jitter

Gaussian

Fitting

2

1

Calibration for Self-

referenced Clock

Clock Frequency

: 820 MHz

Injected Timing Jitter

: 1.61 ps RMS

DTin [ps]

DTout [ps]

500

-500

0

-5 5

Meas. CDF

TDA’s gain

Cumulative Distribution Function (CDF)

Relative Delay [ps]

0

256

512

768

1024

Co

un

t o

f O

utp

ut

Pu

lse

0 1220610305 915

(0) (1T )(0.5T )(0.25T ) (0.75T )

Clock Frequency : 820 MHz

まとめ

参照クロック不要，高分解能であるタイミングジッタ測定を実証

自己参照クロックは参照クロックの要求を取り除く

カスケード接続型時間差増幅器により高分解能化が可能

65 nm CMOSで試作を行い，提案回路の効果を検証

1.61 ps RMSジッタ(誤差4%)の検出に成功

820 MHz ，28 fs 分解能

従来手法 (参照クロックあり)

CUT

Dela

y o

f th

e D

ela

y L

ine

Ideal Clock

(Dotted Line)

+0.05T

OUT’”

+0.05T

Latch

CUT

OUT”’

OUT’

-0.05T

LatchOUT’

CUT-0.05T

0T

OUT”

+0T

Latch

CUT

OUT”

REF

REF

REF

REF

REF

REF

1

3

6

提案手法 (参照クロックなし)Ideal Clock

(Dotted Line)

Dela

y o

f th

e D

ela

y L

ine

1→2

3→3

6→5

研究背景・目的

200 fs RMSジッタを実現するようなADPLLが開発されている

低コスト(参照クロック不要)，高分解能(200 fs以下)であるオンチップタイミングジッタ測定回路が要求されている

従来手法は参照クロックを必要とし，分解能は400 fs

本研究

参照クロック不要，高分解能(28 fs)なオンチップタイミングジッタ測定回路を実現した

Period Jitter : JTiming Jitter : DfDf (0) Df (T) Df (2T)

T±J

性能比較

Process

This Work Conventional

(1, IBM)

Area

Reference Clock

w/o TDA w/ TDA

65 nm

Conventional

(2, Advantest)

130 nm 130 nm

Unnecessary Necessary Unnecessary

3200 mm2117000 mm2

+ I/O Pad

Measured JitterTiming

(Direct)Timing

(S Period)

Output Signal Digital DigitalHigh-Speed

Analog

490mm2 1350mm2

Frequency 2 GHz2.5 GHz3.5 GHz 820 MHz

Resolution N/A400 fs2.8 ps 28 fs

Timing

( Times) 2

オンチップジッタ測定の文献

This Work

Unnecessary

Digital

28 fs

Conventional

(1, IBM)

Reference Clock

Conventional

(2, Advantest)

Necessary Unnecessary

Measured JitterTiming

(Direct)Timing

(S Period)

Output Signal DigitalHigh-Speed

Analog

Resolution 0.4 ps N/A

本研究の狙い(文献[1]と比較)

自己参照クロック技術により，“参照クロック不要”のオンチップタイミングジッタ測定回路を実現

カスケード接続型時間差増幅器を用いて，高分解能(28 fs)を達成

Timing

( Times) 2

[1] K. Jenkins, et al., “An on-chip jitter measurement circuit with sub-picosecond

resolution,” in Proc. European Solid-State Circuits Conf., Sep. 2005, pp. 157-160.

[2] M. Ishida, et al., “A Programmable On-Chip Picosecond Jitter-Measurement Circuit

without a Reference-Clock Input,” in Proc. IEEE Int. Solid-State Circuits Conf.,

pp. 512-513, Feb. 2005.

理論的背景(“ ”倍に拡がる理由)

REF

RMS

CUT

RMS

REF

RMS

CUT

RMSSkew ffffs DDDD 2ˆ22

Latch

CUT

RMSfDREF

RMSfD

(Conventional [1]) (This Work)

Random Skew Measurement by Latching [3, T. Yamaguchi, TCAD]

RMS Value of Timing Jitter of Data, ClkCross-correlation

Coefficient,

LatchCUT

REF

CUTRMS

REFRMS ff DD

CUTRMSSkew fs Dˆ

Reference-Clock-Required Reference-Clock-Free

0.0][nTCUTREF ff DD

LatchCUT

nT-delay

(n≥3)

220ˆ nTCUTCUT

Skew ffs DD

CUTRMS

CUTRMS ff DD 22

2

REFRMS

CUTRMS

REFRMS

CUTRMSSkew ffffs DDDD 2ˆ

22 REFRMS

CUTRMS

REFRMS

CUTRMSSkew ffffs DDDD 2ˆ

22

2

[3] T. J. Yamaguchi, et al., “Skew Measurement in Clock Distribution Circuits Using an

Analytic Signal Method,” IEEE Trans. On CAD, vol. 23, no. 7, pp. 997-1009, Jul. 2004.

理論的背景(“ ”倍に拡がる理由)

REF

RMS

CUT

RMS

REF

RMS

CUT

RMSSkew ffffs DDDD 2ˆ22

Latch

CUT

RMSfDREF

RMSfD

(Conventional [1]) (This Work)

Random Skew Measurement by Latching [3, T. Yamaguchi, TCAD]

RMS Value of Timing Jitter of Data, ClkCross-correlation

Coefficient,

LatchCUT

REF

CUTRMS

REFRMS ff DD

CUTRMSSkew fs Dˆ

Reference-Clock-Required Reference-Clock-Free

0.0][nTCUTREF ff DD

LatchCUT

nT-delay

(n≥3)

220ˆ nTCUTCUT

Skew ffs DD

CUTRMS

CUTRMS ff DD 22

2

REFRMS

CUTRMS

REFRMS

CUTRMSSkew ffffs DDDD 2ˆ

22 REFRMS

CUTRMS

REFRMS

CUTRMSSkew ffffs DDDD 2ˆ

22

2

[3] T. J. Yamaguchi, et al., “Skew Measurement in Clock Distribution Circuits Using an

Analytic Signal Method,” IEEE Trans. On CAD, vol. 23, no. 7, pp. 997-1009, Jul. 2004.

関連発表論文および特許出願1) K. Niitsu, M. Sakurai, N. Harigai, D. Hirabayashi, T. J. Yamaguchi, and H. Kobayashi,

"A Reference-Clock-Free On-Chip Timing Jitter Measurement Circuit Using a Cascaded

Time Difference Amplifier in 65nm CMOS," accepted to IEEE/ACM Asia and South Pacific

Design Automations Conf. (ASP-DAC 2012, University LSI Design Contest), Jan. 2012.

2) N. Harigai, K. Niitsu, D. Oki, M. Sakurai, T. J. Yamaguchi, and H. Kobayashi, "A Twistedly-

Cascaded Time Difference Amplifier for High Robustness Against Process Variation," in

Proc. Int. Conf. on Solid-State Devices and Materials (SSDM 2011), Sep. 2011, pp. 184-185.

3) M. Sakurai, K. Niitsu, N. Harigai, D. Hirabayashi, D. Oki, T. J. Yamaguchi, and H. Kobayashi,

"Analysis of Jitter Accumulation in Interleaved Phase Frequency Detectors for High-

Accuracy On-Chip Jitter Measurements," in Proc. Int. SoC Design Conf. (ISOCC 2011),

Nov. 2011, pp. 146-149.

4) K. Niitsu, M. Sakurai, N. Harigai, T. J. Yamaguchi, and H. Kobayashi, "An On-Chip Timing

Jitter Measurement Circuit Using a Self-Referenced Clock and a Cascaded Time Difference

Amplifier with Duty-Cycle Compensation," in Proc. IEEE Asian Solid-State Circuits Conf.

(A-SSCC 2011), Nov. 2011, pp. 201-204.

5) 新津葵一、針谷尚裕、櫻井正人、小林春夫、「時間差増幅回路」、出願番号：特願２０１１－２０６２５８、出願日：平成２３年９月２１日

6) 新津葵一、小林春夫、「オンチップジッタデータ取得回路、ジッタ測定装置、及びその方法」、出願番号：特願２０１０－２１９２８６、出願日：平成 ２２年９月２９日