vhdl 7th sem

Table of Contents

S.No Assignment

1 Design of combinational circuit, 2-4 Decoder, 4-2 encoder, Binary to gray code converter using VHDL.

2 Model flip-flop, register and latch in VHDL. Implement Asynchronous and synchronous reset

3 Design of a state machine: Circuit to detect if an incomingSerial number is divisible by 5. Simulate the incoming serialNumber with a clock and Data in which is set to high or low.The incoming data is entering from the right. Use VHDL.

4 Design traffic light controller using VHDL.

5 Binary and BCD counter using VHDL.

6 Data demultiplexer. Data is required on a high speed 4-bit input bus, output to one of the three 4-bit output bus.

7 Serial in parallel out register using VHDL.

8 ALU using VHDL.

Assignment # 1

Design of 2x4 Decoder

--code for 2x4 decoder

library ieee;use ieee.std_logic_1164.all;

entity Decoder2x4 is port(i :in std_logic_vector(1 downto 0);e :in std_logic;o std_logic_vector(3 down to 0));end Decoder2x4;

architecture Behv of Decoder2x4 isbeginprocess(i,e)begin if(e=’1’) then o(0)<= (not i(0)) and (not i(1)); o(1)<= i(0) and (not i(1)); o(2)<= (not i(0)) and i(1); o(3)<= i(0) and i(1); else o<-“ZZZZ”; end if;end process;end architecture;

Test Bench

--test bench

entity TB isend TB;

architecture TB_arch of TB iscomponent Decoder2x4 is port(i :in std_logic_vector(1 downto 0);e :in std_logic;o std_logic_vector(3 down to 0));end component;signal i:std_logic_vector(1 downto 0);

signal e:std_logic;signal o:std_logic_vector(3 downto 0);begininst:Decoder2x4 port map(i,e,o);processbegin e<= not e after 80 ns; i<= transport “00”; wait for 20ns; i<= transport “01”; wait for 20ns; i<= transport “10”; wait for 20 ns; i<= transport “11”; wait for 20 ns;end process;end architecture;

Design of 4x2 Encoder

--code for 4x2 encoder


entity encoder4x2 is port(i:in std_logic_vector(3 downto 0);o:out std_logic_vector(1 downto 0);e:in std_logic);end encoder4X2;

architecture behv of encoder4x2 isbeginprocess(i,e)begin if e=’1’ then case i is when “0001”=> o<=”00”; when “0010”=> o<=”01”; when “0100”=> o<=”10”; when “1000”=> o<=”11”; when others=> o<=”ZZ”; else o<=”ZZ”; end if;end process;end architecture;

Test Bench

-- test bench

entity tb isend tb;

architecture tb_arch of tb iscomponent encoder4x2 is port(i:in std_logic_vector(3 downto 0);o:out std_logic_vector(1 downto 0);e:in std_logic);end component;signal i:std_logic_vector(3 downto 0);signal o:std_logic_vector(1 downto 0);

signal e:std_logic;begin inst:encoder4x2 port map(i,o,e);processbegin e<= not e after 40 ns; i<=”0001”; wait 10 ns; i<=”0010”; wait 10 ns; i<=”0100”; wait 10 ns; i<=”1000”; wait 10 ns;end process;end architecture;

Design of Binary to Gray Code Converter

-- code for binary to gray converter

library ieee;use ieee.std_logic_1164.all;entity b2g is port(i:in std_logic_vector(3 downto 0); o:out std_logic_vector(3 downto 0);e:in std_logic);end b2g;architecture behv of b2g isbeginprocess(i,e)begin if e=’1’ then o(0)<= i(0) xor i(1); o(1)<= i(1) xor i(2); o(2)<= i(2) xor i(3); o(3)<= i(3); else o<=”ZZZZ”; end if;end process;end architecture;

Test Bench

-- test benchentity tb isend tb;architecture tb_arch of tb iscomponent b2g is port(i:in std_logic_vector(3 downto 0); o:out std_logic_vector(3 downto 0);e:in std_logic);end component;signal i:std_logic_vector(3 downto 0);signal o:std_logic_vector(3 downto 0);signal e:std_logic;begininst:b2g port map(i,o,e);processbegin e<=not e after 30 ns;

i<=”0000”; wait for 10 ns; i<=”0011”’ wait for 10 ns; i<=”1010”; wait for 10 ns;end process;end architecture;

Assignment # 2

Design of Synchronous and Asynchronous Register

--synchronous register

library ieee;use ieee.std_logic_1164.all;entity syn_8_reg is port(d:in std_logic_vector(7 downto 0); q:out std_logic_vector(7 downto 0); clk:in std_logic;rst:in std_logic);end syn_8_reg;architecture behv_syn of syn_8_reg isbeginprocess(clk)begin if clk=’1’ then if rst=’1’ then q<=”00000000”; else q<=d; end if; end if;end process;end architecture;

--asynchronous register

library ieee;use ieee.std_logic_1164.all;entity asyn_8_reg is port(d:in std_logic_vector(7 downto 0); q:out std_logic_vector(7 downto 0); clk:in std_logic;rst:in std_logic);end asyn_8_reg;architecture behv_asyn of asyn_8_reg isbeginprocess(clk,rst)begin if rst=’1’ then q<=”00000000”; elsif clk=’1’ then

q<=d; end if;end process;end architecture;

Test Bench--test bench

entity tb isend tb;

architecture tb_arch of tb iscomponent syn_8_reg is port(d:in std_logic_vector(7 downto 0); q:out std_logic_vector(7 downto 0); clk:in std_logic;rst:in std_logic);end component;component asyn_8_reg is port(d:in std_logic_vector(7 downto 0); q:out std_logic_vector(7 downto 0); clk:in std_logic;rst:in std_logic);end component;signal d:std_logic_vector(7 downto 0);signal qsyn,qasyn:std_logic_vector(7 downto 0);signal clk:std_logic;signal rst:std_logic;begininst1:syn_8_reg port map(d,qsyn,clk,rst);inst2:asyn_8_reg port map(d,qasyn,clk,rst);clk<=not clk after 15 ns;rst<=not rst after 10 ns;processbegin d<=”00000000”; wait for 30 ns; d<=”00011100”; wait for 30 ns;end process;end architecture;

Design of Synchronous and Asynchronous D Flip-flop

--synchronous D flip-flop


entity syn_d_ff is port(d:in std_logic;q:out std_logic;clk:in std_logic; rst:in std_logic);end syn_d_ff;architecture behv_syn of syn_d_ff isbegin process(clk)begin if clk=’1’ then if rst=’1’ then q<=’0’; else q<=d; end if; end if;end process;end architecture;

--asynchronous D flip-flop library ieee;use ieee.std_logic_1164.all;

entity asyn_d_ff is port(d:in std_logic;q:out std_logic;clk:in std_logic; rst:in std_logic);end asyn_d_ff;architecture behv_asyn of asyn_d_ff isbegin process(clk,rst)begin if rst=’1’ then q<=’0’; elsif clk=’1’ then q<=d; end if;

end process;end architecture;

Test Bench

--test bench

entity tb isend tb;architecture tb_arch of tb is

component syn_d_ff is port(d:in std_logic;q:out std_logic;clk:in std_logic; rst:in std_logic);end component;component asyn_d_ff is port(d:in std_logic;q:out std_logic;clk:in std_logic; rst:in std_logic);end component;

signal d,qsyn,qasyn,rst,clk: std_logic;begininst1: syn_d_ff port map(d,qsyn,clk,rst);inst2: asyn_d_ff port map(d,qasyn,clk,rst);processbegin d<=’1’; wait for 30 ns; d<=’0’; wait for 30 ns;end process;clk<=not clk after 15 ns;rst<=not rst after 10 ns;end architecture;

Design of Latch

--D Latch library ieee;use ieee.std_logic_1164.all;

entity dlatch is port(d:in std_logic;q:out std_logic;clk:in std_logic; rst:in std_logic);end dlatch;architecture behv_latch of dlatch isbegin process(d,rst)begin if rst=’1’ then q<=’0’; elsif clk=’1’ then q<=d; end if;end process;end architecture;

Test Bench

entity tb isend tb;architecture tb_arch of tb iscomponent dlatch is port(d:in std_logic;q:out std_logic;clk:in std_logic; rst:in std_logic);end component;

signal d,q,rst,clk: std_logic;begininst: dlatch port map(d,q,clk,rst);processbegin d<=’1’; wait for 30 ns; d<=’0’; wait for 30 ns;end process;clk<=not clk after 15 ns;

rst<=not rst after 10 ns;end architecture;

Assignment # 3

Detection of divisibility by 5

library ieee;use ieee.std_logic_1164.all;entity FSM5 isport (i:in std_logic; re:out std_logic_vector(3 downto 0);o:out std_logic; clk:in std_logic);end FSM5;

architecture checkdiv5 of FSM5 istype states is (S1, S2, S3, S4, S5);signal state:states;signal count:integer range 0 to 31;beginp1:process(clk)beginif clk'event and clk='1' thencase state is when S1 =>

if i = '0' thenstate <= S1;else state <= S2;end if;

when S2 => if i = '0' thenstate <= S3;else state <= S4;end if;



when S5 => if i = '0' then

state <= S4;else state <= S5;end if;

end case;count <= count + 1;end if;if(state=S1) then re<="0000"; o<='1'; end if; if(state=S2) then re<="0001"; o<='0'; end if; if(state=S3) then re<="0010"; o<='0'; end if; if(state=S4) then re<="0011"; o<='0'; end if; if(state=S5) then re<="0100"; o<='0'; end if; end process;end checkdiv5;

Assignment # 4

Design of Traffic Light Controller

--traffic light controller


entity tlc is port(clk:in std_logic;red:out std_logic;yellow:out std_logic;green:out std_logic);end tlc;

architecture tlc_arch of tlc istype state is (SRED,SYELLOW,SGREEN);variable tlcstate :state:=SRED;variable count:integer:=0;beginprocess(clk)begin if clk=’1’ then case tlcstate is

when SRED=> if count=10 then tlcstate:=SGREEN; count:=0; else count:=count+1; red<=’1’; yellow<=’0’; green<=”0’;

end if; when SYELLOW=> if count=2 then tlcstate:=SRED; count:=0;

else count:=count+1; red<=’0’; yellow<=’1’; green<=’0’;

end if; when SGREEN=> if count=10 then tlcstate:=SYELLOW; count:=0; else count:=count+1; red<=’0’; yellow<=’0’; greem<=’1’; when others=> tlcstate:=SRED; count:=0; end case; end if;

end process;end architecture;

Test Bench

--test benchentity tb is end tb;

architecture tb_arch of tb iscomponent tlc is port(clk:in std_logic;red:out std_logic;yellow:out std_logic;green:out std_logic);end component;

signal clk:std_logic:=’0’;signal red, yellow, green : std_logic;beginclk<=not clk after 10 ns;inst:tlc port map(clk,red,yellow,green);end architecture;

Assignment # 5

Design of Binary Counter and BCD Counter

--binary counter

library ieee;use ieee.std_logic_1164.all;entity bincnt is port(count:out std_logic_vector(3 downto 0);clk:in std_logic;rst:in std_logic);end bincnt;

architecture bincnt_arch of bincnt isbeginprocess(clk,rst)begin if rst=’1’ then count<=”0000”; elsif clk’event and clk=’1’ then count<=count+1; end if;end process;end architecture;

--bcd counterlibrary ieee;use ieee.std_logic_1164.all;entity bcdcnt is port(count:out std_logic_vector(3 downto 0);clk:in std_logic;rst:in std_logic);end bcdcnt;

architecture bcdcnt_arch of bcdcnt isbeginprocess(clk,rst)begin if rst=’1’ then count<=”0000”; elsif clk’event and clk=’1’ then if count=”1001” then

count<=”0000”; else count<=count+1; end if; end if;end process;end architecture;

Test Bench

--testbench

entity tb is end tb;architecture tb_arch of tb iscomponent bincnt is port(count:out std_logic_vector(3 downto 0);clk:in std_logic;rst:in std_logic);end component;component bcdcnt is port(count:out std_logic_vector(3 downto 0);clk:in std_logic;rst:in std_logic);end component;signal clk,rst:std_logic:=’0’;signal bcdcount,bincount:std_logic_vector(3 downto 0);beginclk<=not clk after 20 ns;rst<=not rst after 400 ns;inst1: bincnt port map(bincount,clk,rst);inst2: bcdcnt port map(bcdcount,clk,rst);end architecture;

Assignment # 6

Design of 4 Bit Data Demultiplexer

--Demultiplexer 4 bit data on three 4 bit output bus


entity demux is port(din:in std_logic_vector(3 downto 0);sel:in std_logic_vector(1 downto 0);dout1, dout2,dout3:out std_logic_vector(3 downto 0));end demux;

architecture demux_arch of demux isbeginprocess(din,sel)begin case sel is when “00”=> dout1<=din; dout2<=”zzzz”; dout3<=”zzzz”; when “01”=> dout1<=”zzzz”; dout2<=din; dout3<=”zzzz”; when others=>dout1<=”zzzz”; dout2<=”zzzz”; dout3<=din; end case;end process;end architecture;

Test Bench

-- testbench

entity tb is end tb;

architecture tb_arch of tb iscomponent demux is port(din:in std_logic_vector(3 downto 0);sel:in std_logic_vector(1 downto 0);dout1, dout2,dout3:out std_logic_vector(3 downto 0));end component;signal din,dout1,dout2,dout3:std_logic_vector(3 downto 0);signal sel:std_logic_vector(1 downto 0);begininst:demux port map(din,sel,dout1,dout2,dout3);p1:processbegin din<=”0010”; wait for 20 ns; din<=”1001”; wait for 20 ns;end process;p2:processbegin sel<=”00”; wait for 25 ns; sel<=”01”; wait for 25 ns; sel<=”10”; wait for 25 ns; sel<=”01”; wait for 25 ns; sel<=”11”; wait for 25 ns;end process;end architecture;

Assignment # 7

Serial in Parallel Out


entity sipo is port(sin,clk,rst,enable:in std_logic; o:out std_logic_vector(3 downto 0));end sipo;

architecture sipo_arch of sipo issignal temp:std_logic_vector(3 downto 0);beginprocess(clk)begin if rst=’1’ then temp=”0000”; else if clk=’1’ and enable=’1’ then temp(3)<=temp(2); temp(2)<=temp(1); temp(1)<=temp(0); temp(0)<=sin; end if; end if;end process;o<=temp;end architecture;

--testbench

entity tb isend tb;architecture tb_arch of tb iscomponent sipo is port(sin,clk,rst,enable:in std_logic; o:out std_logic_vector(3 downto 0));end component;signal sin,clk,rst,enable:std_logic;

signal o:std_logic_vector(3 downto 0);begininst: sipo(sin,clk,rst,enable,o);clk<=not clk after 10 ns;processenable<=’1’;rst<=’0’;sin<=’1’;wait for 10 ns;sin<=’1’;wait for 10 ns;sin<=’0’;wait for 10 ns;sin<=’1’;wait for 10 ns;end process;end architecture;

Assignment # 8

ALU

entity arthm_comp isport (x,y: in bit_vector(3 downto 0); cin,op1,op2: in bit;f1: out bit_vector(3 downto 0));end entity;architecture arthm_comp_arch of arthm_comp iscomponent fa_4bit isport ( x , y : in bit_vector( 3 downto 0);carryin,op1,op2 : in bit;z : out bit_vector( 3 downto 0);

carryout : out bit);end component;beginadder_4bit: fa_4bit port map(x,y,cin,op1,op2,f1);end arthm_comp_arch;

LOGICAL COMPONENTentity logical isport(x: in bit_vector(3 downto 0);y: in bit_vector(3 downto 0); op1,op2: in bit; f2: out bit_vector(3 downto 0));end entity;architecture logical_arch of logical isbeginf2 <= x and y when op1='0' and op2='0' else x or y when op1='0' and op2='1' else x xor y when op1='1' and op2='0' else not x;end logical_arch;

1 BIT FULL ADDERentity fa_1bit isport ( a , b, cin : in bit ;f, cout : out bit);end entity;

architecture fa_1bit_arch of fa_1bit isbeginf <= a xor (b xor cin) ;cout <= (a and b ) or ( a and cin) or (b and cin) ;end fa_1bit_arch ;

4 BIT FULL ADDERentity fa_4bit isport (x,y: in bit_vector(3 downto 0); carryin,op1,op2: in bit; z: out bit_vector(3 downto 0); carryout:out bit);

end entity ;architecture fa_4bit_arch of fa_4bit iscomponent fa_1bit isport ( a , b, cin : in bit ;f, cout : out bit);end component ;component mux4x1 isport (a,b,c,d: in bit; s1,s2: in bit; e: out bit);end component;signal tmp_carry : bit_vector (2 downto 0);signal muxop:bit_vector(3 downto 0);signal temp:bit_vector(3 downto 0);begin temp<=not y;inst1: mux4x1 port map(y(0),temp(0),'0','1',op1,op2,muxop(0));inst2: mux4x1 port map(y(1),temp(1),'0','1',op1,op2,muxop(1));inst3: mux4x1 port map(y(2),temp(2),'0','1',op1,op2,muxop(2));inst4: mux4x1 port map(y(3),temp(3),'0','1',op1,op2,muxop(3));inst5: fa_1bit port map(x(0), muxop(0), carryin, z(0), tmp_carry(0) );inst6: fa_1bit port map(x(1), muxop(1), tmp_carry(0), z(1), tmp_carry(1) );inst7: fa_1bit port map(x(2), muxop(2), tmp_carry(1), z(2), tmp_carry(2) );inst8: fa_1bit port map(x(3), muxop(3), tmp_carry(2), z(3), carryout );end fa_4bit_arch ;

4X1 MULTIPLEXERentity mux4x1 is

port (a,b,c,d: in bit; s1,s2: in bit; e: out bit);end entity;architecture mux4x1_arch of mux4x1 isbegine <= a when s1='0' and s2='0' else b when s1='0' and s2='1' else c when s1='1' and s2='0' else d ;end mux4x1_arch;

ALU ARCHITECTUREentity alu isport (L,M:in bit_vector(3 downto 0);CIN,SEL1,SEL2,SEL3,SEL4: in bit; FOUT: out bit_vector(3 downto 0));end entity;architecture alu_arch of alu iscomponent arthm_comp isport (x,y: in bit_vector(3 downto 0);cin,op1,op2: in bit; f1: out bit_vector(3 downto 0));end component;component logical isport(x: in bit_vector(3 downto 0);y: in bit_vector(3 downto 0); op1,op2: in bit;f2: out bit_vector(3 downto 0));end component;component mux4x1 isport (a,b,c,d: in bit; s1,s2: in bit; e: out bit);end component;signal val1,val2: bit_vector(3 downto 0);beginAC: arthm_comp port map(L,M,CIN,SEL1,SEL2,val1);LC: logical port map(L,M,SEL1,SEL2,val2);MUX1: mux4x1 port map(val1(0),val2(0),'0',L(1),SEL3,SEL4,FOUT(0));MUX2: mux4x1 port map(val1(1),val2(1),L(0),L(2),SEL3,SEL4,FOUT(1));MUX3: mux4x1 port map(val1(2),val2(2),L(1),L(3),SEL3,SEL4,FOUT(2));MUX4: mux4x1 port map(val1(3),val2(3),L(2),'0',SEL3,SEL4,FOUT(3));end alu_arch;

ALU TESTBENCHentity alu_testbench isend entity;architecture alu_test_arch of alu_testbench iscomponent alu isport (L,M:in bit_vector(3 downto 0);CIN,SEL1,SEL2,SEL3,SEL4: in bit; FOUT: out bit_vector(3 downto 0));end component;signal in1,in2,out1:bit_vector(3 downto 0);signal cin,s1,s2,s3,s4 :bit;begininst1: alu port map(in1,in2,cin,s1,s2,s3,s4,out1);processbeginin1 <= "0001";in2 <= "0101";cin <='0';s1 <= '0';s2 <= '0';s3 <= '0';s4<='0';wait for 20 ns;s1 <= '0';s2 <= '1';cin<='1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';cin<='0';wait for 20 ns;s1 <= '0';s2 <= '0';s3 <= '1';wait for 20 ns;s1 <= '0';s2 <= '1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';wait for 20 ns;in1 <= "1001";in2 <= "0111";cin <='0';s1 <= '0';s2 <= '0';s3 <= '0';

wait for 20 ns;s1 <= '0';s2 <= '1';cin<='1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';cin<='0';wait for 20 ns;s1 <= '0';s2 <= '0';s3 <= '1';wait for 20 ns;s1 <= '0';s2 <= '1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';wait for 20 ns;

in1 <= "0001";in2 <= "0101";cin <='0';s1 <= '0';s2 <= '0';s3 <= '0';s4<='1';wait for 20 ns;s1 <= '0';s2 <= '1';cin<='1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';cin<='0';wait for 20 ns;s1 <= '0';s2 <= '0';s3 <= '1';wait for 20 ns;s1 <= '0';s2 <= '1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';wait for 20 ns;in1 <= "1001";in2 <= "0111";cin <='0';s1 <= '0';s2 <= '0';s3 <= '0';

wait for 20 ns;s1 <= '0';s2 <= '1';cin<='1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';cin<='0';wait for 20 ns;s1 <= '0';s2 <= '0';s3 <= '1';wait for 20 ns;s1 <= '0';s2 <= '1';wait for 20 ns;s1 <= '1';s2 <= '0';wait for 20 ns;s1 <= '1';s2 <= '1';wait for 20 ns;end process;end alu_test_arch;

vhdl 7th sem

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