xu ly anh video dung fpga tren de2-clbrobot-robotgiaoduc

iii

TOM TAT LUAN VAN

Luan van nay trnh bay ve thiet ke he thong x ly anh Video tren FPGA(CycloneII) bao

gom cac thanh phan: thu nhan va so hoa tn hieu Video Analog, x ly anh Video so, hien th

len VGA. Cyclone II giao tiep vi ben ngoai thong qua KIT DE2 (Ngoai CycloneII, cac thanh

phan tch hp tren KIT DE2 ma ta se s dung la: chip ma hoa tn hieu Video Analog

ADV7181B; SDRAM IS42S16400 e lu tr va xuat frame anh hp ly; chip ADV7123 e

hien th anh len man hnh). Qua trnh thc hien luan van se bao gom cac cong oan:

Ve c s ly thuyet can tm hieu:

Cach thc cai at che o hoat ong va cau truc cua tn hieu so ngo ra cua ADV7181B.

Nguyen tac c ban ve hoat ong cua SDRAM.

Cac phng phap va giai thuat x ly anh.

Cach thc hien th hnh anh len man hnh.

Thc hien thiet ke len CycloneII vi phan mem Quartus va Verilog HDL vi cac khoi:

Cai at che o hoat ong cho ADV 7181B thong qua giao thc I2C.

Nhan biet va tach cac d lieu can thiet trong chuoi byte do ADV7181B a ra.

Lu tr roi x ly frame anh theo 1 so cac phng phap a tm hieu.

Xuat anh ra man hnh thong qua chip ieu khien quet man hnh ADV7123.

X ly anh la lnh vc rat rong ln va ang phat trien manh me. Ta ch tm hieu va thc

hien mot so phng phap c ban.

www.robotgiaoduc.com www.clbrobot.com

Chng 1: KIT DE2 cua Altera

Trang 1

PHAN I: GII THIEU TONG QUAN

CHNG 1: KIT DE2 CUA ALTERA

1.1 S LC

Trong e tai luan van, ta se s dung phan mem Quartus II e tong hp chng trnh

sau o dch ra ma hex va lap trnh he thong len chip FPGA Cyclone II tren kit DE2 cua

Altera thong qua JTAG USB.

Hnh 1.1: Kit DE2

Kit DE2 co rat nhieu tnh nang cho phep cac nha thiet ke thc hien mot khoi lng

ln cac he thong, mach chc nang t n gian en phc tap. Di ay la cac tnh nang

c cung cap san tren kit DE2:

Altera Cyclone II 2C35 FPGA

Altera Serial Configuration device - EPCS16



Trang 2

USB Blaster dung e lap trnh he thong t PC, ho tr cac che o JTAG cung

nh ieu khien trc tiep khi s dung NIOS II

512 Kbyte SRAM

8 Mbyte SDRAM

4 Mbyte Flash memory

Khe cam SD Card

4 phm nhan PushButton KEY[3:0]

18 Switch (cap mc 0 hay 1)

18 en LEDR va 9 en LEDG

Co hai nguon clock la 50 MHz va 27 MHz

Chip giai ma am thanh 24 bits vi cac jack cam line-in, line-out va microphone

VGA DAC (10-bit high-speed triple DACs) vi cong VGA

TV Decoder (NTSC/PAL) vi TV-in (Video-in)

Cong 10/100 Ethernet

Bo ieu khien USB host/slave

RS 232 vi cong ket noi 9 chan

Cong PS/2 giao tiep vi chuot va keyboard

Cong hong ngoai

40 chan e m rong

Khi tong hp chng trnh roi gan chan cho he thong, ta ch can khai bao chan ung

theo ten cua bang chan trong file Excel DE2_pin_assignments i kem vi a cai. Roi

thc hien File Menu >> Assignments >> Import Assignments >> Browser en file o.

Chng trnh Quartus II se t ong gan chan theo ung bang chan tren.

Trong e tai, cac thanh phan cua Kit DE2 ma ta se s dung la Cyclone II 2C35

FPGA, congTV-IN (ADV7181B) e nhan d lieu Video, SDRAM e lu tr cac frame

anh, cong VGA (ADV7123) e truyen anh len monitor. Altera Cyclone II 2C35 FPGA von

a rat quen thuoc vi sinh vien cua bo mon ien T nen khong e cap lai na. Tiep theo

ta tm hieu s lc hoat ong cua ADV7181B, SDRAM.



Trang 3

1.2 CHIP MA HOA TN HIEU VIDEO ADV7181B:

1.2.1 CHC NANG VA DANG D LIEU NGO RA

Nguon anh can x ly la tn hieu analog video do DVD player xuat ra. Ket noi ngo ra

TV-Out composite cua DVD Player vi cong TV-In tren Kit DE2 th bo ADV7181B se so

hoa tn hieu nay sang chuan ITU-RTBT 656 la chuoi cac frame anh. Moi iem trong

frame anh thu ve c bieu dien di dang I(x,y) trong o x,y la toa o cua pixel tren

frame va I la mc xam tng ng cua pixel o. Nh vay 1 frame anh thu c se c

bieu dien di dang mot ma tran 2 chieu 720 x 525 vi 720 la so pixel tren 1 hang, 525 la

so hang trong 1 frame.

chuan Video ITU RBT 601:

Chuan ITU R BT 601/656 nh ngha mot thiet ke cho viec ma hoa an xen mot

khung bao gom 525 (hoac 625) line tn hieu video tng t thanh dang so, truyen tn

hieu vi xung clock 27Mhz. Mot single horizontal line co cau truc:

EAV, BLANKING va SAV la cac trng (field) phan biet e ong bo d lieu c truyen.

EAV va SAV eu la cac trng 4 byte :

-EAV: cho biet iem ket thuc cua Active Video Data trong line hien hanh cung nh

la iem bat au cua line tiep theo.

-SAV: bao hieu iem bat au cua Active Video Data trong line hien hanh.

FFh 00h 00h XY

Byte th t XY cha thong tin ve trng c truyen,tnh trang cua khoang trong

(field blanking) theo chieu doc (Vertical) hoac cua dong trong (line blanking) theo chieu

ngang (horizontal):



Trang 4

Bit Symbol Chc nang

7 1 Luon mc 1

6 F Field Bit: 0 => Filed1; 1 => Filed2

5 V

Vertical Blanking Status Bit:

-Len mc cao khi vertical field blanking interval.

-Xuong mc thap cac trng hp khac.

4 H

Horizontal Blanking Status bit:

-Neu la trng SAV th mc 0.

-Neu la trng EAV th mc 1.

3 P3 Protection bit 3




Cac Protection Bits th dung e kiem tra va sa loi phu thuoc vao cac bit F, V, H.

Nhng khi nhan Video Stream ta co the bo qua cac bit nay nen ta khong xet en.

Y ngha cua cac bit F va V la e am bao s ong bo cac horizontal line trong mot

frame theo chieu doc:



Trang 5

Cach at gia tr cac bit F, V theo cac trng (Field 1 hoac 2) va tnh hieu dung

(Active or Blanking) se c hieu ro hn qua bang mo ta mot frame gom 525 horizontal

line sau:

-Field1 (F=0): 262 line t line 4 en line 265; Field 2(F=1): 263 line t line 266 en line 3

-Active or Blanking: cac Active video data va cac Vertical Blanking Interval c sap

xep xen ke nhau:

Active portion(V = 0): Odd Field: 244 line t 20 -> 263; Even Field: 243 line t 283 -> 525;

Vertical Blanking Interval (V = 1): 38 line gom 19 line t 1 -> 19 va 19 line t 266 -> 282;

Hnh 1.2: Frame anh theo chuan ITU656



Trang 6

Mot horizotal line tn hieu se gom cac thanh phan sau:

Blanking: Trong suot thi gian truyen tn hieu Video, gia cac Active video signal

segments se la cac horizontal blanking interval. Gia tr cua cac byte trong trng nay se

phai phu hp vi cap o (levels) cua cac tn hieu Cb, Cr va Y tng ng theo quy tac sau:

Cb = 80h; Y = 10h; Cr = 80h ta co chuoi byte : 80h,10h,80h, . . . .80h,10h.

Tuy vao so line tn hieu ma chuoi nay se bao gom 268 byte (khung 525 line) hoac la

280 byte (khung 625 line)

Active Video Data: Co tat ca 1440 byte cha ng cac thong tin ve anh: 720 gia tr Y

(luminace-brightness); 360 gia tr Cr (red chrominace); 360 gia tr Cb (blue chromiance)

c sap xep theo tng nhom c mot Cb va Cr th co 2 gia tr Y: CbYnCrYn+1 tao thanh

chuoi: Cb0Y0Cr0Y1Cb1Y2Cr1Y3............Cb359Y718Cr359Y719.

Cac trng SAV va EAV: moi trng dai 4 byte

Vay trong he thong 525 line th mot Horizontal line se bao gom 1716 byte.

1.2.2 GIAO THC CAI AT I2C

ADV7181B ho tr mot giao dien ket noi 2 day tuan t a 2-wire serial interface

I2C. Hai ngo vao : d lieu tuan t SDA, xung clock tuan t SCLK mang thong tin gia

ADV7181B vi bo ieu khien he thong I2C. Moi thiet b t(Slave) se c nhan ra bi

mot a ch duy nhat.

Cac chan I2C cua ADV7181B cho phep ngi dung cai at, cau hnh bo ma hoa va

oc ngc lai d lieu VBI (vertical blank interval) bat c. ADV7181B co 4 a ch Slave

cho ca thao tac oc va ghi phu thuoc vao mc logic cua chan ALSB. ALSB ieu khien bit

1 cua a ch Slave ( Slave_address[1] ) bi viec thay oi chan nay co the ieu khien c

ca hai bo ADV7181B ma khong co s xung ot v trung a ch Slave. Bit thap nhat cua

a ch Slave ( LSB hay la Slave_address[0] ) quyet nh thao tac ghi hay oc: mc 1 oc

va mc 0 th ghi. ay ta ch s dung 1 bo ADV7123, giao thc I2C chu yeu dung e nap

d lieu cho cac thanh ghi nen chon a ch Slave cho chip ma hoa nay la 0x40h t bang

gia tr a ch I2C Slave di ay:



Trang 7

I2C Address for ADV7181B

ALSB R/

W

Slave Address

0

0

1

1

0

1

0

1

0x40h = 0000xxxx01000000b

0x41h = 0000xxxx01000001b

0x42h = 0000xxxx01000010b

0x43h = 0000xxxx01000011b

e ieu khien thiet b tren Bus th phai co mot giao thc ac biet i kem. au tien

Master se khi ong truyen d lieu bang viec thiet lap ieu kien bat au( SDA t 1 xuong

0 trong khi SCLK van mc cao ) ay ta goi la START, no am ch rang theo sau o la

mot luong a ch hay d lieu. Cac ngoai vi ap tra lai START va dch chuyen 8 bit tiep

theo (7 bit a ch va 1 bit oc/ghi ), cac bt nay c truyen t bit cao(MSB) en

thap(LSB) . Cac ngoai vi khi a nhan ra cac a ch c truyen th ap ng bang cach gi

SDA = 0 trong toan bo chu ky th 9 cua xung clock goi la ACK. Cac thiet b khac th se rut

khoi Bus tai iem nay va bao toan trang thai IDE( khi ca SDA va SCLK eu mc cao e

cho cac thiet b theo doi 2 line nay, ch START va a ch c truyen ung ). Bit oc/ghi

ch ra hng cua d lieu, LSB = 0/1 th Master ghi/oc thong tin vao/t ngoai vi.

ADV7181B hoat ong nh thiet b Slave tieu chuan tren Bus, cha 196 a ch con(

Subaddress la o lech cua a ch can thao tac vi a ch thiet b) e cho phep truy cap

cac thanh ghi noi. ieu o giai thch rang byte au tien la a ch cua thiet b va byte th

hai la a ch con au tien. Cac a ch con nay t ong tang dan cho phep truy oc/ghi

a ch con bat au. S truyen d lieu th luon b ngat bi ieu kien dng (STOP). Ngi

dung co the truy cap ti bat c duy nhat 1 thanh ghi a ch con tren c s 1-1 khi khong

co s cap nhat toan bo cac thanh ghi. e tai nay ta khong s dung che o cap nhat toan

bo ma ch truy cap vao cac thanh ghi can thiet cac a ch con tren c s 1-1.

START va STOP co the xuat hien bat k au trong s truyen d lieu, neu cac ieu

kien nay c khang nh ngoai chuoi lien tuc vi cac thao tac oc va ghi thong thng,

th no tac ong lam bus tr ve trang thai IDE. Neu a ch ngi dung phat ra khong phu

hp( invalid ) th ADV7181B se khong gi xac nhan ACK va tr ve trang thai IDE.

Neu cac a ch con t ong tang dan roi vt qua gii han a ch con cao nhat:



Trang 8

Neu ang oc th nhng gia tr cha ng trong thanh ghi co a ch con cao nhat se

c tiep tuc oc cho en khi Master phat 1 NACK (SDA khong b a xuong mc thap

trong toan bo chu ky th 9) e ch rang viec oc ket thuc.

Neu ang ghi th nhng gia tr cua byte khong phu hp se khong c load

Hnh 1.3: Truyen d lieu tren Bus va chuoi oc va ghi tuan t vi giao thc I2C

Truy cap cac thanh ghi: MPU co the viet hoac oc cac thanh ghi ngoai tr cac

a ch con, chung ch c ghi, chung ch ra cac thanh ghi ma tac vu oc hay ghi tiep theo

truy cap en. Moi s giao tiep vi phan nay thong qua Bus START vi mot s truy cap

cac thanh ghi nay. Cac thao tac ghi hay oc se c thc hien t/en a ch ch, roi tang

len a ch tiep theo en khi mot lenh STOP tren Bus c thc thi.

Lap trnh cac thanh ghi: cau hnh cho tng thanh ghi, thanh ghi giao tiep gom 8 bt

ch c ghi. Sau khi thanh ghi nay c truy cap tren bus va mot thao tac oc/ghi c

la chon, cac a ch con c cai at ch ra cac thanh ghi ma cac tac vu se at ti.

Chon la thanh ghi: (SR en SR0) nhng bt nay c cai at e ch ra a ch bat

au c yeu cau.

Chuoi I2C : c s dung khi can cac thong so vt qua 8 bit, v vay no phai c

phan phoi tren t nhat la 2 thanh ghi cua I2C:

Khi mot thong so c thay oi bi 2 lan ghi th no co the gi gia tr khong phu hp

(invalid) trong khoang thi gian lan au va lan cuoi I2C c hoan thanh, co ngha la cac

bit au cua no co the mang gia tr mi trong khi cac bit con lai van gi gia tr cu.



Trang 9

e tranh sai sot nay chuoi I2C se gi cac bit gia tr cap nhat cua cac thong so trong

bo nh cuc bo, va cac bit cua chuoi I2C c cap nhat vi nhau mot lan khi tac vu ghi vao

thanh ghi cuoi cung hoan thanh.

Tac vu hp ly tren chuoi I2C se da tren cac c s sau: Cac thanh ghi danh cho chuoi

I2C se c ghi theo th t tang dan a ch cac thanh ghi. V du: HSB[10:0] th ghi len

0x34 trc roi ngay lap tc ghi them vao 0x35.

1.2.3 CAI AT CAU HNH HOAT ONG :

Di ay la bang mo ta cac thanh ghi va cac gia tr can c cai at e phat hien

chuan Video Analog NTSC 525 line ngo vao va ma hoa sang chuan ITU656 ngo ra:

Bang 1.1: Cai at gia tr cho cac thanh ghi cua ADV7181 tng ng

sudadd Thanh ghi Gia tr cai at Chu giai

0x00h

Input

Control

00h: e chon ngo vao la dang hon

hp (Composite) va co the t

ong phat hien ra 1 trong cac

chuan: SECAM, PAL( B/G/H/I/D

), NTSC ( khong co pedestal )

50h:e phat hien chuan NTSC-M

-4 bit thap dung e chon

nh dang ngo vao.

-4 bit cao dung e chon che

o khi ma ngo vao la cac

chuan Video (PAL, NTSC,

SECAM ) th ADV7818 co

the t phat hien.

0x04h

Extended

Output

Control

02h: cho phep bo giai ma ket noi

trc tiep vi bo ma hoa

-bit 1 quyet nh bo giai ma

co ket noi trc tiep vi bo

ma hoa hay khong.

0x08h

Contrast

Register

ieu chnh o tng phan nh vao

o li cua thanh phan Luma

-Tuy vao gia tr thanh ghi

nay ma tnh o li thanh

phan Luma

0x0Ah

Brightnes

Register

ieu chnh o sang cua tn hieu

Video

-Tuy vao gia tr thanh ghi

nay e tnh o sang



Trang 10

0x0Eh

ADI

Control

Bit 5 mc 0 th truy cap ban o

thanh ghi cua ngi dung, mc 1

truy cap ban o thanh ghi ngat

c cai at tuy y tr bit 5.

Bit5 dung e cho phep ngi

dung truy cap ban o ngat

0x10h

Status

Register1.

ReadOnly

Ta at bit 4 len 1 e bao rang

chuan NTSC4-4-3 c phat hien

4 bit thap cung cap thong tin

ve trang thai noi cua bo ma

hoa, cac bit 4, 5, 6 bao cao

chuan Video c phat hien

0x11h

INDENT

ReadOnly

ADV7818B th dat gia tr 13h

Cung cap s nhan dien trong

s xem xet lai cac thanh

phan

0x15h

Digital

Clamp

Control 1

00h at che o au noi cham

Slow

Bo nh th thi gian au noi

so (digital clamp) quyet nh

thi hang cua mot bo au

noi tot

0x17h

Shaping

Filter

Control

41h: bit 6 = 1 th chon bo loc SH1

oi vi thanh phan chrom, bit 1 =

1 va cac bit 4,3,2,1 = 0 th che o

t ong chon bo loc cho thanh

phan luma: gai xung thap cho

nguon tn hieu kem chat lng

hoac bang rong cho nguon chat

lng cao

Cho phep la chon 1 day

cac bo loc thap hay loc gai

xung thap hoac bo ma hoa

se chon mot bo loc toi u

tuy theo chat lng nguon

tn hieu a vao

0x2Bh

Misc Gain

Control

00h: Cap nhat cho peak white tren

tng line video va che o mau

Bit 0 xac nh chu ky cap

nhat cho peak white. Bit7

cai at che o mau hay

trang en.

0x2Ch

AGCMod

e

Control

8Ch: co nh o li mau va o

sang (phng phap thu cong)

thong qua cac chuoi CMG[11:0]

(mau ) va LMG[11:0] (o sang).

2 bit cuoi chon che o cho

o li mau. Cac bit 6,5,4 cai

at che o e ieu khien o

li cho o sang. Bit 7,3,2

luon at mc 1.



Trang 11

0x2Dh

Chroma

Gain

Control 1

F8h: 2 bit 5,4 luon at mc 1.

Hai bit au = 1 dung trong che o

thch nghi toc o AGC

4 bit cuoi CMG[11:8] lap

trnh o li mau mong

muon. Bit 7,6 la CATG[1:0]

nh th cho o li mau t

ong theo doi toc o AGC

0x2Eh

Chroma

Gain

Control 2

Tuy vao o li mau can co ma at

gia tr. CMG[11:0] =750d th o

li =1 vi he NTSC. CMG[11:0] =

741d th o li = 1 vi he PAL

Tng ng vi CMG[7:0] e

ket hp vi 4 bit cuoi cua

Chroma Gain Control 1 e

tao CMG[11:0] xac nh o

li mau

0x2Fh

Luma

Gain

Control 1

F4h: 2 bit 5,4 luon at mc 1.

Hai bit au = 1 dung trong che o

thch nghi toc o AGC

4 bit cuoi LMG[11:8] lap

trnh o li sang mong

muon. Bit 7,6 la LATG[1:0]

nh th cho o li mau t

ong theo doi toc o AGC

0x30h

Luma

Gain

Control 2

Tuy vao o li mau can co ma at

gia tr.LMG[11:0]=1234d th o

li = 1 vi he NTSC. CMG[11:0]

=1266d th o li = 1 vi he PAL

ng vi LMG[7:0] ket hp

vi 4bit cuoi cua Luma Gain

Control1 tao LMG[11:0] xac

nh o li mau

0x31h

VS and

FIELD

Control 1

12h:bit3 = 0 bat au 1 line tng

quan vi HSE vabit5 = 1 th nh

v VS/Field thu cong qua cac

thanh ghi 0x32,0x33,0xE50xEA

Bit3 quyet nh viec bat au

line tng quan vi HSE hay

HSB Bit4 chon che o cua

SAV/EAV

0x32h

VSync

Field

Control 2

81h:Bit6 = 0 VS len mc cao gia

line thuoc Even Field. Bit7=1 VS

chuyen trang thai au line thuoc

Old Field. Bit0=1 la mac nh

Bit7,6 quy nh VS oi trang

thai (bat au 1 line) hay len

mc cao ( gia line) thuoc

Even hay Old Field

0x33h

VSync

Field

Control 3

84h:Bit6=0 VS xuong mc thap

gia line thuoc Even Field. Bit7=1

VS oi trang thai au line thuoc

Odd Field. Bit2=1 la mac nh.

Bit 7,6 la VHESE,VHESO

quy nh VS oi trang thai

(bat au 1 line) hay len mc

cao ( gia line) thuoc Even

hay Odd Field



Trang 12

0x37h Polarity

A0h: VS va HS tch cc mc thap

va Field tch cc mc cao. LLC1

ao ngc cc tnh so vi s o

nh th.

Bit 6,4,2 luon cai mc 0.

Bit 3,5,7 xac nh mc tch

cc cua Field,VS,HS. Bit1

xac nh LLC1 co ao cc

tnh hay khong

0x3Ah

16h: cho phep Power Down tren

ADC2, ADC1. ADC0 hoat ong

bnh thng. Bit4 mac nh la 1.

Bit 1,2,3 mc 1 cho phep

che o Power-Down tng

ng tren cac bo ADC2,

ADC1, ADC0

0x50h

CTI DNR

Control 4

00h: nh vay ta coi nh khong co

cac xung nhieu.

04h,20h: ( cai at theo khuyen

ngh ) e tnh bu phan xung nhieu.

DNR_TH[7:0]: ac ta so

canh xung toi a c hieu

la nhieu nen se coi la trong.

0x51h

Lock

Count

Bit6 la SRLS chon tn hieu khoa

tho(s tran Field vi cac thong tin

chieu doc hay xet tng hang line-

to-line )

00h: so line trong tnh trang khoa

trc khoa la 1, trc mat khoa la

1. Chon tn hieu khoa tho la tran

Field, khoa trang thai ch nh vao

khoa hang

-3 bit cuoi la CIL [2:0] quy

nh so line con lai trong

tnh trang khoa trc khi ch

trang thai khoa

-Bit5,4,3 la COL[2:0] quy

nh so line con lai ngoai

tnh trang khoa trc khi ch

trang thai mat khoa

-Bit7:khoa trang thai ch nh

vao khoa hang hay ca khoa

hang va ca song mang phu

0xC3h

ADC

SWITCH 1

05h: ADC1 khong ket noi, ADC0

noi vi AIN6 (tren DE2 th cong

TVin ch noi vi chan AIN6 cua

ADV7181)

Phai at SETADC_sw_man_en = 1

thanh ghi 0xC4h.

4 bit thap la ADC0_SW[3:0]

, 4 bit cao la ADC1_SW[3:0]

e ieu khien viec chon thu

cong cho ADC0 va ADC1



Trang 13

0xC4h

ADC

SWITCH 2

80h: ADC2 khong c ket noi.

Bit7 = 1 th mi cho phep cac cai

at thu cong thanh ghi 0xC3h,

0xC4h

-4 bit thap la ADC2_SW[3:0]

-Bit7 la SETADC_sw_man_en

0xE4h

SD

Saturation

Cr

3Eh: tang o li mau vi he so

khac 0 db

SD_SAT_CB [7:0] ieu

chnh s bao hoa cua bc

hnh bang viec tang giam

tac ong mau

0xE5h

NTSC V Bit

Begin

80h: Bit7 la NVBEGDELO len 1 :

lam cho viec bit V len mc cao b

tre 1 line thuoc Odd Field.

5 bit cuoi la NVBEG[4:0]

ch ra so line sau khi lcount

cung tac ong e at V len

cao.

0xE6h

NTSC V Bit

End

03h: Bit7,bit6 la NVENDDELO

va NVENDDELE mc 0 nen

khong lam tre

5 bit cuoi la NVEND[4:0]

ch ra so line sau khi lcount

cung tac ong e a V

xuong thap .

0xE7h

NTSC F Bit

Toggle

85h: Bit7 la NVBEGDELO len 1 :

lam cho viec chuyen oi cua bit F

b tre 1 line thuoc Odd Field.

5 bit cuoi la NFTOG[4:0] ( =

00011 th mac nh) ch ra so

line sau khi lcount cung tac

ong e chot tn hieu F .

0xEAh

PAL F Bit

Toggle

0Fh: khong tao tre. PAL mac nh

th PFTOG[4:0] = 00011

5 bit cuoi la PFTOG[4:0] ch

ra so line sau khi lcount

cung tac ong e chot tn

hieu F .

Hai thanh ghi a ch 03h va 8Fh c gi nguyen nh mac nh cua nhasan xuat

e cho ra nh dang video ITU656 8 bit tren cac chan P8 en P15 cua Pixel Port ong thi

tan so clock a ra LLC la 27MHz.

Tai cac a ch 00h, 0Eh, 10h, 11h, 3Ah, C3h va C4h la cac thanh ghi can c nap

gia tr chnh xac nhng bit nhat nh, so con lai c cai at theo khuyen ngh cua nha

san xuat. ong thi tai a ch 0037h ta at che o ao ngc tnh cua cac tn hieu VS,

HS, FIELD so vi gian o nh th. Khi o dang song H, F, V ngo ra co dang :



Trang 14

Hnh 1.4: Dang song do ADV7181B xuat ra vi cau hnh hoat ong e ra.

Tn hieu V khong nhng ch la tn hieu ong bo ma con cho biet trong cac khoang t

line 1 en line 9 va t line 264 en line 272 th bit V tng ng trong trng SAV mc 1,

ch ra rang o la cac Line trong (Blanking). ay la iem khac biet so vi frame anh theo

chuan ITU656 Hnh 2 ma ta can chu y khi chon d lieu e x ly sau nay.


Chng 1: Kit DE2 cua Altera

Trang 15

1.3 SDRAM IS42S16400

SDRAM IS42S16400 co tat ca 67180864 bit SDRAM c to chc thanh 4 dai

(BANK) nh, moi dai co dung lng 1024576 t (Words) 16 bit vi toc o truyen d lieu

co the len en 133MHz.

1.3.1 NGUYEN TAC HOAT ONG

Thc hien viec truyen d lieu qua cac chan a ch va d lieu di s chi phoi cua

cac chan dieu khien:

CKE Cho phep xung clock. Khi tn hieu nay mc thap, chp x ly giong nh la

xung clock hoan toan b dng lai.

/CS La chon Chip: mc cao, th bo qua tat ca cac au vao khac (ngoai tr

CKE), va hoat ong nh mot lenh NOP nhan c.

DQM Mat na d lieu: Khi cao, nhng tn hieu nay khong che d lieu vao/ra. Khi i

kem vi s viet, d lieu khong that s viet vao. Khi d lieu c gi mc trong 2 chu ky

trc mot chu ky oc, viec oc khong c a ra t chp. Tren mot chp nh x16 hay

DIMM, vi 1 t 8 bit th co mot hang DQM.

/RAS Row Address Strobe la bit ieu khien cho qua a ch hang

/CAS Column Address Strobe bit ieu khien cho qua a ch cot

/WE Write enable cho phep ghi

Cac tn hieu /RAS, /CAS, /WE dung e la chon 1 trong 8 lenh. Noi chung th dung

e phan biet cac lenh oc, ghi.

SDRAM ben trong c chia thanh trong 2 hay 4 dai (Bank) d lieu noi oc lap ben

trong. Mot hoac hai a ch vao cua dai (Bank) BA0 va BA1 se la chon Bank ma lenh tac

ong en.

Phan ln cac lenh eu s dung a ch c a vao ngo vao a ch. Nhng co mot

so lenh lai khong s dung chung, hay ch bieu dien mot a ch cot,v vay ta s dung A[10]

e la chon nhng phng an.



Trang 16

Bang 1.2: Cac che o truy cap SDRAM

/CS /RAS /CAS /WE Ban A10 An Lenh

H X X X X X X c che cac lenh khac

L H H H X X X Khong lam g ca(NOP)

L H H L X X X Dng (huy) truyen khoi: dng lenh oc

khoi hay ghi khoi khi ang thc hien.

L H L H Bank L Column Read: oc khoi d lieu t hang kch hoat

hien hanh.

L H L H Bank H Column

oc vi Precharge ( nap lai ) t ong: khi

thc hien xong th Precharge ( tc la ong

hang lai).

L H L L Bank L Column Write: ghi khoi d lieu t hang kch hoat

hien hanh.

L H L L Bank H Column

Ghi vi s nap lai t ong: khi thc hien

xong th nap lai (Precharge) tc la ong

hang lai.

L L H H Bank Row Active(kch hoat): m mot hang vi lenh

Read va Write.

L L H L Bank L X Precharge( nap lai): Ngng hoat ong hang

hien hanh cua bank (dai) c chon

L L H L X H X

Precharge all (nap lai toan bo): Ngng hoat

ong hang hien hanh cua tat ca cac bank

(dai).

L L L H X X X

Auto refresh (t ong lam ti): lam ti 1

hang cua tng bank,s dung bo em noi.

Tat ca cac dai phai c nap lai.

L L L L 0 0 Mode

Load mode register (che o nap cac thanh

ghi): A[9:0] c nap e cau hnh chip

DRAM.

Trong o quan trong nhat la ngam nh

CAS (2 hoac 3 chu ky) va chieu dai khoi

(1, 2, 4 hoac 8 chu ky)



Trang 17

1.3.2 S TNG TAC CAC TN HIEU IEU KHIEN SDRAM

Khong co lenh nao luon c cho phep

o Lenh che o nap cac thanh ghi (load mode register command) yeu cau tat ca cac

dai (Bank) trang thai IDE, va phai tr hoan ve sau cho s thay oi e tac ong.

o Lenh t ong lam ti (auto refresh command) th yeu cau tat ca cac dai (Bank)

trang thai IDE, va mat 1 khoang thi gian lam ti e a Chip ve trang thai IDE: thng

la trcd + trp.

o Ch co nhng lenh khac th cho phep tren mot Bank IDE la cac lenh kch hoat.

Can phai mat trcd trc khi hang c m hoan toan va chap nhan mot lenh oc hay ghi.

o Khi mot dai (Bank) c m th co 4 lenh c cho phep: oc, ghi, ket thuc

truyen khoi (Burst terminal), nap lai (precharge). Lenh oc, ghi bat au truyen khoi va co

the b ngat bi nhng ngat sau:

-Ngat mot oc khoi d lieu:

Sau mot lenh oc th bat c luc nao cung co the co mot trong cac lenh: oc, ket thuc

truyen khoi, hoac la nap c phat ra. Va se ngat oc khoi nay neu co mot ngam nh

CAS c cau hnh. Neu co 1 lenh oc thi iem 0, 1 lenh oc khac chu ky 2, ngam

nh CAS chu ky 3 th lenh oc au tien se truyen khoi d lieu ra ngoai chu ky 3 va 4,

va ket qua cua lenh oc th 2 se bat au xuat hien chu ky 5.

Neu lenh chu ky 2 la ket thuc truyen khoi hoac la nap lai Bank kch hoat th khong

co d lieu ra chu ky 5.

Mac du viec ngat lenh oc co the xuat hien mot Bank bat ky , nhng lenh nap lai

ch ngat viec oc khoi neu no tac ong tren cung mot Bank hoac tat ca cac Bank, neu

lenh nay hng en mot Bank khac th viec oc khoi van tiep tuc.

S ngat oc tao ra bi mot lenh ghi th cung co the nhung se kho khan hn. Thc

hien ieu nay nh vao mot tn hieu DQM e khong che ngo ra cua SDRAM , v vay trong

khoang thi gian nay,chp ieu khien bo nh co the lai d lieu i qua chan DQ e ghi vao

SDRAM. V tac ong cua DQM tren lenh oc th b tr hoan 2 chu ky trong khi oi vi



Trang 18

lenh oc th ngay lap tc, nen DQM phai len mc cao (raised) sm hn 2 chu ky trc khi

co lenh ghi.

e thc hien ieu nay trong 2 chu ky th yeu cau nh v thi iem SDRAM tat ngo

ra tai 1 canh len xung Clock va thi iem d lieu c cung cap (cho lenh ghi ) nh ngo

vao cua SDRAM canh tiep theo cua Clock.

-Mot ngat ghi khoi d lieu (ap dung cho ca trng hp lenh oc co t ong nap lai):

Bat ky lenh oc, ghi, hay ket thuc truyen ti mot Bank bat ky se ket thuc (dng)

viec ghi khoi ngay lap tc, d lieu tren chan DQ khi lenh th 2 c phat th ch do lenh

nay s dung.

Ngat ghi khoi vi lenh precharge (en cung mot Bank) th kha phc tap. o la thi

gian viet nho nhat, twr phai c lt qua gia tac vu ghi sau cung ti 1 Bank (chu ky

khong b che (unmasked) cuoi cung cua ghi khoi) vi lenh precharge ke tiep, v vay mot

ghi khoi se b dng (huy) bi lenh tch nap (pre-charge) neu co u chu ky keo dai c

che i (dung DQM) e tao twr can thet. Mot lenh ghi vi s tch nap t ong cha ng

mot tr hoan t ong.

-Ngat mot lenh tch nap t ong:

Viec x ly s gian oan cua thao tac oc, ghi vi che o tch nap t ong la mot ac

tnh la chon cua SDRAM, va c ho tr rat nhieu. Neu c s dung, s tch nap (sau

khi mot s oc) hay thi gian ch twr theo sau bi s tch nap (sau khi oc) bat au cung

mot chu ky nh mot lenh ngat.

-Sap xep truyen khoi SDRAM:

Mot bo vi x ly hien ai co bo em noi chung se truy nhap bo nh trong nhng n

v cua line bo em. V du e truyen 64byte, line bo em yeu cau 8 s truy cap lien tiep ti

mot DIMM(dual in-line memory module: module nh co hai hang chan) 64bit, ma toan bo

co the c kch khi bi mot lenh n oc hay ghi tuy vao s cau hnh cac chp SDRAM

S truy cap line em ien hnh c kch khi bi mot s oc t mot a ch ac

biet, va SDRAM cho phep " t co tnh chat quyet nh " cua line em se c truyen au



Trang 19

tien. ("t " ay co ngha la chieu rong (cua) chp SDRAM hay DIMM, 64 bt vi mot

DIMM tieu bieu.).

Chp SDRAM ho tr hai giao thc e sap xep cac t con lai trong line em:

+ Che o truyen khoi an xen: lam cho cac tnh toan cua con ngi them phc tap

nhng lai de dang tong hp phan cng hn va c u tien vi cac bo vi x ly Intel. Ta

khong s dung kieu truyen nay.

+ Che o truyen khoi tuan t: nhng t tre hn c truy cap trong viec tang dan a

ch, khi ket thuc th quay tr lai iem bat au khoi. Chang han, vi mot tuyen khoi co

chieu dai la 4, va a ch cot c yeu cau la 5, nhng t se truy cap theo th t 5-6-7-4.

Neu chieu dai truyen khoi la 8, th t truy cap la 5-6-7-0-1-2-3-4. ieu nay c thc

hien bi viec them mot bo em a ch cot, va bo qua so nh khi i het khoi.

Ta co the la chon chieu dai khoi va kieu truy cap khoi bang cach s dung che o

thanh ghi c mo ta phan tiep theo

-Che o thanh ghi cua SDRAM:

Toc o d lieu n SDRAM co mot che o thanh ghi 10 bt n lap trnh c. Sau

o chuan SDRAM toc o d lieu kep SDRAM bo sung them che o thanh ghi, nh a ch

s dung nhng chan a ch Bank. Vi SDR SDRAM, chan a ch Bank va a ch hang

A[10] va cao hn th c l i, nhng phai la 0 trong khi che o ghi vao thanh ghi.

Trong chu ky cua che o thanh ghi th cac gia tr nap vao M[9:0] chnh la cac bit a ch.

M[9] che o ghi tng khoi, mc 0 th ghi s dung che o va chieu dai truyen khoi

che o oc, mc 1 th tat ca cac ghi khong phai la truyen khoi(nh v n)

M[8:7] che o van hanh, muon che o lu tr th at gia tr 00.

M[6:4] ngam nh CAS ch vi cac gia tr hp le la 010 (CL2) va 011 (CL3). Ch ra

so chu ky gia lenh oc va d lieu c gi ra t Chip. Chip se hoan thanh mot gii han

c ban trong nano-giay da tren gia tr nay; khi khi tao, bo ieu khien bo nh phai s

dung kien thc cua no ve tan so xung Clock va dch gii han kia thanh nhng chu trnh.

M[3] kieu truy cap cac t trong khoi : 0 th truy cap tuan t, 1 th truy cap an xen.



Trang 20

M[2:0]: chieu dai khoi: gia tr 000, 001, 010 va 011 ch ra kch thc khoi tng

ng la 1, 2, 4 hay 8 t. Moi oc ( va viet, neu m[9] la 0) se thc hien nhieu s truy cap, tr

phi c gian oan bi mot s dng (huy) truyen khoi hay cac lenh khac. Gia tr 111 ac

ta khoi vi ay u hang (full-row Burst hoac con goi la full page Burst). S truyen khoi

vi ay u hang ch c cho phep vi kieu tuan t. oi vi SDRAM IS42S16400 th

chieu dai cua 1 khoi che o full page Burst la 256 t. S truyen khoi th tiep tuc cho

en khi co ngat

-Lam ti t ong:

Dung e lam ti lai Chip ram nh vao s m va ong ( kch hoat va tch nap ) tng

hang trong tng Bank. Tuy nhien, e n gian hoa chp ieu khien bo nh, Chip SDRAM

ho tr lenh t ong lam ti, tc la ong thi thc hien thao tac nay ti mot hang trong

tng Bank. SDRAM cung duy tr mot bo em noi c lap lai tren toan bo cac hang co

the. Chip ieu khien bo nh th n gian phai phat ra u so lng cac lenh lam ti t

ong (1 lenh oi vi 1 hang ) vi moi khoang lam ti (mot gia tr chung la tref = 64 ms).

Tat ca cac Bank phai trang thai IDE khi lenh c phat.

-Che o Lower Power:

Nh a e cap, ngo vao cho phep xung Clock (CKE) co the c dung e dng xung

Clock ti SDRAM. Gia tr ngo vao CKE c xet tai tng canh len cua xung Clock, va

neu mc thap, th moi canh len cua xung Clock tiep theo se b bo qua moi muc ch

khac so vi viec kiem tra CKE.

Neu CKE xuong thap trong khi SDRAM ang thc hien tac vu, th no n gian ch la

ong bang lai tai cho cho en khi CKE len mc cao.

Neu SDRAM trang thai IDE ( tat ca cac Bank c tch nap , khong co lenh nao

ang hoat ong) khi CKE xuong thap, SDRAM t ong chon che o power-down(tiet

kiem nang lng), gi nang lng cc tieu cho tieu khi co canh len cua CKE. Khoang

nay th khong c dai hn gia tr toi a khoang lam ti tref, neu khong nhng g bo nh

cha ng se b mat. ay la phng phap e dng toan bo xung Clock trong khoang thi

gian nay e tiet kiem nang lng.



Trang 21

Cuoi cung, neu CKE mc thap vao luc mot lenh lam ti t ong c gi en

SDRAM, SDRAM chon che o t lam ti ( seft-refresh mode). Tng t Power Down,

nhng SDRAM dung mot timer noi e phat ra cac chu ky lam ti noi khi can thet. Trong

thi gian nay th dng xung Clock. Che o t lam ti tieu thu t nang lng hn so vi

che o Power Down,nhng van cho phep bo ieu khien bo nh disable toan bo.


Chng 2: Ly thuyet X ly anh

Trang 22

CHNG 2 : LY THUYET X LY ANH

2.1 GII THIEU

X ly anh so co nhieu ng dung thc te. Mot trong nhng ng dung sm nhat la vao

nam 1964 a s dung may tnh x ly thanh cong anh chup mat trang do ve tinh gi ve. He

thong chup hnh gan tren ve tinh th b han che ve kch thc va trong lng, do o anh

nhan c thng b m, meo hnh hoc va nhieu nen.

Cac phng phap x ly anh bat nguon t hai ng dung:

Nang cao chat lng thong tin hnh anh oi vi mat ngi.

X ly so lieu cho may t ong.

T o en nay, pham vi x ly anh ln manh khong ngng va c ng dung trong

hau het cac lnh vc (truyen anh, truyen ch, truyen hnh, nhan dang ch viet va van tay,

may cat lp trong y hoc, vien tham, quan s, noi vu, nghien cu khoa hoc, ). Ta co the

dung x ly anh e nen d lieu anh nham tiet kiem dung lng bo nh va tan dung hieu

qua kenh truyen.

X ly anh so co the chia lam bon lnh vc, tuy thuoc vao loai cong viec. o la cai

thien anh, phuc hoi anh, ma hoa anh, va ly giai noi dung (understanding) anh.

Cai thien: nang cao o tng phan, loc nhieu, lam trn anh e ngi xem, nh trong

truyen hnh, chuan oan y hoc, phan tch be mat trong vien tham, thien van hoac la c

x ly trc e tr giup hoat ong cua may moc, nh trong nhan dang oi tng bi may

moc.

Phuc hoi: anh b xuong cap trong mot so trng hp, chang han nh b nhoe,va muc

ch la e giam bt hoac loai bo han anh hng s xuong cap. Muc ch cuoi cung la tao

ra anh sau x ly giong nh anh ban au

Ma hoa: muc ch la bieu dien anh vi mot so t bt nhat trong ieu kien chat lng

anh va o ro chap nhan c cho tng ng dung cu the, chang han nh hoi ngh video,

truyen hnh, lu tr va truyen thong



Trang 23

Ly giai anh: au vao la anh, muc ch la dien at noi dung anh bang mot he ky

hieu nao o. Nhng ng dung cua ly giai anh bao gom th giac may tnh, ky thuat robot va

nhan dang muc tieu. Ly giai anh khac vi ba lnh vc khac cua x ly anh mot kha canh

chnh: au ra thng la mot bieu dien bang k hieu noi dung cua anh au vao. S phat

trien thanh cong cua cac he thong trong lnh vc nay can en ca x ly tn hieu va nhng

khai niem tr tue nhan tao.

He thong x ly anh so bao gom mot pham vi rong cac kien thc ve phan cng, phan

mem va c s ly thuyet.

Cac bc c ban cua x ly anh so c mo ta trong s o di ay:

Hnh 2.1 : Cac bc c ban cua x ly anh so

Thu thap anh(image acquision) : Anh so c thu thap bang mot cam bien

anh co kha nang bien thong tin ve cng o sang va mc xam cua anh thc thanh tn hieu

ien ap di dang analog. Tn hieu nay sau o c so hoa e tr thanh tn hieu so.

Hien nay co mot so cam bien anh thc hien ca viec thu nhan tn hieu ve cng o

sang cua anh va so hoa tn hieu. Trong trng hp cam bien khong co chc nang so hoa th

can phai co mot bo bien oi anh tng t thanh anh so (video decoder). Tn hieu anh sau

khi c so hoa con c ma hoa theo nhng chuan video (video format) nhat nh

trc khi c a vao qua trnh lu tr va x ly. Cac chuan video thng gap nh IUT-

R-BT 656, 601...



Trang 24

Tien x ly anh : Sau khi anh so c thu thap di dang tn hieu so, can phai trai

qua giai oan tien x ly. Chc nang chu yeu cua tien x ly la cai thien anh, nang cao

cac tnh chat cua anh giup cho cac qua trnh x ly ve sau c thuan tien hn. Cac cong

oan c ban cua tien x ly la : nang cao o tng phan, loc nhieu...

Phan vung anh: Bc tiep theo cua qua trnh x ly la phan vung anh. Anh sau khi a

c cai thien, se tr nen thuan tien hn cho viec phan ngng va phan vung. Nhiem vu

chnh cua phan ngng va phan vung anh la tach anh au vao thanh cac oi tng, vat the

rieng biet. Ket qua cua qua trnh phan vung anh, ta se c mot tap hp cac iem anh co

lien ket vi nhau thanh cac oi tng, c anh so phan biet, thuan tien cho cac

qua trnh x ly cao hn.

au ra cua qua trnh phan vung anh la cac pixel cha c loc, bao gom lien ket cua

1 vung hoac tat ca cac iem anh trong vung o. So lieu nay can c bien oi thanh dang

thch hp cho may tnh x ly.

Phan tch anh: ay la giai oan x ly bac cao trong he thong x ly anh so. Anh sau

khi c phan vung thanh cac oi tng rieng biet, a c anh so phan biet, se c

phan tch e phuc vu nhng muc ch khac nhau nh:

Xac nh cac ac trng hnh hoc cua oi tng: da tren c s oi tng a c

xac nh va phan biet, ta co the thc hien xac nh cac ac trng hnh hoc cua moi

oi tng ay, nh : v tr, kch thc, hng, ... va so oi tng hay mat o oi tng

trong anh. ay la cac ac trng c dung nhieu trong he thong th giac may

(machine vision)

Nhan dang : cac oi tng co the la cac vat the co hnh dang nhat nh, hoac cac k

t so, ch cai, dau van tay...Anh sau khi c phan vung co the c nhan dang theo

nhng phng phap nhat nh nh phng phap neural, e tm ra mau hnh dang ma

oi tng o thuoc ve.

e hng dan hoat ong cua tng module x ly, can co mot he c s kien thc e

kiem tra hoat ong va tng tac gia cac module. He nay co nhiem vu kiem soat hoat

ong cua tng module va sap xep trnh t hoat ong cua chung trong tng thi iem, giai

quyet bai toan xung ot



Trang 25

2.2 CAC THUAT TOAN X LY ANH SO

2.2.1 TOAN T CA SO (WINDOWING OPERATOR)

Trong viec thc thi cac thuat toan x ly anh so c ban, ngi ta thng s dung mot

toan t ac biet goi la toan t ca so. Toan t ca so la mot tap hp co hnh dang nhat

nh, gom cac pixel co lien ket vi mot pixel trung tam, la pixel ang c x ly. Cac

phep toan tren cac pixel nay se co anh hng en cac pixel trung tam cung la cac pixel

ang c x ly trong mot thuat toan x ly anh.

Toan t ca so co nhieu hnh dang, tuy thuoc vao thuat toan thc hien. Tuy nhien

thng dung nhat la cac toan t co dang hnh vuong vi cac canh la mot so le, v du :3x3,

5x5, 7x7....Trong o an nay, chung em s dung thng xuyen toan t ca so co dang 3x3,

v ay la kch thc hp ly e thc hien hieu qua tat ca cac thuat toan x ly c ban va

nang cao, ong thi lai de thc hien va rut ngan toi a qua trnh x ly. Neu s dung ca so

5x5 va 7x7, thi gian x ly se tang len rat nhieu.

2.2.2 NHAN CHAP (CONVOLUTION)

Nhan chap khong phai la mot thuat toan x ly anh, ma ch la phep toan thong dung

trong cac thuat toan x ly anh s dung toan t ca so. Nhan chap c s dung trong

cac bai toan do bien (edge detection) va loc tuyen tnh (linear filter).

Nhan chap tnh toan ra gia tr mi cua pixel trung tam cua toan t ca so, bang cach

thc hien phep tnh vi cac pixel lan can va chnh pixel trung tam.

Viec thc thi phep nhan chap nh sau: cho mot ca so vi pixel trung tam chay tren

toan bo frame anh, vi moi ca so 3x3 thu c, ta thc hien phep toan:

j+1i+1

n = i-1 m = j-1

I(i,j) = c(n,m). I(n,m)

Ket qua tnh c cho ra gia tr mi cua pixel trung tam. Trong bieu thc, c(n,m) la

cac phan t cua mot ma tran goi la mat na (mask). Moi thuat toan x ly khac nhau s

dung mot mat na khac nhau e tnh gia tr cua cac iem anh.

Hai thuat toan c s s dung phep nhan chap la loc tuyen tnh, do bien



Trang 26

2.2.3 LOC TUYEN TNH(LINEAR FILTER)

Co tac dung cai thien anh, loai bo nhieu ho tr cho cac qua trnh x ly cao hn. Moi

bo loc khac nhau s dung mot mat na khac nhau, cho hieu qua khac nhau tuy vao muc

ch s dung va tnh trang cua anh sau khi thu thap. V du oi vi anh co nhieu phan bo

eu, ngau nhien oc lap vi moi pixel, ta co the s dung mat na danh cho loc trung bnh,

mat na nay se lam giam anh hng cua nhieu oi vi pixel trung tam bang cach lay trung

bnh cong cac pixel lan can trong ca so.

11 12 13

21 22 23

31 32 33

c c c 1 2 11

c = c c c = 2 4 29

c c c 1 2 1

;

Neu anh co nhieu Gaussian, ta s dung mat na:

11 12 13

21 22 23

31 32 33

c c c 1 2 11

c = c c c = 2 4 29

c c c 1 2 1

;

2.2.4 DO BIEN

a) Khai niem ve bien: Bien cua mot oi tng c xac nh ni mc xam cua cac

pixel co s thay oi ot ngot. Tap hp cac iem bien tao thanh bien hay ng bao cua

anh (boundary).

Mo hnh bieu dien ng bien: theo toan hoc, iem anh co s bien oi mc xam

u(x) mot cach ot ngot theo hnh di.

Hnh 2.2 ng bao cua anh



Trang 27

Nh vay, phat hien bien mot cach ly tng la xac nh c tat ca cac ng bao

trong cac oi tng. nh ngha tren la c s cho cac ky thuat phat hien bien. ieu quan

trong la s bien thien mc xam gia cac iem anh trong mot vung thng la nho, trong

khi o bien thien mc xam cua iem vung giap ranh (khi qua bien) lai la kha ln.

b) cac ky thuat phat hien bien:

T nh ngha toan hoc cua bien ngi ta s dung hai phng phap chnh e phat

hien bien nh sau:

Phng phap phat hien bien trc tiep: phng phap nay chu yeu da vao s bien

thien o sang cua iem anh e lam noi bien bang ky thuat ao ham: phng phap

Gradient th lay ao ham bac nhat cua anh, phng phap Laplace th ay ao ham bac hai

cua anh. Hai phng phap nay c goi chung la phng phap do bien cuc bo.

Ngoai ra, ngi ta con s dung phng phap i theo ng bao da vao cong cu

toan hoc la nguyen ly quy hoach ong va c goi la phng phap do bien tong the.

Phng phap do bien trc tiep co hieu qua va t b tac ong cua nhieu.

Phng phap phat hien bien gian tiep: Neu bang cach nao ay, chung ta thu c

cac vung anh khac nhau th ng phan cach gia cac vung o chnh la bien. Tc laviec

xac nh ng bao cua anh c thc hien t anh a c phan vung. Phng phap do

bien gian tiep kho cai at nhng ap dung tot khi s bien thien o sang nho.

Trong khuon kho luan van ta dung phng phap Gradient e phat hien bien s dung

mat na loc Prewitt nh sau:

nh ngha: Gradient la mot vec t f(x, y) co cac thanh phan bieu th toc o thay oi

mc xam cua iem anh (theo hai hng x, y trong boi canh x ly anh hai chieu) tc:

Trong o dx, dy la khoang cach gia 2 iem ke can theo hng x, y tng ng (thc

te chon dx= dy=1). ay la phng phap da theo ao ham rieng bac nhat theo hng x, y.



Trang 28

Vi mot anh lien tuc f(x,y), cac ao ham rieng cua no cho phep xac nh v tr cc

ai cuc bo theo hng cua bien. Thc vay, gradient cua mot anh lien tuc, c bieu dien

bi mot ham f(x,y), doc theo r vi goc r , c nh ngha bi:

' '( , ) cos sinx ydf r f dx f dy

f fdr x dr y dr

( , )f r at cc ai khi ( , )df r

dr

= 0; tc

' 'cos sinx yf f = 0; t o ta xac nh c

hng cc ai:

Ky thuat Gradient: Theo nh ngha ve Gradient, neu ap dung no vao x ly anh,

viec tnh toan se rat phc tap. e n gian ma khong mat tnh chat cua phng phap

Gradient, ngi ta s dung ky thuat Gradient dung cap mat na H1, H2 trc giao (theo 2

hng vuong goc). Neu nh ngha g1, g2 la Gradient theo hai hng x, y tng ng th

bien o g(m,n) tai iem (m,n) c tnh:

2 21 2 0( , ) ( , ) ( , )g m n g m n g m n A

2( , ) ( ( , ))r m n artg g m n

Mot so toan t Gradient tieu bieu:toan t Robert, Sobel, Prewitt, ang hng

(Isometric), 4-lan can nh di ay:

Toan t Robert (1965).

Robert ap dung cong thc tnh Gradient tai iem (x, y). Vi moi iem anh I(x,y) ao ham

theo x, y c ky hieu tng ng:

xg = I(x+1,y) - I(x,y)

yg = I(x,y+1) - I(x,y)



Trang 29

Cong thc tren c cu the hoa vi cap mat na theo chieu x, y tng ng(mat na Robert):

1

0 1

1 0H

va

2

1 0

0 1H

Chu y la cac ky thuat tren thc s ch la mo phong va xap x ao ham bang ky thuat

nhan chap do anh so la tn hieu ri rac, do vay ao ham thc s khong ton tai.

Vi ky thuat Sobel va Prewitt, ta s dung cap mat na:

H x =

1 0 1

2 0 2

1 0 1

H y =

1 2 1

0 0 0

1 2 1

Gradient c xap x bi cong thc:

x xG H I va y yG H I

Thc te cho thay toan t Sobel va Prewitt tot hn toan t Robert do t nhay cam vi

nhieu hn. Viec lay ao ham mot tn hieu co xu hng lam tang nhieu trong tn hieu o.

o nhay cam nay co the giam bt bang thao tac lay trung bnh cuc bo trong mien phu bi

mat na.


Chng 3: C che hien th hnh anh len monitor

Trang 30

CHNG 3: C CHE HIEN TH HNH ANH LEN MONITOR

3.1 NGUYEN TAC CHUNG

e hien th hnh anh ra man hnh c tch hp th can phai co mot bo VGA

Generator vi cac tn hieu va c che lam viec nh sau:

3.1.1 VGA COLOR SIGNALS

Co 3 tn hieu color la: red, green va blue gi tn hieu mau sac (color information)

en man hnh VGA. Moi mot tn hieu ieu khien mot sung ban ien t (electron gun)

e phong cac hat electron ve len mot mau c ban tai mot iem tren man hnh. Dai

cua tn hieu nam t t 0 V (tng ng vi mau toi hoan toan) va 0.7V (sang hoan toan)

ieu khien cng o cua moi thanh phan mau va 3 thanh phan mau ket hp vi nhau

tao len mau cua iem anh (dot) hay phan t anh (pixel) tren man hnh.

Hnh 3.1 : VGA Connection

Tuy vao o rong A bit cua tn hieu mau ngo vao tn ma moi mau analog ngo ra

la mot trong 2A mc vi bo chuyen oi digital to analog A bit. 3 tn hieu analog ket

hp vi nhau tao nen phan t anh (pixel) vi 2A 2A 2A = 32 A mau khac nhau.

3.1.2. VGA SIGNAL TIMING

Moi mot anh (hay frame) tren man hnh hien th la ket hp cua h dong, moi

dong co w pixel. Kch thc cua moi frame c bieu dien w x h di cac dang tieu

bieu gom 640 x 480m 800 x 600, 1024 x 768 va 1280 x 1024.



Trang 31

Hnh 3.2 : CRT Display Timing Example

e ve mot frame, co nhng mach ien co trach nhiem di chuyen dong

electron t trai sang phai va t tren xuong di doc theo man hnh goi la deflection

circuit. Nhng mach nay yeu cau phai co 2 tn hieu ong bo e khi ong va dng

dong electron tai ung thi iem e cho mot dong cac iem anh c ve doc theo

man hnh va moi dong c ien theo c che t tren xuong di e tao len mot anh.

3.1.3 NGUYEN TAC HOAT ONG CUA VGA GENERATOR

He thong ben ngoai ghi gia tr pixel vao trong thanh ghi pixel (data register) .

Noi dung cua thanh ghi nay c dch sau moi xung clock e thay the pixel hien tai.

Cac bit nay c gi en bo DAC e chuyen sang dang tn hieu mau analog. Roi kiem

tra xem gia tr tren chan Blank e xuat ra cong VGA.

Hai mach tao xung ong bo (pulse generation circuit) c dung e tao cac xung

ong bo do c (VSYNC) va ngang (HSYNC). Bo hirizontal sync generator co au ra la

tn hieu gate mot chu k trung khp vi sn len cua xung ong bo ngang ( horizontal

sync pulse), tn hieu gate nay noi vi tn hieu clock-enable cua bo vertical sync

generator v the nen clock-enable ch cap nhat bo em thi gian sau moi dong pixel



Trang 32

(line of pixels). Tn hieu gate cua vertical sync generator c dung nh tn hieu bao

ket thuc mot frame, ong thi no cung reset va xoa toan bo noi dung cua pixel buffer

nen bo VGA generator luon khi ong t trang thai xoa sach hoan toan vi moi frame.

Bo tao tn hieu ong bo cung tao ra cac tn hieu horizontal va vertical

blanking. Khi dung phep toan OR logic ta c tn hieu blanking toan cuc.

3.2 BO VGA DAC ADV7123

Kit DE2 tch hp mot bo VGA DAC la ADV7123 vi cau truc:

Ho tr tn hieu mau 10 bit ngo vao, vi bo DAC 10 bit se cho ra 102 mc mau

Analog ngo ra, tuy nhien trong thiet ke d lieu mau ta cung cap cho ADV7181 ch la 8

bit nen tn hieu mau Analog ngo ra co 82 mc. 3 tn hieu analog ket hp lai vi nhau tao

nen phan t anh 242 (16 trieu ) mau.

Cac tn hieu ong bo la SYNC va BLANK: gia tr cua SYNC th khong anh hng

en qua trnh hien th, BLANK vi gia tr 0 th chot cac d lieu mau ngo vao.

Hnh 3.3: S o cau truc cua ADV7123

cac chan cua ngo ra c noi tng ng vi cac chan cua cong VGA tren KIT

DE2, v vay e s dung c bo VGA DAC nay ta phai tao ra mot khoi va cung cap cac

tn hieu BLANK, Red, Green, Blue cho ADV7123 va phai tao ra 2 tn hieu ong bo

VSYN va HSYNC noi trc tiep vao cong VGA mot cach ong thi.


Chng 4: S lc he thong

Trang 33

PHAN II: THIET KE HE THONG

CHNG 4: S LC HE THONG

4.1. YEU CAU

Tm hieu ve cac giai thuat x ly anh.

ng dung giai thuat x ly anh video vao phan cng, cu the la mo ta phan cng

thc hien giai thuat bang ngon ng Verilog HDL.

ng dung FPGAs e kiem tra ket qua, ong thi so sanh vi ket qua vi hnh anh

video ban au.

4.2 NOI DUNG THC HIEN

Lay nguon tn hieu video t DVD ( VCD ) Player a vao kit DE2 cua Altera qua

cong TV-IN.

S dung phan mem Quartus II cua Altera e viet chng trnh bang ngon ng

Verilog HDL va giao tiep vi kit DE2.

Thiet ke khoi loc trung bnh va do bien cho anh ngo ra bang Verilog HDL.

Giao tiep vi ADV7181B, VGA, SDRAM tren kit DE2.

Hien th ket qua len Monitor va so sanh vi tn hieu goc



Trang 34

4.3 S O THIET KE VA NGUYEN LY HOAT ONG

4.3.1 S O THIET KE

Hnh 4.1: S o he thong

4.3.2 NGUYEN LY HOAT ONG

Khoi I2C_Video_Config: vi giao thc giao tiep I2C se at gia tr cho cac thanh

ghi cua bo ma hoa ADV7181 e cau hnh hoat ong cho chip ma hoa nay.

Khi Timer tr hon ban u: Sau chuoi khi ong, ADV7181B ri vao thi k

khong on nh, khoi se phat hien thi k khong on nh nay roi tnh toan thi iem bat au

lam viec cua cac khoi khac.

Khoi Desize_Horizon: Lay ra chuoi lien tuc cac Pixel trong dong d lieu do

ADV7181B xuat ra ong thi nh lai kch thc frame anh t dang 720 x 480 sang chuan

VGA 640 x480.



Trang 35

SDRAM BUFFER: Nhan d lieu va tn hieu ieu khien ghi t khoi Desize Horizon

e ghi gia tr cac Pixel vao SDRAM, ong thi cung nhan tn hieu t VGA controller e

ieu khien viec xuat d lieu, a ch phu hp (xuat xen ke cac line thuoc Odd field va

Even field)

Khoi x ly anh YUV: X ly d lieu anh nhan c t SDRAM BUFFER roi xuat ra

d lieu anh cho khoi Convert YUV to RGB

Khoi ConvertYUVtoRGB: ADV7181B xuat ra anh video dang YUV, e co the

hien th len VGA th trc tien chuyen oi thanh dang RGB.

Khoi VGA_Controller: Nhan d lieu anh RGB t khoi ConvertYUVtoRGB e xuat

d lieu va tn hieu ong bo cho Video DAC 7123, ong thi cung phat ra cac tn hieu ieu

khien SDRAM_BUFFER e xuat d lieu t SDRAM.


Chng 5: Khoi I2C_Video_Config

Trang 36

PHAN III: NOI DUNG THIET KE

CHNG 5: Khoi I2C_VIDEO_CONFIG

5.1 S O KHOI

Hnh 5.1: S o khoi I2C_Video_Config

Ten Mo ta

ICLK Xung Clock 50MHz t Kit DE2

RESET Tn hieu Reset he thong

I2C_SCLK Ngo ra cha xung Clock cung cap cho ADV7181B

I2C_DATA Port 2 chieu e cau hnh gia tr cac thanh ghi cua

ADV7181B

Hnh 5.2: Dang song e truyen d lieu va cau truc ghi vi giao thc I2C



Trang 37

5.2 LU O GIAI THUAT:

5.3 MO TA

Vai tro cua khoi ch la ghi gia tr vao cac thanh ghi cua ADV7181B nen co the chon

xung clock lam viec cua khoi la 20KHz nh vao bo chia tan t tan so 50MHz. a ch

Slaver cua ADV7181B la 40h nen ta s dung cach gan mI2C_DATA


Trang 38

always@(posedge mI2C_CTRL_CLK or negedge iRST_N)

begin

if(!iRST_N) begin

LUT_INDEX


Trang 39

// Tang LUT_INDEX len 1 e nhay en thanh ghi mi roi quay ve

trang thai 0

LUT_INDEX


Trang 40

6'd9 : SDO=SD[17];

6'd10 : SDO=SD[16];

//Tha noi ng truyen e nhap ACK t ADV7181B qua Port 2 chieu I2C_DATA

6'd11 : SDO=1'bz;

//a ch thanh ghi can nap

6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end

6'd13 : SDO=SD[14];

6'd14 : SDO=SD[13];

6'd15 : SDO=SD[12];

6'd16 : SDO=SD[11];

6'd17 : SDO=SD[10];

6'd18 : SDO=SD[9];

6'd19 : SDO=SD[8];

// Tha noi ng truyen nhap e ACK t ADV7181B qua Port 2 chieu I2C_DATA

6'd20 : SDO=1'bz;

//Gia tr can ghi vao thanh ghi

6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end

6'd22 : SDO=SD[6];

6'd23 : SDO=SD[5];

6'd24 : SDO=SD[4];

6'd25 : SDO=SD[3];

6'd26 : SDO=SD[2];

6'd27 : SDO=SD[1];

6'd28 : SDO=SD[0];

// Tha noi ng truyen nhap ACK t ADV7181B qua Port 2 chieu I2C_DATA

6'd29 : SDO=1'bz;

//Thiet lap c STOP va bao ket thuc chuoi

6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end

6'd31 : SCLK=1'b1;

6'd32 : begin SDO=1'b1; END=1; end

endcase

Trong o SD_COUNTER thc hien em t 0 -> 63, nh vay viec nap cho mot thanh

ghi ch thc hien trong 33 chu ky au con 30 chu ky sau th Bus trang thai IDE (SCLK =



Trang 41

1 va SDO = 1) e ch chu ky ghi tiep theo. ong thi e am bao c yeu cau ve dang

song tren chan I2C_SCLK va xac nhan (ACK) a nap xong thanh ghi, ta thc hien:

wire I2C_SCLK = SCLK | ( ( (SD_COUNTER >= 4) & (SD_COUNTER

Chng 6: Khoi Timer tr hoan ban au

Trang 42

CHNG 6: KHOI TIMER TR HOAN BAN AU

6.1 S O KHOI

Hnh 6.1: S o cua khoi Timer tr hoan ban au

Ten Mo ta

ICLK Xung clock 50Mhz t kit DE2

VS Tn hieu VS ( Vertical Sync ) t ADV7181B

HS Tn hieu HS (Horizontal Sync) t ADV7181B

TD_Stable Bao hieu ADV7181b a hoat ong on nh

RST0, RST1, RST3 Ngo ra cho phep cac khoi khac bat au lam viec

6.2 MO TA

Vi cau hnh a cai at phan trc, khi a hoat ong on nh, dang song do

ADV7181B phat ra nh sau:

V vay e phat hien xem chip ma hoa nay a hoat ong on nh hay cha khoi

TD_DETEC tien hanh kiem tra ieu kien: VS mc cao trong 9 chu ky lien tiep cua HS

roi chuyen xuong mc thap, neu thoa man th a TD_Stable len mc cao. Khi tn hieu

TD_Stable len mc cao, khoi RESET_DELAY bat au em len theo xung nhip cua ICLK


Chng 6: Khoi Timer tr hoan ban au

Trang 43

(50MHz) e tnh thi iem xuat ra mc 1 tren cac chan RST0, RST1, RST2. Cac tn hieu

nay dung e khi ong cac khoi khac theo trnh t nh sau:

1) Ban au th xoa tat ca d lieu trong cac khoi.

2) Tnh t thi iem TD_Stable len 1(dn v la chu ky clock 27MHz) :

Sau 1132461.5: tch cc RST0 e kch hoat khoi SDRAM BUFFER,

Sau 1698692.5: tch cc RST1 e kch hoat khoi Desize Horizon

Sau 2264923.5: tch cc RST2 e kch hoat khoi x ly anh YUV vaVGA Controller.

3) Gi nguyen gia tr ngo ra cho en khi co tn hieu RESET he thong th lap lai.

iem can chu y ay la khi Desize Horizon hoat ong th se xuat

DATA_VALID cho phep ghi d lieu vao SDRAM BUFFER. Roi phai ch 1 khoang thi

gian e ghi u so d lieu can thiet mi kch hoat VGA Controller e xuat d lieu t

SDRAM BUFFER. Nh ta a biet 1 frame anh do ADV7181B xuat ra bao gom 900900

byte (525 line, moi line co 1716 byte) hay e truyen het 1 frame se mat 900900 chu ky.

Do xung clock tren chan LLC e truyen cac byte la 27 MHz nen ta kiem tra lai cac thi

iem nay nh sau:

Lay goc thi gian la khi bat au frame au tien

TD_Stable len 1 khi Frame au tien a phat c 9 line: 9 x 1716 = 15444 chu ky.

Frame th 3 c bat au tai thi iem 2 x 900900 = 1801800

Khoi Desize Horizon c kch hoat tai thi iem 1714136.5 (= 15444 + 1698692.5)

tc la trc khi frame th 3 bat au. am bao rang khoi se xuat ra DATA_VALID = 1

toan bo cac Active Pixel cua frame th 3.

Khoi VGA controller c kch hoat tai thi iem 2280367.5 (=15444 + 2264923.5)

nen oRequest c xuat ra tai thi iem 2315727.5 (= 2280376.5 + 35360 ). Vi 35360

chu ky la khoang thi gian t khi khoi c reset cho en khi oRequest len 1. Vay viec

oc t SDRAM BUFFER c kch hoat khi frame th 3 a bat au c 1 khoang thi

gian la 513927.5 (= 2315727.5 - 1801800). ieu nay am bao cho viec xuat ra ung tng

frame t SDRAM BUFFER ma ta se e cap ky hn phan mo ta SDRAM BUFFER.

Cau truc va thiet ke cua khoi nay tng oi n gian nen ta khong a lu o giai

thuat va code thc thi ma ch mo ta s lc.


Chng 7: Khoi Desize Horizon

Trang 44

CHNG 7: KHOI DESIZE_HORIZON

7.1 S O KHOI

Hnh 7.1: S o cua khoi Desize Horizontal

Ten Mo ta

CLK_27 Xung clock 27Mhz t kit DE2

RST_N Reset he thong

TD_DATA[7:0] D lieu hnh anh t ADV7181B

ACLR Tn hieu xoa bat ong bo do khoi Timer tr hoan cung cap

CLK Xung clock 27MHz t chan TD_CLK cua ADV7181B

So chia = 9 So chia cung cap cho bo chia do ngi thiet ke nhap vao

TV_X[9:0] V tr cua Pixel trong hang hien hanh ong thi cung la so

b chia cung cap cho bo chia

Thng [9:0] Thng cua phep chia TV_X cho 9

So d [9:0] So d cua phep chia TV_X cho 9

DATA_VALID ong bo cho oYCbCr e a vao SDRAM_Controller

oYCbCr[15:0] Chuoi d lieu anh ngo ra

DATA_VALID: mc 1 th se cho phep Pixel i kem c ghi vao SDRAM thong

qua SDRAM_Controller. Do frame ma ADV7181B xuat ra co dang 720x480 e a ve

chuan 640x480 ma hnh anh khong b xen th vi moi 9 pixel lien tiep ta se loai bo Pixel



Trang 45

au tien: khong cho phep ghi vao SDRAM bang cach a DATA_VALID xuong mc 0

(lay ra 8 Pixel trong 9 Pixel : 8

640 7209

)

ong thi e am bao c chuoi a vao SDRAM_controller van co dang chuoi

CbYnCrYn+1 lien tiep th phai hoan oi gia 2 thanh phan Cb va Cr c sau 2 lan loai bo 1

Pixel.

Hnh 7.2: V tr cac Pixel trong chuoi

Nh hnh tren X la v tr cac Pixel b loai bo (b bo qua khi hien th len man hnh),

khi o chuoi Pixel tai S1 la Cb4Y8Cb5 Y10 va tai E1 la Cr8Y17Cr9Y19 v vay e am bao

chuoi ra co dang CbYCrY lien tiep th phai hoan oi v tr gia Cb va Cr trong khoang Cb5

Y10 .... Cr8Y17.



Trang 46

7.2 LU O GIAI THUAT



Trang 47

7.3 MO TA

TD_DATA la chuoi Pixel c phat ra theo chuan Video ITU656. Ta co the xem

mot frame thc s bat au vi Odd Field khi bit F (bit 6 trong Byte cuoi cua trng SAV

hay EAV) chuyen t 1 ve 0, vay e xet ieu kien bat au cua 1 frame ta phai i en

trng SAV hay EAV roi mi kiem tra gia tr cua bit F:

Window


Trang 48

Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom

mi, at ten la DIV; chon phan Arithmetic >> LPM_DEVIDE. V oTV_X 720 nen chon

o rong bit cua so b chia (Numerator) la 10, o rong bit cua so chia (denominator) la 4,

kieu d lieu khong dau. V so chia can nhap la 9 nen ta ghep vao khoi tong the nh sau:

DIV u5 ( .aclr(!DLY0),

.clock(TD_CLK),

.denom(4'h9),

.numer(TV_X),

.quotient(Quotient),

.remain(Remain));

Trong o quotient, remain la thng va so d, ta nhap cac ieu kien oTV_X co chia

het cho 9 vathng la so le thong qua cac chan iSkip va iSwap_CbCr bang cach khai bao:

Desize_Horizontal u4 ( .iTD_DATA(TD_DATA),

.oTV_X(TV_X),

.oYCbCr(YCbCr),

.oDVAL(TV_DVAL),

.iSwap_CbCr(Quotient[0]),

.iSkip(Remain==4'h0),

.iRST_N(DLY1),

.iCLK_27(TD_CLK) );

Sau o ghep 1 Y vi 1 Cr hay 1 Y vi 1 Cb ong thi hoan oi v tr cua Cr va Cb tai

cac v tr can thiet:

if(iSwap_CbCr)

begin

case(Cont[1:0]) //hoan oi Cb Va Cr

0: Cb


Trang 49

case(Cont[1:0]) // khong can hoan oi

0: Cb

Chng 8: Khoi SDRAM BUFFER

Trang 50

CHNG 8: KHOI SDRAM BUFFER

8.1 S O KHOI

Gom 2 khoi PLL va SDRAM Controller:

Hnh 8.1: S o cua khoi SDRAM BUFFER



Trang 51

Ten Mo ta

RESET Tn hieu Reset he thong

CLK_27 Xung clock 27Mhz t kit DE2

CLK

Xung clock 81MHz PLL a ra cho cac ngo vao CLK cua khoi

SDRAM Controller ( chnh la tan so oc cua SDRAM WRITE

FIFO, ghi cua SDRAM READ FIFO1 va SDRAM READ FIFO2)

SDR_CLK Xuat xung clock 81MHz cho SDRAM

WR_LOAD

RD1_LOAD

RD2_LOAD

Lan lt la tn hieu e xoa bat ong bo SDRAM WRITE FIFO,

SDRAM READ FIFO1 va SDRAM READ FIFO2 lay t chan

RST0 cua khoi Timer tr hoan ban au.

WR_DATA D lieu anh a vao SDRAM WRITE FIFO do Desize horizon cap

WR

Cho phep ghi vao SDRAM WRITE FIFO lay t chan

DATA_VALID cua khoi Desize horizon

WR_CLK Xung clock 27MHz t chan LLC(TD_CLK) cua ADV7181B

RD_WRFIFO Cho phep oc d lieu t SDRAM WRITE FIFO

WRITE_SIDE[8:0] So t (Word) hien co trong SDRAM WRITE FIFO

DATA_IN

D lieu t SDRAM WRITE FIFO a vao Control Center e ghi

SDRAM.

DATA_OUT[15:0]

D lieu Control Center oc t SDRAM e xuat ra ngoai qua 1

trong 2 FIFO: SDRAM READ FIFO1, SDRAM READ FIFO2

RD1

RD2

RD1 = ~ RD2: Lan lt cho phep oc d lieu t SDRAM READ

FIFO1, SDRAM READ FIFO2 vi s ieu khien cua khoi VGA

Cotroller thong qua chan Request va VGA_Y.

RD1_CLK

RD2_CLK

Tan so oc cua SDRAM READ FIFO1 va SDRAM READ FIFO2

c la 27MHz t KIT DE2

READ_SIDE1[8:0] So t (Word) hien co trong SDRAM READ FIFO1

READ_SIDE2[8:0] So t (Word) hien co trong SDRAM READ FIFO2

WR_RDFIFO1 Cho phep ghi d lieu SDRAM READ FIFO1

WR_RDFIFO2 Cho phep ghi d lieu SDRAM READ FIFO2

RD1_DATA[15:0]

RD2_DATA[15:0]

D lieu ngo ra cung cap cho khoi x ly anh YUV

Cac chan DQ[15:0], SA[11:0], CKE, CAS_N, RAS_N, SDR_CLK, WE_N, BA[1:0],

CS_N[1:0], DQM[1:0] th c noi tng ng vao chip SDRAM co san tren kit DE2.



Trang 52

8.2 LU O GAI THUAT

Lu o danh cho viec ghi va xuat tng khoi d lieu xen ke t SDRAM.



Trang 53

Lu o e xuat hoac ghi dong d lieu vao cac FIFO: ng vi tng thao tac oc hay

ghi tren ma ta co lu o giai thuat tao a ch truy cap SDRAM nh sau:

8.3 MO TA

Nh ta a biet 1 frame anh theo chuan ITU656 bao gom Odd Field va Even Field:

khi xuat ra man hnh th cac line thuoc Odd Field se c hien th hang le, con cac line

thuoc Even la hang chan. Nen cac line cua 2 Field nay phai c xuat xen ke nhau nhng

trong chuoi video ITU656 do ADV7181B xuat ra th 2 Field c xuat lien tuc: xuat xong

Odd Field roi mi ti Even Field (cac frame khi ghi vao SDRAM th thanh 2 Field lien



Trang 54

tuc) nen e xuat ra cac line xen ke th ta phai tuan t xuat 1 line t a ch ma Odd Field

c lu gi roi lai xuat tiep 1 line t a ch ma Even Field c lu gi.

D lieu trong mot frame anh se c ghi lan lt vao SDRAM t a ch 0 en a

ch 324480 (324480 = 640 x 507, 507 chnh la so line cua frame c ghi vao SDRAM ,ta

bo qua 18 line co bit V =1 ), luc nay phan d lieu can xuat ra t SDRAM chia thanh 2

phan (trong 1 frame theo chuan ITU656 thc s co ti 487 active line, ta xen bt 7 active

line e giam so line ve chuan hien th la 480):

Phan 1: T a ch 8320 (640 x 13) en 161920 (640 x 253) se la cac Pixel thuoc

Odd Field. ay chnh la 240 line t 23 en 262 trong frame goc.

Phan 2: T a ch 170880 (640 x 267) en 324480 (640 x 507) la cac Pixel thuoc

Even Fiel. ay chnh la 240 line t 286 en 525 trong frame goc.

SDRAM ho tr che o truy cap d lieu theo tng khoi (Burst) vi chieu dai khoi co

the thay oi c nh vao cai at gia tr 3 bit cuoi (BL) cua thanh ghi mode register bang

cach truy cap che o load mode roi nhap gia tr cho thanh ghi nay qua cac chan a ch:

ay ta oc va ghi theo tng khoi 128 Word 16 bit nen nhap BL = 111: chieu dai

cua Burst la full page (tc la 256 word vi viec s dung SDRAM di dang 4Mx16) ; WT

= 0: truy xuat tuan t (Sequential) d lieu trong khoi; LTMODE = 011: thi gian ch

(latency) cho tn hieu RAS la 3 chu ky;

Cac Burst d lieu cua 2 phan tren se c xuat xen ke nhau. Ta khi tao va truy

xuat a ch cho cua cac phan nay nh sau:

if(!RESET_N)

begin

rWR_ADDR


Trang 55

//chieu dai cua khoi can truy xuat

rWR_LENGTH


Trang 56

rRD1_ADDR Create tao mot

custom mi, at ten la SDRAM_PLL, chon phan I/O >> ALTCLKlLOCK, ta khong s

dung cac chan ong bo ma ch nhap cac thong so cho tan so ngo vao va tan so, pha ngo ra



Trang 57

nh sau :inclk0 la 27MHz; c0 chon tan so la 81MHz vi pha ban au la 0; c1 tan so la 81

MHz vi pha ban au tre 3ns (bu tr vi khang thi gian ieu khien cac tn hieu ong bo

e truy cap SDRAM).

Chan c0 se cung cap tan so oc tan cho SDRAM WRITE FIFO e ghi d lieu vao

SDRAM, tan so ghi cho SDRAM READ FIFO1 va SDRAM READ FIFO2 e ghi d lieu

c xuat ra t SDRAM. Chan c1 cung cap tan so lam viec cho SDRAM.

ong thi khi thc hien 1 tac vu ta can phai tr hoan cac tac vu khac mot khoang

thi gian c mo ta theo gian o sau (cha xet tac ong cua RD1 va RD2):

Hnh 8.2: Gian o nh th cho chu ky truy xuat gia SDRAM va cac FIFO

V vay e am bao truy xuat ung d lieu th can phai co cac FIFO co chieu dai 384

( tc la 128 x 3 ). Tuy nhien trong th vien cua Quarus ch khong co FIFO dai 384 Word

nen se tao mot FIFO dai 512 Word nh sau:

Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao mot

custom mi, at ten la SDRAM_WRITE_FIFO, chon phan Memory Compiler >> FIFO

chon o rong d lieu la 16bit, chieu dai ( deep ) la 512 Words. Lam tng t e tao cac

khoi SDRAM_READ_FIFO1 va SDRAM_READ_FIFO2.

Chu y la: Khi s dung FIFO dai 512 Word ta phai co 1 so thay oi trong thiet ke, tuy

nhien cac thay oi nay tng oi n gian nh tang tan so xung clock len 108 MHz, s

dung them 1 tac vu ghi trong (WR2) e am bao d lieu xuat ra ung theo yeu cau.

Thc hien ghi va xuat tng khoi d lieu xen ke t SDRAM nh sau:



Trang 58

// Ghi vao SDRAM READ FIFO1 cac Pixel thuoc line Odd frame

if( (READ_SIDE1< rRD1_LENGTH) )

begin

mADDR


Trang 59

end

if(mRD_DONE)

begin

RD_MASK


Trang 60

begin

Write


Trang 61

frame tiep theo vao SDRAM BUFFER, khi o RD1 tch cc th co the xuat ra 1 line thuoc

frame mi nay ch khong phai la line cua frame hien hanh.

Nh a noi trong phan mo ta khoi Timer tr hoan ban au, viec oc t SDRAM

BUFFER c kch hoat sau 1 khoang thi gian la 513927.5 chu ky tnh t khi frame th 3

bat au: khi cac Pixel tren line th 300 cua frame goc ( 513872.5 1716; vi1716 la so

byte cua 1 line trong frame goc) tng ng vi line th 282 (bo qua18 line co bit V =1)

ang c ghi vao SDRAM BUFFER, th bat au xuat xen ke cac line. ieu kien RD2

truy xuat ung Even frame c thoa man, xet cac line ma RD1 xuat ra:

Khi WR ghi lien tuc t line 282 en line 507 vao SDRAM BUFFER th hien nhien

la RD1 truy xuat ung. Luc nay line ma RD1 ang xuat la 13 + (507 - 282) 2 = 125.5

Xet frame tiep theo: phai ch het 9 line au tien mi bat au ghi t line 0. Luc o

RD1 se truy xuat line th 125.5 + 9 : 2 = 130; nh vay cho en khi RD1 xuat line xong line

th 253 th WR mi ch ghi ti line (253-130)2 = 246. am bao d lieu c xuat van la

cua frame hien thi.

Ngoai ra trong khoi Control Center con co cac khoi command, control interface e

tao va ong bo cac lenh lam ti (refresh), tch nap (Precharge), chon che o oc, ghi,

truyen khoi, ong thi ma hoa va giai ma lenh cho SDRAM theo mo ta cac che o truy

cap SDRAM Bang 1.2 vi cau truc kha phc tap. Trong khuon kho luan van nay ta

khong e cap en ma ch tham khao va s dung code verilog t cong ty Altera va hang

san xuat KIT DE2 la Terasic.

Khi ghep vao trong khoi tong the ta se dung cau truc e xuat d lieu nh sau:

.RD1_DATA(m1YCbCr), .RD2_DATA(m2YCbCr), roi chon d lieu e a vao khoi x

ly anh YUV : assign mYCbCr_d = !VGA_Y[0]? m1YcbCr : m2YCbCr; vi !VGA_Y[0]

la do khoi VGA Controller a ra cho biet line ang xuat tren man hnh v tr le hay

chan e chon d lieu xuat ra tng ng.


Chng 9: Khoi X ly anh YUV

Trang 62

CHNG 9: KHOI X LY ANH YUV

9.1 S O KHOI

Hnh 9.1: S o cua khoi x ly anh YUV

Ten Mo ta

CLK Xung clock 27Mhz t kit DE2.

RESET Reset he thong.

mYCbCr_d[15:0] D lieu hnh anh ngo vao.

oRequest Tn hieu ieu khien do VGA Controller cung cap: yeu

cau xuat d lieu.

iX[0]

Tn hieu ieu khien do VGA Controller cung cap, cho

biet v tr cua Pixel la chan hay le (bit 0 trong gia tr cua

bo em v tr Pixel)

oRequest

Tn hieu ieu khien do VGA Controller cung cap: yeu

cau xuat d lieu.

iYCbCr Pixel anh sau qua Image Process x ly.

oY[7:0] Thanh phan o sang (Luma) cua Pixel c tach ra.

oCb[7:0] Thanh phan Cb cua Pixel c tach ra.

oCr[7:0] Thanh phan Cr cua Pixel c tach ra.

Resgister[1..9][15:0] 9 thanh ghi tng ng vi ca so 3x3 pixels.



Trang 63

9.2 MO TA

Khoi Line Buffer: la bo em e lu lai cac gia tr cac Pixel can thiet

Xet ca so 3x3 Pixel: trong chuoi d lieu ngo vao v tr cac pixel nay nh sau:

e ca pixel nay xuat hien cung luc trong 1 ca so th phai can co cac bo em ( cac

thanh ghi va line buffer) e lu lai cac gia tr cua P1, P2, P3, P4, P5, P6, P7, P8 cho en

khi P9 xuat hien:

Hnh 9.2 : S dung cac Line_buffer va Register e tao ca so 3x3 pixel

Line_Buffer co the la 1 FIFO hoac la 1 thanh ghi dch(shift register), nhng trong th

vien cua Quartus khong co FIFO vi chieu dai 640 Words, nen ta s dung thanh ghi dch:


mi, at ten la Line_Buffer, chon phan Memory Compiler >> shift register ( RAM-Based).

Ta chon o rong d lieu la 8bits, chieu dai (distance between Taps) la 640, so Tap la 1, va

anh dau chon e s dung chan clock enable. Nh vay ta c ca so Pixel:

P1 P2 P3

P4 P5 P6

P7 P8 P9



Trang 64

Khoi x ly anh: ta chon 1 trong hai che o lam viec:loc trung bnh va tach bien.

Loc trung bnh: thc hien phep tng quan ca so pixel vi mat na

1 2 11

2 4 216

1 2 1

Tuy nhien d lieu vao la 16 bit vi 8 bit cao la thanh phan Y va 8 bit thap la Cb hoac

Cr. Nen ta s dung khai bao e tach ra tng thanh phan roi x ly:

Loc_trung_binh Loc_trung_binh_0 ( clock,

reset,

register1[7:0],

register2[7:0],

register3[7:0],

register4[7:0],

register5[7:0],

register6[7:0],

register7[7:0],

register8[7:0],

register9[7:0],

out2

);

Loc_trung_binh Loc_trung_binh_1 ( clock,

reset,

register1[15:8],

register2[15:8],

register3[15:8],

register4[15:8],

register5[15:8],

register6[15:8],

register7[15:8],

register8[15:8],

register9[15:8],

out1

);

e thc hien phep tng quan gia ca so Pixel vi mat na loc, ta tien hanh theo

cac bc:

-Nhan cac thanh phan tng ng cua 2 ca so lai vi nhau: mat na loc ch co cac he so

1, 2, 4 (de thay ket quala cac so 10 bit )



Trang 65

k = 1 th gi nguyen: : multi_1


Trang 66

module MULT2 ( dataa,

datab,

result);

e lay phep bnh phng ta nhap cung mot gia tr cho 2 ngo vao dataa va datab

Dung bo lay can bac 2 t th vien cua Quartus e tnh G t tong hai ket qua tren:

Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom mi, at

ten la SQUARE, chon phan Arithmetic >> ALTSQRT. Chon o rong bit ngo vao la 16

bit.Sau khi tong hp ta c mot khoi vi khai bao nh sau (trong o radical la d lieu 17

bit ngo vao, q la ket qua 9 bit cua phep lay cant,t a khong s dung chan remainder):

module SQUARE ( radical,

q,

remainder);

Thc chat khoi x ly anh ch la cac cap khoi loc bien, loc trung bnh c ghep song

song nhau. Moi khoi trong cap x ly tren tng 8 bit d lieu, sau o ghep chung lai vi

nhau (out3, out 4 tng t la cac ngo ra cua cac khoi loc bien)

assign out_pixel = (!reset)? 16'b0 : out;

assign out = select_process? {out1,out2} : {out3,out4};

Khoi se xuat ra gia tr cua pixel anh tng ng vi gia tr pixel anh nam chnh gia

ca so. Co 1 van e c at ra ay la khi mot frame va bat au th ca so cha co u

9 Pixel nhng bo x ly anh van thc hien loc va xuat pixel se dan en sai so bien anh.

ong thi khoi Image Process can co 1 so chu ky xung clock e x ly xong anh. Tuy

nhien vi 1 frame kch thc 640 x 480 th cac sai lech nay co the chap nhan c.

Khoi Extract YCrCb to Y, Cr, Cb : n gian ch la tach chuoi d lieu 16 bit dang

YCrCb lien tiep ra 3 thanh phan Y, Cr, Cb. Da vao tn hieu iX[0] do VGA controller a

ra e biet v tr cua Pixel trong hang la chan hay le(16 bit nay la YCb hay la YCr):

if(iX[0])

{mY,mCr}

Chng 10: Khoi Convert YcrCb to RGB

Trang 67

CHNG 10: KHOI CONVERT YCRCB TO RGB

10.1 S O KHOI:

Hnh 10.1: S o cua khoi Convert YCrCb to RGB

Ten Mo ta


RESET Reset he thong.

iY[7:0] Thanh phan o sang (Luma) cua Pixel c tach ra.

iCb[7:0] Thanh phan Cb cua Pixel c tach ra.

iCr[7:0] Thanh phan Cr cua Pixel c tach ra.

Red[9:0] Thanh phan Red cua Pixel tng ng.

Green[9:0] Thanh phan Green cua Pixel tng ng.

Blue[9:0] Thanh phan Blue cua Pixel tng ng.

10.2 MO TA

Khoi nay chuyen oi t dang d lieu anh YCrCb 8 bit sang dang RGB 10 bit cho phu

hp vi yeu cau ngo vao cua VGA DAC la ADV7123. Di ay la cong thc chuyen oi

sang dang RGB 8 bit:

R = 1.164 ( Y - 16 ) + 1.596 ( Cr 128 ) ;

G = 1.164 ( Y - 16) - 0.392 ( Cb - 128 ) - 0.813 ( Cr - 128 ) ;

B = 1.164 ( Y - 16 ) + 2.017 ( Cb 128 ) ;



Trang 68

Sau o e co dang RGB 10 bit th ta dch trai 2 bit ( nhan 4 ) nen co cong thc mi:

R = 4.656 ( Y - 16 ) + 6.384 ( Cr - 128 ) ;

G = 4.656 ( Y - 16 ) - 1.568 ( Cb - 128 ) - 3.252 ( Cr - 128 );

B = 4.656 ( Y - 16 ) + 8.068 ( Cb - 128 ) ;

Do cac he so co dang thap phan, trong khi o cac phep toan cua phan cng c

tong hp ch thc hien tren so nguyen nen khi lam tron va tnh toan th sai so kha ln, v

vay ta phai nhan bieu thc tren vi mot so nguyen H nao o e giam bt sai so khi lam

tron cac he so, sau o tnh toan bieu thc roi chia lai cho H. So nguyen H ta chon co dang

k2 th thay v thc hien phep chia cho A ta ch can dch phai k bit. ay ta chon k = 7 hay

H = 128 th o chnh xac cua he so se en ch so th 2 sau dau phay. Ta co cong thc cuoi

cung (a lam tron e tnh toan tren cac so nguyen) :

oR = (596 Y + 817Cr 114131) : 128 ;

oG = (596 Y 200Cb 416Cr + 69370) : 128 ;

oB = (596 Y + 1033Cb 141781) : 128 ;

e thc hien cong thc tren ta tien hanh theo cac bc:

1)Nhan cac thanh phan Y, Cb, Cr vi cac he so tng ng roi cong chung lai, s dung bo

tong hp cong nhan ( ALTMULT_ADD ) trong th vien cua Quartus :


mi, at ten la MAC3; chon phan Arithmetic >> ALTMULT_ADD. Vi cac thong so c

chon nh sau:

+ Tnh oG can 3 phep nhan : so lng bo nhan la 3.

+ Y,Cb,Cr la so 8 bit dng: o rong ngo vao A la 8, kieu d lieu khong dau (Unsigned)

+ Trong cac he so co so am nen, gia tr ln nhat la 1033 (so 11 bit) : o rong ngo vao B la

11, kieu d lieu co dau (signed)

+ Chon ham gia hai bo nhan au tien (first pair of multiplier) la phep cong (Add).

Khi tong hp xong ta c mot khoi vi khai bao nh sau :



Trang 69

module MAC_3 (dataa_0,

dataa_1,

dataa_2,

datab_0,

datab_1,

datab_2,

result,

aclr0,

clock0);

Trong o:

+ Ngo vao ieu khien : xoa bat ong bo aclr0 va xung clock lam viec clock0,

+ Cac ngo vao d lieu la dataa_0; dataa_1; dataa_2 la cac so 7 bit khong dau; datab_0;

datab_1; datab_2 la cac so 11 bit co dau;

+ Ngo ra la d lieu 21 bit co dau:

result = (dataa_0 datab_0) + (dataa_1 datab_1) + (dataa_2 datab_2)

Chu y: data_b0, data_b1, data_b2 la cac he so cong thc a tnh tren: d h596 =254 ,

d h817 =331 , d h-200 =F38 (so bu hai), d h-416 =E60 (so bu hai), d h1033 =409 .Vay e thc

hien bc nay ta se goi cac khoi MAC_3 nh sau:

MAC_3 u0( iY, iCb, iCr,

11'h254, 11'h000, 11'h331,

X, iRESET, iCLK);


11'h254, 11'hF38, 11'hE60,

Y, iRESET, iCLK);


11'h254, 11'h409, 11'h000,

Z, iRESET, iCLK);

2)Sau o tr (cong) vi cac so hang con lai roi chia cho 128 bang cach dch phai 7 bit:

X_OUT >7;

Y_OUT >7;

Z_OUT >7;



Trang 70

Tuy nhien khi cac gia tr R, G, B c tnh theo cong thc tren th co the la so am

hoac vt qua1023 (10 bit ) v vay ta gii han lai gia tr vao trong khoang 0 en 1023:

if(X_OUT[13])

oRed1023)

oRed

Chng 11: Khoi VGA Controller

Trang 71

CHNG 11: KHOI VGA CONTROLLER

11.1 S O KHOI

Hnh 11.1 : S o cua khoi VGA Controller

Ten Mo ta


RESET Tn hieu reset do khoi Timer tr hoan ban au cung cap

oRequest

Tn hieu ieu khien cho phep xuat d lieu t SDRAM BUFFER

va lu cac gia tr cua Line Pixel vao khoi Line Buffer

oVGA_BLANK

oVGA_SYNC

oVGA_VS

oVGA_HS

Cac chan nay c gan tng ng vao chip giai ma ADV7123 va

cong VGA tren kit DE2 e ong bo viec xuat ra monitor cac

frames anh. Do xuat anh theo chuan VGA 640x480 nen chan

VGA_SYNC luon phai at mc cao e am bao viec ong bo.

VGA_X[0]

Cho biet v tr cua Pixel la chan hay le e ieu khien viec tach

cac thanh phan Y, Cr, Cb trong khoi x ly anh YUV

VGA_Y[0]

Cho biet Line se hien th tren man hnh la thuoc Odd Frame hay

Even Frame e chon d lieu a ra t SDRAM BUFFER

Cac chan d lieu iRed, iGreen, iBlue c noi trc tiep vi ngo ra VGA_R, VGA_G,

VGA_B. Ngo ra oVGA_CLOCK la nghch ao cua ngo vao CLK .



Trang 72

11.2 LU O GIAI THUAT

Giai thuat tao tn hieu ong bo e giao tiep vi VGA la tao cac bo em vi cac

thong so chuan e tao ra cac tn hieu ong bo theo gian o thi gian:

Hnh 11.2: Vung hien th trong 1 chu ky quet vi tn hieu reset t he thong



Trang 73

T cac thong so nh th cho chuan VGA 640x480 60Hz tren , do xung clock trong

thiet ke co tan so 27MHz nen ta chon cac gia tr tng ng cho cac thong so nh sau:

1) oi vi VGA_HS (tn hieu ong bo quy nh thi gian hien th 1 hang trong 1 chu

ky quet ngang): H_FRONT = 16, H_SYNC = 96, H_BACK = 48, H_ACT = 640. Nh vay

khi hien th xong 1 hang th phai ch 1 khoang thi gian la H_BLANK = H_FRONT +

H_SYNC + H_BACK = 160 (n v la so chu ky xung clock) th hien th hang mi. Luc

nay thi gian quet ngang la: H_TOTAL = H_BLANK + H_ACT = 800.

Lu o giai thuat tao VGA_HS :



Trang 74

2) oi vi VGA_VS(tn hieu ong bo quy nh thi gian hien th 1 frame trong 1 chu

ky quet toan bo man hnh): V_FRONT = 11; V_SYNC = 2; V_BACK = 31; V_ACT = 480.

Nh vay khi hien th xong 1 frame th phai ch 1 khoang thi gian la V_BLANK =

V_FRONT+V_SYNC+V_BACK = 44 (n v la chu ky xung quet ngang VGA_HS) th

hien th frame mi. Thi gian quet man hnh la V_TOTAL = V_BLANK + V_ACT= 524.

Lu o giai thuat tao VGA_VS cung c thc hien tng t ch khac la V_Cont

c em len sau moi canh len cua VGA_HS.

11.3 MO TA

Khoi se tao cac tn hieu ieu khien cho ADV 7123 va ong bo viec truy xuat, x ly

d lieu vi cac khoi khac da tren cac tn hieu nh th quet ngang va quet doc sao:

+ Tao tn hieu quet ngang VGA_HS vi bo em len H_Cont :

always@(posedge iCLK or negedge iRST_N)

begin

if(!iRST_N)

begin

H_Cont


Trang 75

+Tao tn hieu quet doc VGA_VS vi bo em V_Cont theo canh len cua VGA_HS:

always@(posedge oVGA_HS or negedge iRST_N)

begin

if(!iRST_N)

begin

V_Cont =V_BLANK)? V_Cont-V_BLANK : 11'h0;

Nh vay ke t khi bat au quet 1 frame th phai ch 1 khoang thi gian co o dai la

(V_BLANK H_TOTAL) + H_ BLANK = 35360 (chu ky) th oRequest mi c tch cc.


Tong ket

Trang 76

PHAN IV: TONG KET

ANH GIA KET QUA

a cau hnh va s dung c chip ma hoa ADV7181B

S dung c SDRAM 4Mx16 e lu tr d lieu.

a hien th c len VGA anh video vi kch thc chuan 640x480

Thiet ke c bo loc trung bnh, bo loc bien theo phng phap Sobel (ma

xu ly anh video dung fpga tren de2-clbrobot-robotgiaoduc

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