課程名稱 : 積體電路分析與模擬 (analysis and simulation of integrated circuits)

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課程名稱 : 積體電路分析與模擬 (Analysis and Simulation of Integrated Circuits)

Text Books1. 電腦輔助電子電路設計 , 鄭群星 , 全華2. Reference Books1. OrCAD PSpice and Circuit Analysis, J.

Keown 2. Real Word FPGA Design with Verilog,

Coffman

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任課教師及相關資料授課教師 : 李宗演研究室 : 綜科館 207-4 E-mail: [email protected] URL: www.ntut.edu.tw/~tylee/ Tel: 02-2771-2171 ext. 2251 Office Hour: 星期三及四 10:00~12:00

mailto:[email protected]

http://www.ntut.edu.tw/~tylee/

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Goal Introduce the methodologies of analy

sis and simulation on integrated circuits

Learn the analysis and simulation techniques on analog circuits using OrCAD PSpice tool

Learn the design and simulation techniques on digital circuits using Xilinx FPGA design tool kit

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Progress of Course Analysis and Simulation Techniques o

n Analog Circuits Using OrCAD PSpice Tool/ 8 Weeks

Design and Simulation Techniques on Digital Circuits Using Xilinx FPGA Design Tool Kit / 8 Weeks

進度表

週次月日時數授課內容要項備註

1 3 .積體電路分析與模擬簡介 . 電路描述格式及規則　

2 3 .被動元件的描述規則及取用 . 獨立電源元件　

3 3 　中秋節

4 3.控制電源元件及描述 . 半導體元件及描述 ,

.模擬電路分析的種類及輸出格式　

5 3 .直流模擬電路分析　

6 3 .小信號模擬電路分析　

7 3 .交流信號模擬電路分析　

8 3 .相關參數分析　

9 3 期中考期中考週　

10 3 .FPGA簡介　

11 3 .圖形編輯器介紹　

12 3 .邏輯模擬器之使用介紹　

13 3 .如何建自己的元件庫　

14 3 .自訂元件模組之使用　

15 3 .狀態機設計法　

16 3 .硬體描述語言　

17 3 .設計實例

18 3 期末考試全校停課舉行期末考試　

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Scores Term Exam 30% Final Exam 30% Home Works, Computer Exercises, an

d Others 40%

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Question & Answer ? ? ? ? ? ?

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Chapter 1 Introduction

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Design Concept Verification The design is described in

equations or behavioral expressions

This high-level design description is then simulated or verified to match with expected result

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Design Implementation Verification

Simulates the physical design The simulated result should match

with the expected specification

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Design Performance Verification

Predicts or verifies the design “quality”

Post-layout simulation with extracted RCs is needed in nanometer technology

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Verification Methodologies Dynamic simulation

Examples: SPICE, Verilog Static verification or analysis

Examples: Formal verification, static timing analysis

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Dynamic vs Static Verification Dynamic simulation mimics the physical

behavior Difficult to select the input stimulus pattern to

cover all possible verifications using dynamic simulation

More time consuming to simulate many possible test patterns

Static verification tends to validate the design still works under all possible working conditions

Static verification is less accurate and may give wrong results occasionally

Static verification is limited to digital circuits only

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Important Simulation Technologies Complier code logic simulation Transistor-level SPICE-like circuit

simulation Switch-level transistor circuit

simulation Fast SPICE circuit simulation Analog behavioral simulation Hierarchical circuit simulation

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Complied Code Logic Simulation Complier the digital circuit into a

sequence of computer machine code Traditional interpretation method

looks up the logic gate model to simulate the digital state changes

Machine code execution runs faster than procedural interpretation

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SPICE Circuit Simulation Developed at UC Berkeley in early 1970s Models and simulations the electrical-level

circuit behavior accurately Widely used due to open release to public users Solves the whole circuit as a single entity Slow and limited to speed circuit size less than

100,000 elements Earlier attempts to speed up simulation,

including waveform relaxation and iterative method, failed to commercialize

Fast SPICE simulation technology achieved commercial success until late 1990s

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History of Dynamic Simulation Logic simulation and circuit

simulation are converging into a mixed-signal simulation

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Basic Idea of Circuit Simulation

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First Generation SPICE Technology

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Second Generation Fast SPICE Technology

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Hierarchical Simulation Technology

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Hierarchical Circuit Simulation

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Switch-Level Simulation Models MOSFET as a switch Able to model the bi-directional signal flow

behavior of MOSFET Simulates the flat transistor netlist extracte

d from physical layout Simulation speed is 1,000X faster than SPIC

E and is close to gate-level logic simulation Limited in digital circuit only A hot technology in 1980s but only achieved

limited commercial success

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Switch-Level Logic Simulation

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Switch-Level Timing Simulation Models the conducting MOSFET by an

equivalent resistance Calculates the switching delay by the RC time

constant Limited to digital CMOS circuit simulation Unable to simulate analog behavior even in

digital circuits

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Analog Event-Driven Simulation

Similar to digital logic simulation except the event is triggered by analog voltage change instead of logic state transition

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Fast SPICE Circuit Simulation Partitions the whole circuit into smaller subci

rcuits and solves each one individually Runs 10-100X faster than SPICE Can simulate circuits up to 5 million element

s Simulates analog behavior in digital circuits Less accurate especially when simulating hig

h-sensitivity analog circuits Gets more acceptance due to new enhancem

ents in simulating analog circuits

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Analog Behavioral Simulation Needed in top-down analog/mixed-signal d

esign flow Further speeds up verification A new trend: device model described in Veri

log-A Verifies design concept instead of design im

plementation Very difficult to create and characterize the

analog behavior model

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Use SPICE or Mixed-Signal Simulation Mixed-signal simulator is difficult to use No need if SPICE performance is

reasonable Fast SPICE may do a better job if

majority portions are analog

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Reference A.-C. Deng, Signal Integrity in SOC Des

ign, SOC/IP 菁英人才養成課程 , 三 C 整合策劃推行小組 , July 2002.

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Question & Answer

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SPICE & OrCAD PSpice 介紹

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SPICE 模擬電路程式之功能 DC Analysis Small Signal Transfer Function DC Transfer Curves Small Signal Sensitivities Small Signal Frequency Domain Response Noise Analysis Distortion Analysis Transient Analysis Fourier Analysis Temperature Analysis

電路描述模擬的方式

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OrCAD PSpice 使用電路描述模擬的方式 (1)

開始→程式集→ OrCAD family release 9.2 Lite Edition →PSpiceAD Lite Edition

File→New→Text File 依 OrCAD PSpice 描述格式將電路輸入 ,

filename 為 XXX.CIR

OrCAD PSpice 使用電路描述模擬的方式(2)

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File→Open→XXX.CIR Simulation File→Run XXX View→Outputfile ( 出現輸出檔視窗 XXX.out)

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File→Exit (Exit OrCAD PSpice)

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OrCAD PSpice 使用繪圖描述模擬的方式 (1)

開始→程式集→ OrCAD family release 9.2.1 Lite Edition →Capture Lite Edition

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File→New→Project

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Location → 輸入 C:\OrCAD pspice\project\example1 →OK ( 目錄要先存在 )

Create a blank project

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Project Manager and Schematic page Editor

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繪圖及模擬 : 1. 取元件 ~ 直流電源 Place → Part → Begin Search → VDC

→ VDC/source.olb

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繪圖及模擬 : 1. 取元件 ~ 電阻 Place → Part → Begin Search → R/ana

log.olb →ok (Ctrl + R 轉動用 )

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繪圖及模擬 : 1. 取元件 ~ 地線 Place → Ground, libraries →SOURCE,

Symbol →0 →ok

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繪圖及模擬 : 2. 開始連線 Place → Wire

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繪圖及模擬 : 3. 改變元件的屬性 ~ 電源在該 VDC 元件以 mouse 左鍵連續按兩

次

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繪圖及模擬 : 3. 改變元件的屬性 ~ 電阻改變電阻的屬性之方法與改變電源的屬

性類似

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繪圖及模擬 : 4. 加入元件節點編號 Place → Net Alias →1 →Ok → 放置電路中

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繪圖及模擬 : 5. 電路圖存檔 File →Save →OrCAD Capture 對話盒

→ OK

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繪圖及模擬 : 6. 產生網路連接表 Letlist PSpice →Create Netlist 繪圖及模擬 : 7. 觀看網路連接表 PSpice → View Netlist

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繪圖及模擬 : 8. 開始模擬 PSpice →New Simulation profile

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設定 Analysis type

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PSpice →Run

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View →output file ( 模擬的輸出之結果 )

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Question & Answer

課程名稱 : 積體電路分析與模擬 (analysis and simulation of integrated circuits)

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