경종민 [email protected] 1 future prospect of ic technology (itrs)-ii ( 계속 ) 2002. 9.16
TRANSCRIPT
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Design Verification Challenges
[ ≤65nm / Beyond 2007 ]1. Design for verifiability
– New methodology needed• Understanding of how design errors occur
producing easy-to-verify design– Characterize and minimize performance and area
impact2. Higher levels of abstraction
– Verification methods for the higher-levels of abstraction
– Complexity of design enabled by higher-level design– Equivalence checking between higher-level and
lower-level models
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Design Verification Challenges
3. Human factors in specification– How to specify what I want, correctly and efficiently– Need to understand what kinds of specifications are
most understandable (clear vs. opaque)– Need to consider how to make specifications
modular and modifiable (not intractable)4. Verification of non-digital systems
– Hybrid systems verification for analog properties/effects
– Verification of probabilistic systems5. Heterogeneous systems
– How to model, analyze, and verify MEMS, EO devices, and electro-biological device
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Design Test• High speed device interface
– Faster I/O Speed: multiple GHz– Complex I/O protocol:
• simultaneous bidirectional, differential signaling with voltage swings of ~100 mV
• Highly integrated SOC design– Larger integrated devices
• Non-linear complexity growth for design tools, DFT, manufacturing test
– Integration of analog, mixed signal• Nonlinear increase in the cost of testability,
design verification, manufacturing test
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Design Test Challenges[ ≥65nm / Through 2007 ]1. At-speed test with increasing frequencies
– Continuation of at-speed functional test with increased clock frequencies
– At-speed structure test with increased clock frequencies– Test and on-chip measurement techniques for multi-GHz serial
ports
2. Capacity gap between DFT/Test generation/Fault grading tools and design complexity– Better EDA tools for advanced fault models– DFT to enable low-cost ATE– Non-intrusive logic BIST– AMS DFT/BIST, especially at high frequencies
3. Quality and yield impact due to test equipment limits– Power and thermal management during test– Fault diagnosis and design for diagnosability– Yield improvement and failure analysis tools and methods
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Design Test Challenges4. Signal integrity testability and new fault models
– Signal integrity testability– Fault models for analog failures
5. SOC test– Integration of SOC test methods onto test
equipment platform– Integration of multiple fabric-specific test
methodologies– DFT, BIST and test methods compatible with core-
based SOC environment and constraints– Embedded memory built-in self-diagnosis and self-
repair – Test reuse
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Design Test Challenges[ ≥65nm / Beyond 2007 ]1. Integrated self-testing for heterogeneous SOCs
– Test of multi-GHz RF front-ends on chip– Use of on-chip programmable resources for SOC
self-test– Dependence on self-test solution for SOC– (Analog) signal integrity test issues caused by
interference from digital to analog circuitry– Test methods for heterogeneous SOC including
MEMS and EO components
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Design Test Challenges2. Diagnosis and reliability screens
– Diagnosis and failure analysis for AMS parts– Design for efficient and effective burn-in to screen
out latent defects– Quality and yield impact due to test equipment
limits– New timing-related fault models for defects/noise in
nanometer technologies3. Fault tolerance and on-line testing
– DFT and fault tolerant design for logic soft errors– Logic self-repair using on-chip reconfigurability– System-level on-line testing
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Contents• Introduction to IP reuse• Design for reuse• Efforts for IP reuse• On-chip bus-based SoC architecture for IP
reuse• Virtual component interface
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Contents• Introduction to IP reuse
– SoC (System-on-Chip)– Productivity gap– New design methodology– Advantage of IP reuse– Difficulties of IP reuse
• Design for reuse• Efforts for IP reuse• On-chip bus-based SoC architecture for IP reuse• Virtual component interface
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2008 year(0.07m)
130,000,000 gates
4%
SoC (System-on-Chip)• SoC era is opened due to
– Increasing silicon capacity and– Shrinking time-to-market.
Source : SIA roadmap
1999 year(0.18m)
5,250,000 gates
MPEG2 Decoder (4%): 200,000 gates
TMS320C50 (1%) 40,000 gates
MPEG2 Encoder (27%): 1,400,000 gates
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Productivity Gap
Productivity Gap
Silicon capacity
1988 1992 1996 2000
Design capability
0.8u 0.6u0.5u
0.35u
0.18u
10
1
# of Tr./Chip(million)
100
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New Design Methodology• IP reuse is a solution to the productivity gap.• What is IP?
– IP (Intellectual Property) is composed of• Design file and document file• License (copyright, patent, and trade secret)• Technical support
– Pre-designed and pre-verified macro block– Other names: VC (Virtual Component), core
IPSoC
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Advantage of Reuse
Design Effort (for a specific function)
Project (where a specificfunction is required.) Design for Reuse
= IP Development
Design by Reuse = Design Reuse
Design for one-time use
1st 2nd 3rd 4th 5th
Productivity is improved by using the well-designed IP’s.
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Reuse or not, that’s the Question!
• Design of IP for external reuse ; >3~5 X development cost (vs. one-time use), Not very often due to cost,.., typically one or two per chip now.
• Design of IP for internal reuse ; 2~3 X dev. cost (vs. one-time use, occurs quite often.
• Instantiation of IP developed for reuse ; 10 x productivity boost in instantiation, while IP developed for one-time use incurs 2 x prod. boost (compared to non-reuse)
• Development for reuse? Domain-independent IP must be developed for reuse; domain-specific IP like multi-media or data communication blocks maybe yes if planned to be used on several product generations or several different products in a short period of time, like within 2 years; application-specific blocks probably not.
• Reuse occurs more often than we think, i.e., through adding new features, fixing bugs, improving performance, or further integration, etc. (white box reuse vs. black box reuse)
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IP Specification and its translation
• Formal vs. executable specification; Formal specification handles functional behavior, timing, power and area, but not quite commercial, while Executable spec includes onlt function but commercial like C, C++, S 이 , vera, Specman, etc.
• Design procedure can be either Waterfall or Spiral; waterfall works until 0.35 micron; spiral approach simultaneously considering hw, sw, power, timing and physical is necessary below 0.18, definitely.
• Correct by construction(waterfall, or top-down) or construct by correction (UltraSPARC project at SUN)?
• Top down or Bottom up? Where do they meet? Downward path; translate(refine) the upper level specification; Upward path; integrate and verify
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Difficulties of IP Reuse• Standardization problem of IP deliverables
– Is a simple concept, but actually difficult. (due to culture difference and communication barriers)
• Marketing problem– IP marketing strategy, media, license, pricing
policy
• Security problem– Tradeoff between accessibility and theft
protection
• Management problem– Version control, search, backup and interface
between CAD tools
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Contents• Introduction to IP reuse• Design for reuse
– Principles– Modeling guideline– IP deliverables– IP classification– Factors in selecting IP’s
• Efforts for IP reuse• On-chip bus-based SoC architecture for IP reuse• Virtual component interface
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Design for Reuse• Principles
– A module will be modified and reused in other projects by other design teams.
– A module must be easy to be integrated into a design even without the original designer.
• Techniques for design reuse (= good design techniques)– Good documentation– Good code– Thorough commenting– Well-designed verification environments– Robust scripts
• We already learned these techniques, but in the pressure of a real design project → can’t get reusable design.– Additional effort is required for reusable design, as an early
investment on the future project.
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Modeling Guideline• The RTL description of soft IP’s must have
– Consistency, readability, portability, interoperability, and synthesizability.
• RMM (Synopsys) presents RTL coding guidelines on– Naming convention: signal, variable, port name and more– Coding for portability– Guidelines for clocks and resets– Coding for synthesis– Designing with memories– Code profiling
• For example,– Use registers for all outputs (even inputs if possible)– Use flip-flop instead of latch– Use single edge & single clock– Use synchronous RAM
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RMM• Reuse Methodology Manual (RMM)
– Is used as a text book for reusable design• Written by Michael Keating (Synopsys, Inc.)
and Pierre Bricaud (Mentor Graphics Corp.)– Focus
• How to fit reusable IP’s into SoC development methodology
• How to design reusable soft and hard IP’s• How to integrate IP’s into SoC design• How to verify timing and functionality in
large-scale SoC designs
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IP Deliverables• IP deliverables
– Documentation– Test scheme– Related test bench– Interface– Behavioral model– Emulation model– Test sheet– Synthesizable RTL HDL model– Gate-level netlist
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IP Classification• Hardware IP’s
– In terms of hardness• Hard IP’s : given as a layout (placement & routing
done )• Soft IP’s : given as a synthesizable description
– RTL(Register Transfer Level) description: Verilog, VHDL
• Firm IP’s : with floorplanning and placement done– In terms of programmability
• Processor IP’s• Fixed function hardware IP’s
• Software IP’s– C code: Complex algorithm, speed-optimized code– Assembly code:
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Hardware IP’s Tendency
Hard IP
Soft IP
Class Tendency
custo
miza
bl
e
pre
dicta
bl
e
porta
bl
e
tech
. d
ep
en
dent
long
desig
n
time
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Functionality
Performance
Power
Area
Interface
Support tools
Trade-off
Factors in Selecting IP’s
Credibility
Business terms
Silicon technology
Technical support
…and more
Reuse quality
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Selecting Processor IP’s• Processor IP Selection Criteria
– power, performance, area, cost– flexibility– hardness(hard IP vs. soft IP)– available system software(compiler, assembler)– development environment(in-circuit emulator)– simulation model(speed & accuracy)– supported library– supported OS– inter-operability with other IP’s
Common criteriafor all kinds of IP’s
Specific criteriafor processor IP’s
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Contents• Introduction to IP reuse• Design for reuse• Efforts for IP reuse
– VSI– Design and Reuse (D&R)– RMM– MORE program
• On-chip bus-based SoC architecture for IP reuse
• Virtual component interface
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VSI• Virtual Socket Interface (VSI) Alliance: www.vsi.org
– An industry group working to facilitate the adoption of design reuse
• Object– Define, develop, authorize, test and promote “open
standard specifications on IP’s”• Development Working Groups (DWG): Define details of IP
deliverables– System Level Design DWG– Manufacturing Related Test DWG– On-Chip Busses DWG– Mixed Signal Design DWG– Implementation/Verification DWG– IP Protection DWG– Virtual Component Transfer DWG
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Design and Reuse (D&R)• Design and Reuse: www.design-reuse.com
– A private company but public
• Provided services– IP yellow page service (catalog and
advertisement)– IP marketing/sales assistance service– Tools and services on IP qualification and IP
prototyping
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MORE Program• MORE (Measure Of Reuse Excellence)
assessment program calculates MORE metric– www.openmore.com– Spreadsheet-based assessment (10 pages)– 150 rules and guidelines based on RMM
• 30 are language-specific (VHDL or Verilog)– Tested with IP companies in Pilot Program
• Weighting factors are being refined.– MORE is the reuse quality reference metric.
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Section Item Type AssessmentUnweighted
Score Max ScoreWeighted
Score
I Macro Design Guidelines 11 18 30.56%3 System-Level Design Issues: Rules and Tools 7 12
3.2 Timing and Synthesis Issues 5 103.2.3 Reset 5 10
3.2.3.1
The basic reset strategy for the chip is documented, especially 1) synchronous or asynchronous, 2) internal or external power-on reset, 3) more than one reset (hard vs. soft reset), 4) each macro individually resettable, for debug purposes R S 5 10
3.3 Functional Design Issues 2 23.3.1 System Interconnect and On-Chip Buses 2 2
3.3.1.2If an on-chip busing scheme is used, then the appropriate bus strategy is selected for the different kinds of blocks used in the SoC design. G A 2 2
5 RTL Coding Guidelines 4 65.2 Basic Coding Practices 4 4
5.2.1 General Naming Conventions 4 4
5.2.1.2 Lowercase letters for all signal names, variable names, and port names. G A 2 25.2.1.3 Uppercase letters for names of constants and user-defined types. G A 2 2
5.3 Coding for Portability 0 25.3.3 Packages 0 0
5.3.3.1
If VHDL, then all parameter values and function definitions for a design put into a single separate file (a "package") and named <DesignName>_package.vhd. G NA 0 0
5.3.4 Include Files 0 2
5.3.4.1If Verilog, then keep the `define statements for a design in a single separate file.* G N 0 2
MORE Program
Design rules for reusable design Assessment
MORE metric
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Contents• Introduction to IP reuse• Design for reuse• Efforts for IP reuse• On-chip bus-based SoC architecture for IP
reuse– SoC architecture overview– A typical SoC architecture– System bus vs. peripheral bus– On-chip buses
• Virtual component interface
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SoC Architecture Overview• SoC architecture trend
– At least one programmable processor– Hierarchical bus architecture
• Processor bus > system bus > peripheral bus– Synchronous bus clocking (single clock)– Various proprietary on-chip buses (OCB)
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A Typical SoC Architecture
CPU Co-processor Cache
Processor bus
Peripheral bus
CoreOCB BridgeCoreCoreIP’s with
low bandwidth
System bus
ArbiterCPU BridgeCoreCoreCoreIP’s with
high bandwidth
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System vs. Peripheral Bus
System bus Peripheral bus
Multiple master operation
Single bus master
Pipelined operation Non-pipelined operation
Single & Burst transfer Single transfer only
Split transaction support No split transaction
Cache support No cache support
Error code/timeout No timeout support
Timing analysis is required
Timing ensured by protocol
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On-Chip Buses– ARM (www.arm.com): AMBA
• AHB(Advanced High-Performance Bus) / APB(Advanced Peripheral Bus)
– IBM (www.chips.ibm.com): CoreConnect• PLB(Processor Local Bus) / OPB(On-chip Peripheral Bus)
– PALM Chip (www.palmchip.com) • M Bus / Palm Bus
– Mentor Graphics (www.inventra.com) • FISP Bus
– OMI (www.omimo.be) • PI (Peripheral Interconnect) Bus
– Fujitsu (www.fujitsu.com) • Spcl Bus
Hierarchy of on-chip bus (from VSIA)
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Research on IP Integration
global system specification and designspecification language
exploration&partitioning&architecture selection
software synthesis
interface&communication
synthesis
hardware synthesis
co-verification
prototype/real product development
property assessment (performance, cost, power, ...)
Co-design research focus
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Contents• Introduction to IP reuse• Design for reuse• Efforts for IP reuse• On-chip bus-based SoC architecture for IP
reuse• Virtual component interface
– VCI– Cost of IP integration– Peripheral VCI– Basic VCI
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VCI• Standardized IP interface is required to minimize
integration cost.• Virtual Component Interface (VCI) Standard
– Defined by VSI Alliance for easy IP integration– Specification on IP interface, not on-chip bus– Support point-to-point connection between IP’s and
on-chip bus-based IP integration– Bus wrapper is used to connect VCI-compliant IP’s to
proprietary OCB’s.• VCI Family
– Peripheral VCI– Basic VCI– Advanced VCI
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OCBMaster
OCBSlave
VCI• Point-to-point • On-chip bus-based
integration
VCI-compliant IP
Master
Core
Slave
Core
Request
Response
Master
Core
Slave
Core
Slave Master
On-Chip Bus
Wrapper
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Cost of IP Integration
Core
Very low Low High Very high
On-chip bus
matchinginterface
Core
VCI-compliantinterface
Wrapper
Core
mismatchinginterface
Wrapper
Core
customizedinterface
Wrapper
IP Integration Cost
When interface of IP matches
OCB
When interface of
IPis compliant
with VCI
When interface of
IP mismatches
OCB
When interface of
IP is customized for special purpose
On-chip bus On-chip bus On-chip bus
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Peripheral VCI• Simple interface• Peripheral on-chip bus• Low-speed point-to-point
IP connection• Read or write at a time• Non-pipelined operation
PVCI Core
ADDRESSBE
WDATA
RDATARERROR
EOP
ACKVAL
RD
RESETNCLOCK
Read/Write command
Handshake
CommonSignals(ADDR/DATA)
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Basic VCI• Peripheral VCI + • System on-chip bus• High-speed point-to-point
IP connection• Read and write are
independent of each other.
• Pipelined operation
ADDRESSBE
WDATA
RDATARERROR
EOP
CMDACKCMDVAL
CMD
RESETNCLOCK
CFIXEDCLEN
CONTIGCONST
PLENWRAP
RSPVALRSPACK
REOP
BVCI Core
Read/Write command
Handshake (Write)
CommonSignals(ADDR/DATA)
Handshake (Read)
Auxiliarysignals for
bursttransfer
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Summary• IP reuse can reduce the productivity gap in
SoC.• Modeling guidelines to design reusable
modules need to be set up before project start.• There are many factors in selecting IP’s,
technical, cost, cultural, business, etc.• Efforts for design reuse: VSI, D&R, MORE, VCX• On-chip bus-based SoC architecture is
presented.• Standardized IP interface (i.e,, VCI) is required
to minimize integration cost.