專題名稱 : vlsi implementation of a jpeg baseline system

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專題名稱 : VLSI Implementation of a JPEG Baseline System. 輔仁大學電子工程系所 學生:劉自清、邱于展、黃雅臻 指導教授:呂學坤教授. 簡介 - PowerPoint PPT Presentation

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Cell-Based Design JPEG Baseline Layout JPEG Baseline JPEG
2007 11
SOC JPEG Baseline
SOC encounter JPEG Baseline System
JPEG Baseline System
1. (Subsampler) Level Shifter
2. RGB-YUV
5. (Sequence Controller)
DCT JPEG (Baseline System) JPEG Baseline System
Sub1282
DCT
(1) DRU (Data Reorder Unit) block (row) DRU DRU Matrix-Vector Multiplier
(2) ACFBDEG Matrix – Vector MultiplicationMatrix-Vector Multiplier hardwired multiplier
(3) IDRU (Inverse Data Reorder Unit) DCT
(4) Transpose Memory row 64 column
ZigZag DCT 8 × 8 Z DCT
Quantization
JPEG Baseline System Layout
128 DCT 173-128 = 45
Entropy Encoder Huffman Code Entropy Code 1101111001001111
block ReadyIn block EOB
EOB (EOBEOB2EOB3) ReadyIn high JPEG Baseline System
JPEG
Baseline
(2) Category Selection Circuit 12
(3) Strip Logic ZRL EOB EOB
(4) Huffman EncoderDC DPCM Category AC RunLengthCategory Huffman Coding Code
(5) Data Paker 16 16
Cell Base Design JPEG Baseline System
Cell Base Design JPEG Baseline System RTL coding SOC encounter Physical Design DRC&LVS Layout
Cell Base Design
Entropy Encoder
DC block
AC AC
ZRL 16
EOB block
EB block
Gate Count