0.15pm cmos with high reliability and performance

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0.15pm CMOS with High Reliability and Performance

K.Takeuchi, T.Yamamoto, A.Tanabe, T.Matsuki, T.Kunio, M.Fukuma,*K.Nakajima, 'H.Aizaki, *H .Miyamoto and 'E.Ikawa

Microelectronics Research Labs. and *ULSI Device Development Labs., NEC Corporation

1120. Shimokuzawa, Sagam ihara-shi, Kanagawa 229, JAPAN

Abstract

0 . 1 5 ~ MOSFETs with high reliability andperformance have been realized. The acceptable powersupply voltage V was estimated to be 1.9V. Areasonably short ring oscillator delay of 33ps was obtainedfor the 1.9V V maintaining an 0.4V threshold voltage.Anomalous surface state generation and Vm shift for thePMOS were observed, though the degradation was lesssevere than the nMOS.

Introduction

Recently, MOSFET miniaturization down to 0 . 1 pgate length and below is explored. One of the key issuesfor achieving high performance with such small devicesis the choice of power supply voltage V and hence, hotcamer reliability. It is particularly important for roomtemperature operation, since Vm is difficult to be scaleddown due to the stand-by current requirements, while thedelay is roughly proportional to VJ(V,-V,3.

In this paper, hot carrier reliability and performanceof 0 . 1 5 ~ MOSFETs are presented.

Device Fabrication

Fig.1 shows a schematic cross section of the 0 . 1 5 ~CMOS. The gate oxide thickness is 5nm. Gate electrodeswere drawn by electron beam lithography. The n+ and p+gates were doped simultaneously with the source/drainformation. The source/drain consists of a shallowextension [l ] and a deeper contact region. The junctiondepth and gate-todrain overlap of the source/drainextensions were suppressed by depositing a thin SiO,blanket before their implantation. The activation was doneby RTA. TiSi, salicidation was used to reduce both thegate poly and the source/drain resistances. All the pattemlayers except for the gate were formed by i-linelithog raphy, using 0 . 6 ~ esign rules. Therefore, toreduce the junction capacitance, the channel impurity forpunchthrough stop was implanted only around the gate

electrode (within 0 . 3 ~ f the nominal gate edge),covering most of the source/drain regions with aphotoresist. Fig.2 shows typical I-V curves for a poly gatelength L,=0.15~ . Good tum-off and reasonably large

current is obtained.

36.2.10-7803-1450-6 $3.00 0 1993 IEEE

Hot Carrier Lifetime for nMOS

To determine the allowable V , the hot carrierreliability for both nMOS and PMOS was examined. F ig 3shows shift in the drain current AI& (linear region), andshift in the charge pumping current &, as a function ofstress gate voltage V,, for the nMOS (gate lengthLQ=0.18pm, effective channel length I-=O.l6pn). Thesurface state generation (AIcp) shows a well-known 'bell'shape, and the peak coincides with the maximum insubstra te current I vs V, curve, as usual. However, thecorresponding peak in the AIJ, vs V, curve is notdistinct. This suggests that enhanced electron trappingoccurs at high V,, causing an ID degradation comparableto that in the maximum 1- condition. The enhancedtrapping may have occurred due to some process-relatedproblem. Since he worst case stress condition is not clear,lifetime extrapolation for both maximum I and V,=VDconditions were performed (ng. 4). The extrapolatedlifetime (defined by Ag,,,/g,=lOQ, where g, is thetransconductance in the linear region) is shorter for themaximum I condition. The acceptable V, to guarantee10 year dc lifetime was estimated to be 1.9V.

Hot Carrier Lifetime for PMOS

Fig.5 shows shift in the threshold voltage AVm, andshift in the charge pumping current &, s a function ofstress gate voltage V,, for the PMOS (LQ=0.18pm,L8pp--O.l3pm). Usually, electron trapping dominates inPMOS degradation, causing a sharp positive peak in aAVm vs V, plot at low IV,I. However, in the presentcase, significant surface state generation (&), and largenegative AVm, presumably caused by the surface state,are observed. Similar AIm vs V, results, but withoutsignificant AVm, is found in the literature [2].

The peculiar AIm vs V, curve seems to reflect the rateof hole injection into the gate oxide; The peak aroundvQ =-2 v should correspond to the m a x i " of hot hole

generation, and the monotonic increase for V,<-4V becaused by the increase in hole-attractive field near thedrain. One reason for the enhanced surface stategeneration may be the more hole-attractive vertical field

IEDM 93-883



in surface channel pMOSFETs, compared with buriedchannel ones. Electron trapping also occurs, as indicatedby the slight positive AVm at lower lVol stress. However,it seems to be less significant in determining the devicelifetime.

The results of PMOS lifetime extrapolation mshown in Fig.6. Bias conditions similar to the nMOS ase

(Vo=VJ2 and V,=V,J were chosen. The lifetime wasdefined by AVm=20mV, since AVm was severer than Agm.The estimated allowable V, (2.5V) is much larger thanthat for the nMOS.

Switching speed

Applying the 1.9V supply voltage, a reasonably shortring oscillator delay zpdof 33ps (Fig.7) was obtained forFO=1, &=0.15pm, while suppressing the standby-currentto about lOpA/pm (IVmI=0.4V).

According to SPICE simulations, junction capacitanceC,, overlap capacitance Cov, and source/drain resistanceRSD are the key parasitic factors that determine theinverter delay. By means of the area-restricted channelimplant technique. C, is adjusted to be equivalent to

0 . 1 5 ~esign, while using 0 . 6 ~esign rules. Furtherreduction of C, s possible by cutting down the alignmentto lerance (0 . 3 ~ ) . hough Cov is controlled by the SiO,blanket, there still remains room for suppressing thePMOS overlap (L0 -u0 .06p) . By reducing both C, andCO,, 2, about 2Ops should be possible. Parasiticresistance becomes a serious problem. In spite of the TiSi,salicidation, high source/drain doping, and large contactholes, RsD caused, through the reduction of the drivecurrent, more than 10% ncrease in zpp The effect of gatesheet resistance was not serious in this work, since thechannel width used was small (W4p.m. W p 8 p ) .

Closer look at nMOS hot carrier effects

In Fig.8, the allowable V, is compared with that for0 . 4 ~eneration devices. The 1.9V V, for the 0 . 1 5 ~devices is much higher than expected from the constantfield scaling ( V e L , ) , and even higher than the square-root scaling level (V,=LovL) [3]. This can be a result ofnon-stationary carrier transport, which is expected to occurwhen the channel length approaches 0 . 1 ~ . herefore,channel length dependence of nMOS hot carrier effectshave been examined.

Fig.9 shows 'charge to lifetime' (TI,,) vs impactionization rate ( I d , , ) plots [4] for various effectivechannel lengths LBpp. The lifetime z is defined by either(A) relative shift in transconductance (Ag,,,/gm=lO%), r(B) absolute shift in source-to-drain linear resistance(AR=300sZm). For a given I d , , the absolute degradation

in R is independent from & own to 0 . 1 ~ .he &dependence of z in the case of (A) is merely due to thedifference in the initial R. A shorter device has smaller R,and hence suffers from a larger relative degradation

884-IEDM 93

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36.2.2

(AR/R=AgJgJ for the same absolute degradation AR.Fig.10 shows ISJD as a function of VD-VmAT for long

and short devices, where VmAT s the potential of thepinch-off point. V can be determined from theI d D ata itself, as was first pointed out in [5]. TO

obtain more well-defined results, particularly for shortchannel devices, VmAT was extracted from Isv$ID VS VD

curves, instead ofI,

vs V, ones. The horizontal shift ofa curve from the one for Vo=Vm was taken as equal toVNAT, assuming V , a for V,=V,. Here, V, forvD=O.lvwas used. Following this VmAT determinationprocedure, I d D VS VD-VNAT curves almostindependent from LBpp.

Thus, if the voltage applied to the pinch-off region(=VD-VNAT)s fixed, the electron energy distributions nearthe drain is considered to be independent from thechannel length even down to 0 . 1 ~ . o singular I-dependence is detected. However, the results do not meanthe absence of non-stationary carrier transport. Rather, itis believed to have occurred, but equally in all thesamples, resulting in the failure of its detection. Toexperimentally catch it, samples with different pinch-offregion length must be compared.

Conclusion

Hot carrier reliability of 0 . 1 5 ~ MOS and PMOSwas evaluated. The allowable V, was as high as 1.9V.The degradation of PMOS, though much different fromconventional devices, was less severe than nMOS.Applying the 1.9V, a ring oscillator delay T, of 33pswas obtained, maintaining sufficiently high V,. Theresults demonstrate that 0 . 1 5 ~ MOS with both highspeed and reliability is feasible.

No singular channel length dependence was found,either in hot carrier degradation or impact ionization,down to 0 . 1 ~ .o experimentally detect non-stationarycarrier transport, the length of pinch-off region, rather

than channel length, should be varied as a parameter.

Acknowledgement

The authors would like to thank N.Ehdo for hiscontinuous encouragement, and I.Sakai, H.Abiko,T.Horiuchi for their useful suggestions.

References

[l] G.A.Sai-Halasz et al., in 1987 IEDM Tech. Dig., p.397.[2] F.Matsuoka et al., IEEE Trans. Electron Devices, ED-37, 1487 (1990).131 M.Kakumu et al., E E E Trans. Electron Devices, ED-37, 1334 (1990).

[4] C.Hu et al.,IEEE

Trans. Electron Devices, ED-32, 375(1985).[5] T.Y.Chan et al., IEEE Electron Devices Letters, EDL-5, 505 (1984).



lpMos1i s p

A!3D extension

/

Schematic MOSFET cross section.

I \ /P-

iI

punchthrough t of5nm

stopper

E fp)q0 4 Em4

-1

-1Z -2

VoM VoM VcMD M

(a) nMOS (b) PMOS

Fig2 EV curves of n and pMOSFETs. L.&.lSp.

L A . 1 3 p m for nMOS and 0 . 1 0 ~or PMO S. respecuvely.

Fig3 Shift in linear drain current I,, and charge pumpingcurrent Icp vs stress gate voltage V,. for nMOSFET( L g p P - - . 1 6 ~ ) .

-1 60 0.5

stress @VD-5V, 310s

VG (v)

Fig.5 Shift in threshold voltage V, and charge pumpingcurrent I, vs stress gate voltage Vo. for pMOSFETW . 1 3 ~ ) .

Fg.4 Lifetime extrapolation for nMOSFET. The lifetime isdefined by Ag./&=lO%, where & is the maximum

transconductance in the linear region.

1 /VD or')Fig.6 Lifetime extrapolation for pMOSFET. The lietime isd e f d by AV+2OmV. AVm is much more severe thanND.

36.2.3IEDM 93-885



/- Ilk. ’ 0:r 1

GATE LENGTH (p m)ig.7 Output waveform of a 101 stage ring oscillatorwith

F-1, L,#.15~. W , 4 w W,=8~lm, IVm14.4V and

V e 1 . 9 V . The delay ~ ~ - 3 3 ~ s .

Figs Canparison of allowable V between 0.15 and0.4- generations. Junction depth, gate oxide thickness,substrate concentrationare different between the generations.SD is for single drain.

5

Fig.10 Is& VS V,-V, for various V,’S and twodifferent G s . Though slight horizontal shift (SOmV)between W . 1 0 and 1 . 0 ~s observed, the shape of thecurves are almost identical.

105 10-2 lo-’ 100

I S U B / I D

Fig.9 ‘51, VS IsvJrDfor IMOSFETSwith various where‘c is for (A) AgJg-=lO% and (B) AR=30OS&m. R is thesource-to-drain resistance at V,=2V in the linear region.

36.2.4

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0.15pm cmos with high reliability and performance

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