02 vhdl 의 기본

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02 VHDL 의 기본

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VHDL 의 기본 - 강의순서▣ VHDL Model Components

▣ Object

▣ Data Type

▣ Attribute

▣ Operator

▣ Statements◈ Concurrent vs. Sequential Statements

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VHDL Model Components▣ Entity

◈ 하드웨어 외부입출력 인터페이스를 정의

◈ 하드웨어 블록의 이름과 입출력 PORT 를 선언

▣ Architecture

◈ 하드웨어의 내부를 표현

◈ 내부회로의 연결 , 동작 또는 구조를 표현 .

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Entity Declarations

▣ The primary purpose of the entity is to declare the signals

in the component’s interface

▣ The interface signals are listed in the PORT clause

▣ PORT clause declares the interface signals of the object

to the outside world

◈ Declaration syntax :

PORT (signal_name : mode data_type);

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Entity – Signal Mode

▣ The port mode of the interface describes the direction in

which data travels with respect to the component

◈ In : data comes in this port and can only be read

◈ Out : data travels out this port

◈ Buffer : data may travel in either direction, but only one signal

driver may be on at any one time

◈ Inout : data may travel in either direction with any number of

active drivers allowed ; requires a Bus Resolution Function

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Entity – Signal Type▣ 1bit signal: bit, std_logic

▣ 2bit 이상의 signal: bit_vector, std_logic_vector◈ 2bit -- bit_vector(1 downto 0) std_logic_vector(1 downto 0)

◈ 4bit -- bit_vector(0 to 3) std_logic_vector(0 to 3)

◈ std_logic, std_logic_vector : IEEE 1164 Standard

Signal Type 으로 std_logic, std_logic_vector 이 사용될 때는 아래의 문장이 Entity 문장 전에 미리 사용 되어야 함 .

Library ieee;

Use ieee.std_logic_1164.all;

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Architecture Bodies▣ Describe the operation of the component

▣ Consist of two parts :◈ Declarative part -- includes necessary declarations

type declarations, signal declarations, component declarations, subprogram declarations

◈ Statement part -- includes statements that describe organization and/or functional operation of component

concurrent signal assignment statements, process statements, component instantiation statements

architecture 동작표현이름 is

[ 선언문 ]

begin

동작 표현end entity 이름

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Entity and Architecture ex.LIBRARY __library_name;

USE __library_name.__package_name.ALL;

ENTITY __entity_name IS

PORT(

__input_name, __input_name : IN STD_LOGIC;

__input_vector_name : IN STD_LOGIC_VECTOR(__high DOWNTO __low);

__bidir_name, __bidir_name : INOUT STD_LOGIC;

__output_name, __output_name : OUT STD_LOGIC

);

END __entity_name;

ARCHITECTURE a OF __entity_name IS

SIGNAL __signal_name : STD_LOGIC;

SIGNAL __signal_name : STD_LOGIC;

BEGIN

-- Process Statement

-- Concurrent Procedure Call

-- Concurrent Signal Assignment

-- Conditional Signal Assignment

-- Selected Signal Assignment

-- Component Instantiation Statement

-- Generate Statement

END a;

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Simple VHDL Code : AND Gate

Library ieee;


Entity and_2 is port( a, b : in std_logic; y : out std_logic );end and_2;

Architecture dataflow of and_2 isbegin

y <= a and b;end dataflow;

Signal Type 으로 std_logic 이 사용될 때는 항상 사용 .

Signal Type 으로 std_logic 이 사용될 때는 항상 사용 .

Entity 문장 : 입력 a,b, 출력 y 를 나타냄Entity 문장 : 입력 a,b, 출력 y 를 나타냄

Architecture Body : 회로의

설명

Architecture Body : 회로의

설명

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객체 (Object)▣ 값을 가질 수 있는 변수로 아래의 3 가지 종류

◈ Signals

◈ Variable

◈ Constants

▣ The scope of an object is as follows :1. Objects declared in a package are available to all VHDL

descriptions that use package

2. Objects declared in an entity are available to all architecture associated with that entity

3. Objects declared in an architecture are available to all statements in that architecture

4. Objects declared in a process are available only within that process

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객체 (Object) - Signals▣ Used for communication between VHDL components

▣ Real, Physical signals in system often mapped to VHDL signals

▣ All VHDL signal assignments require either delta cycle or user-specified delay before new value is assumed.


◈ 사용 예 signal a, b : std_logic; 선언

a<= ‘1’; b<=‘0’; Signal a,b 에 값 ‘ 1’,’0’ 을 대입 .

SIGNAL signal_name : type_name [ :=value];

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객체 (Object) - Variable▣ Provide convenient mechanism for local storage

▣ Scope is process in which they are declared

▣ All variable assignments take place immediately


◈ 사용 예 variable a, b : std_logic; 선언 a := ‘1’; b :=‘0’; Variable a,b 에 값 ‘ 1’,’0’ 을 대입 .

VARIABLE variable_name : type_name [ :=value];

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객체 (Object) - Constants▣ Name assigned to a specific value of a type

▣ Allow for easy update and readability


◈ 사용 예

constant bits3_0 : std_logic_vector(2 downto 0) := "000"; 선언 y<= bits3_0; Signal y 에 값 “ 000” 을 대입 .

CONSTANT constant_name : type_name [ :=value];

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Data Type▣ Scalar Types

◈ Enumeration Type : BIT, BOOLEAN, CHARACTER

◈ Integer Type : INTEGER

◈ Floating : REAL

◈ Physical

▣ Composition Type

◈ Array Type

◈ Record Type

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Data Type - Scalar Types(1) ▣ Enumeration Type

◈ type bit is (‘0’, ‘1’);

◈ type boolean is (false, true);

◈ type std_ulogic is ( ‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);

◈ type std_logic is resolved std_ulogic;

▣ IEEE 1164 Standard Data Types

◈ ‘U’ : Uninitialized ‘X’ : Strong Unknown

◈ ‘0’ : Strong Logic 0 ‘1’ : Strong Logic 1

◈ ‘Z’ : High Impedance ‘W’ : Weak Unknown

◈ ‘L’ : Weak Logic 0 ‘H’ : Weak Logic 1

◈ ‘-’ : Don’t Care

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Data Type - Scalar Types (2) ▣ Integer Type

◈ Minimum range for any implementation as defined by standard :

-2,147,483,647 to 2,147,483,647

▣ Floating type

◈ Minimum range for any implementation as defined by standard :

-1.0E38 to 1.0E38

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Data Type - Composition Type▣ Array Type

◈ type byte is array (7 downto 0) of bit; byte 형을 선언

◈ signal a: byte; a 를 byte 로 선언◈ a <= “00001111”; a 에 값 할당

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Operators

▣ Defined precedence levels in decreasing order :

◈ Miscellaneous operators -- **, abs, not

◈ Multiplication operators -- *, /, mod, rem

◈ Sign operator -- +,-

◈ Addition operators -- sll, srl, sla, sra, rol, ror

◈ Relational operators -- =, /=, <, <=, >, >=

◈ Logical operators -- AND, OR, NAND, NOR, XOR, XNOR

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Attribute▣ Attributes provide information about certain items in

VHDL

◈ X’EVENT -- TRUE when there is an event on signal X

◈ X’LAST_VALUE -- returns the previous value of signal X

◈ Y’HIGH -- returns the highest value in the range of Y

◈ X’STABLE(t) -- TRUE when no event has occurred on signal X in

the past ‘t’ time

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02-2 Statements

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Statements - 강의순서▣ 병행 (Concurrent) Statement

◈ Simple Assignment, Simple

◈ Signal Assignment, Conditional

◈ Signal Assignment, Selected

◈ Process Statement

▣ 순차 (Sequential Statements)

◈ If Statement

◈ Case Statement

◈ For Loop Statement

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Concurrent - Signal Assignment, Simple

signal_name <= expression;

1) b 에 변화가 생길 때마다 b 의 값이 y 에 출력됨 2) Sensitivity List : b

1) b 에 변화가 생길 때마다 b 의 값이 y 에 출력됨 2) Sensitivity List : b

y <= b;

y <= a or b;

1) a 나 b 에 변화가 생길 때마다 a or b 의 값이 y 에 출력됨 .

2) Sensitivity List : a,b

1) a 나 b 에 변화가 생길 때마다 a or b 의 값이 y 에 출력됨 .

2) Sensitivity List : a,b

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Concurrent - Signal Assignment, Conditional

signal <= expression1 WHEN boolean_expression1 ELSE

expression2 WHEN boolean_expression2 ELSE

expression3;

1) boolean_expression1= 참 (True) 이면

signal <= expression1 이 실행되며 ,



3) 위의 2 가지 조건이 모두 성립하지않으면

signal <= expression3 이 실행된다 .





3) 위의 2 가지 조건이 모두 성립하지않으면


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Concurrent - Signal Assignment, Selected

WITH expression SELECTsignal <= expression1 WHEN constant_value1,

expression2 WHEN constant_value2, expression3 WHEN constant_value3;

1) expression = constant_value1 이면


2) expresion1 = constant_value2 이면




1) expression = constant_value1 이면






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Concurrent – Process Statement

▣ Process 문은 하드웨어 모듈을 기술 .

▣ Process 문의 내부는 순차처리 .

▣ 복잡한 알고리즘의 구현 시 편리


[Label:] process [( Sensitivity List)]

begin

Sequential statements;

end process [Label];

Sensitivity List 에 적혀있는 신호에 변화생길 때

begin 과 end process 내의 문장을 실행

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Sequential – Wait Statement

wait on signal [, signal]

wait until boolean_expression

wait for time_expression

(1) wait on a, b;

(2) wait until ( x < 100 );

(3) wait for 10 ns;

(1) a,b 에 변화가 생길 때까지 기다린다 .

(2) X<100 일 때까지 기다린다 .

(3) 10ns 동안 기다린다 .

(1) a,b 에 변화가 생길 때까지 기다린다 .

(2) X<100 일 때까지 기다린다 .

(3) 10ns 동안 기다린다 .

Suspends the sequential execution of a process or subprogram

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Sequential – Wait on vs. explicit sensitivity list

wait on statement

process begin y <= a and b; wait on a, b; end process;

explicit sensitivity list

process (a, b) begin y <= a and b; end process;

Process 문을 사용하는 두가지 방식 : 모두 가능함 .

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Sequential – IF Statement

IF expression1 THEN

statement1-1;

statement1-2;

ELSIF expression2 THEN

statement2-1;

statement2-2;

ELSE

statement3-1;

statement3-2;

END IF;

1) expression1 = 참 (True) 이면

statement1-1, state1-2 가 실행 ,



3) 위의 2 가지 조건 모두 성립하지않으면








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Sequential – Case Statement

CASE expression IS

WHEN constant_value1 =>

statement1-1;

statement1-2;

WHEN constant_value2 =>

statement2-1;

statement2-2;

WHEN OTHERS =>

statement3-1;

statement3-2;

END CASE;

1) expression1 = constant_value1 이면












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Sequential – For Statement

loop_label:

FOR index_variable IN range LOOP

statement1;

statement2;

END LOOP loop_label;

index_variable 의 값을 변해가면서 statement1, statement2 를 반복적으로 실행 .

아래의 (a), (b) 는 모두 같은 표현임 .

Range 는 downto, to 의 2 가지형태임 .

index_variable 의 값을 변해가면서 statement1, statement2 를 반복적으로 실행 .

아래의 (a), (b) 는 모두 같은 표현임 .

Range 는 downto, to 의 2 가지형태임 .

loop_Start:

FOR i IN 0 to 3 LOOP

y(i) <= a(i) and b(i);

END LOOP loop_Start;

(a)

y(0) <= a(0) and b(0);

y(1) <= a(1) and b(1);

y(2) <= a(2) and b(2);

y(3) <= a(3) and b(3);

(b)

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02-3 VHDL 모델링

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VHDL 모델링 방법 - 강의순서▣ 데이터 흐름 (Dataflow Descriptions)

◈ 부울대수를 이용해서 표현

▣ 추상적 동작 (Behavioral Descriptions)

◈ 알고리즘방법으로 표현

▣ 구조적 (Structural Descriptions)

◈ 단순한 선의 연결로 표현

▣ 혼합적 (Mixed Descriptions)

◈ 위의 3 가지방법을 혼합

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02-3-1 Dataflow Description

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Dataflow Descriptions▣ 입력과 출력과의 관계를 기술한 부울 대수식을 이용한 설계방식 .

▣ 문장의 순서는 무관하다 .

▣ 병행처리문 (Concurrent Statement) 에 주로 사용 .

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Dataflow - 2 입력 AND Gate

Library ieee;


Entity and_2 is port( a, b : in std_logic; y : out std_logic );end and_2;

Architecture dataflow of and_2 isbegin

y <= a and b;end dataflow;

Dataflow 방식은 부울대수를 그대로 표현

Dataflow 방식은 부울대수를 그대로 표현

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Dataflow - 2 입력 OR Gate

Library ieee;Use ieee.std_logic_1164.all;

Entity or_2 is port( a, b : in std_logic; y : out std_logic );end or_2;

Architecture dataflow of or_2 isbegin

y <= a or b;end dataflow;

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Dataflow - Andor_2library ieee;

use ieee.std_logic_1164.all;

entity andor_2 is

port( a, b, c : in std_logic;

y : out std_logic);

end andor_2;

architecture a of andor_2 is

signal t : std_logic;

begin

t<=a and b;

y<=t or c;

end a;

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Dataflow – 4 bits OR gatelibrary ieee;


entity or_4bits is

port( a, b : in std_logic_vector(3 downto 0);

y : out std_logic_vector(3 downto 0)

);

end or_4bits;

architecture xxx of or_4bits is

begin

y <= a or b;

end xxx;

Bus의사용Bus의사용

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Dataflow - Half Adderlibrary ieee; Use ieee.std_logic_1164.all;

Entity half_add isport( a,b : in std_logic; sum, c_out : out std_logic);end half_add;

Architecture dataflow of half_add isbegin

sum <= A xor B;c_out <= A and B;

end dataflow;

문장의 순서는

무관

문장의 순서는

무관

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Dataflow - Full Adderlibrary ieee;use ieee.std_logic_1164.all;entity fulladd is port( a, b, cin : in std_logic; s, cout : out std_logic);end fulladd;architecture a of fulladd issignal t1, t2, t3 : std_logic;begin

t1 <= a xor b;t2 <= a and b;t3 <= t1 and cin;s <= t1 xor cin;cout <= t2 or t3;

end a;

t1

t2

t3

문장의 순서는

무관

문장의 순서는

무관

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Dataflow - Decoder3_8library ieee;use ieee.std_logic_1164.all;

entity decoder38_data is port( d2, d1, d0 : in std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : out std_logic);end decoder38_data;

architecture xxx of decoder38_data issignal nd2, nd1, nd0 : std_logic;Begin

nd2 <= not d2; nd1 <= not d1; nd0 <= not d0; y0<= nd2 and nd1 and nd0; y1<= nd2 and nd1 and d0; y2<= nd2 and d1 and nd0; y3<= nd2 and d1 and d0; y4<= d2 and nd1 and nd0; y5<= d2 and nd1 and d0; y6<= d2 and d1 and nd0; y7<= d2 and d1 and d0;

end xxx;

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02-3-2 Structural Description

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Structural Descriptions▣ 가장 하드웨어적 표현에 가까움▣ 구성 요소 및 연결까지 표현▣ Graphic Editor 를 이용한 고전적인 설계방식과 동일 .

▣ Component( ) 문을 이용하여 선언▣ Port map( ) 문을 이용하여 핀들을 서로 연결 .

◈ 위치결합 (positional association)

Port 문 내의 Signal 의 위치순서대로 나열◈ 이름결합 (named association)

Port 문 내의 Signal 의 위치순서와는 상관없이 ( port 문 내의 형식이름=> 실제 이름 ) 의 방식으로 결합 .

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Structure - Andor_2

library ieee; use ieee.std_logic_1164.all;entity andor_2 is port( a, b, c : in std_logic; y : out std_logic);end andor_2;architecture a of andor_2 iscomponent and_2port( a, b : in std_logic;

y : out std_logic );end component;component or_2 port( a, b : in std_logic;

y : out std_logic );end component;signal t : std_logic;begin

U1 : and_2 port map ( a, b, t );U2 : or_2 port map( a=> t, b=>c , y=>y);

end a;

and_2.vhd, or_2.vhd 는 미리 작성된 상태임 .

and_2.vhd, or_2.vhd 는 미리 작성된 상태임 .

And_2 선언

And_2 선언

Or_2

선언

Or_2

선언

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Structure - Andor_2

library ieee; use ieee.std_logic_1164.all;entity andor_2 is port( a, b, c : in std_logic; y : out std_logic);end andor_2;architecture a of andor_2 iscomponent and_2port( a, b : in std_logic;

y : out std_logic );end component;component or_2 port( a, b : in std_logic;

y : out std_logic );end component;signal t : std_logic;begin

U1 : and_2 port map ( a, b, t );U2 : or_2 port map( a=> t, b=>c , y=>y);

end a;

And_2 :위치결합

방식

And_2 :위치결합

방식

Or_2 : 이름결합

방식

Or_2 : 이름결합

방식형식이름

형식이름

실제이름

실제이름

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Structure – 4 bits adder library ieee;use ieee.std_logic_1164.all;

entity add_4bits is port( a, b : in std_logic_vector(3 downto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); cout : out std_logic);end add_4bits;

architecture a of add_4bits iscomponent fulladd port( a, b, cin : in std_logic; s, cout : out std_logic);end component;signal tcout1, tcout2, tcout3 : std_logic;

beginU1 : fulladd port map( a(0), b(0), cin, sum(0), tcout1);U2 : fulladd port map( a(1), b(1), tcout1, sum(1), tcout2);U3 : fulladd port map( a(2), b(2), tcout2, sum(2), tcout3);U4 : fulladd port map( a(3), b(3), tcout3, sum(3), cout);end a;

Fulladd.vhd 는 미리 작성된 상태임Fulladd.vhd 는 미리 작성된 상태임

tcout1

tcout2

tcout3

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Structure - Mux 8X1 Library ieee; Use ieee.std_logic_1164.all;

entity mux8_1 is

port( a, b, c, d, e, f, g, h : in std_logic;

s2, s1, s0 : in std_logic;

y : out std_logic);

end mux8_1;

architecture xxx of mux8_1 is

component decoder3_8


d0,d1,d2,d3,d4,d5,d6,d7 : out std_logic);

end component;

signal t : std_logic_vector(7 downto 0);

signal d0,d1,d2,d3,d4,d5,d6,d7 : std_logic;

begin

U1: decoder3_8 port map( s2,s1,s0,d0,d1,d2,d3,d4,d5,d6,d7);

t(0) <= a and d0; t(1) <= b and d1; t(2) <= c and d2;

t(3) <= d and d3; t(4) <= e and d4; t(5) <= f and d5;

t(6) <= g and d6; t(7) <= h and d7;

y <= t(0) or t(1) or t(2) or t(3) or t(4) or t(5) or t(6) or t(7);

end xxx;

Decoder3_8.vhd 는 미리 작성된 상태임

Decoder3_8.vhd 는 미리 작성된 상태임

Mixed Modelling : structure +

dataflow

t(0)

t(1)

t(2)

t(3)

t(4)

t(5)

t(6)

t(7)

48

Structure – 4bits Mux 8X1 Library ieee;Use ieee.std_logic_1164.all;

Entity mux81_4bits is port( a, b, c, d, e, f, g, h : in std_logic_vector(3 downto 0);

s2, s1, s0 : in std_logic; y : out std_logic_vector(3 downto 0));end mux81_4bits;

Architecture a of mux81_4bits iscomponent mux8_1 port( a, b, c, d, e, f, g, h : in std_logic;

s2, s1, s0 : in std_logic; y : out std_logic);end component;

beginU0: mux8_1 port map (a(0),b(0),c(0),d(0),e(0),f(0),g(0),h(0),s2,s1,s0,y(0));U1: mux8_1 port map (a(1),b(1),c(1),d(1),e(1),f(1),g(1),h(1),s2,s1,s0,y(1));U2: mux8_1 port map (a(2),b(2),c(2),d(2),e(2),f(2),g(2),h(2),s2,s1,s0,y(2));U3: mux8_1 port map (a(3),b(3),c(3),d(3),e(3),f(3),g(3),h(3),s2,s1,s0,y(3));end a;

49

02-3-3 Behavioral Description

50

Behavioral Descriptions▣ 기능적 또는 알고리즘적 표현 .

▣ 고급언어를 사용한 프로그램 작성방법과 유사 .

▣ 자료보관과 관리가 편리 .

▣ Process( ) 문이 주로 사용됨 .

51

Behavioral - Signal Assignment, Conditionallibrary ieee;use ieee.std_logic_1164.all;entity mux21_when is port( a,b : in std_logic; s : in std_logic; y : out std_logic);end mux21_when;architecture a of mux21_when isbegin y <= a when (s='0') else b;end a;

마지막 조건은

else 로 처리해야

함

마지막 조건은

else 로 처리해야

함

회로보다는 동작에

관심 .

회로보다는 동작에

관심 .

52

Behavioral - Signal Assignment, Selected

library ieee;


entity mux21_with is

port( a, b: in std_logic;

s : in std_logic;

y : out std_logic);

end mux21_with;

architecture a of mux21_with is

BEGIN

WITH s SELECT

y <= a WHEN ‘0’,

b WHEN others;

END a;

마지막 조건은

else 로 처리해야 함

마지막 조건은

else 로 처리해야 함

53

Behavioral – Sequential Statement (IF)library ieee; use ieee.std_logic_1164.all;

entity mux21_if_proc is port( a,b : in std_logic; s : in std_logic; y : out std_logic);end mux21_if_proc;

architecture proc of mux21_if_proc isbegin

process(a,b,s)begin

if( s='0') theny<=a;

elsey<=b;

end if;end process;

end proc;

a, b,s 에

변화생길 때 실행

a, b,s 에

변화생길 때 실행

마지막 조건은 else 로 처리해야

함 .

마지막 조건은 else 로 처리해야

함 .

54

Behavioral – Process Statement (case)

library ieee; use ieee.std_logic_1164.all;

entity mux21_case_proc is port( a,b : in std_logic; s : in std_logic; y : out std_logic);end mux21_case_proc;

architecture proc of mux21_case_proc isbegin

process(a,b,s)begin case s is

when '0' => y<= a;when others => y<= b;

end case;end process;

end proc; 마지막 조건은 others 로

처리해야 함 .

마지막 조건은 others 로

처리해야 함 .

55

Behavioral – Signal vs. Variable

library ieee;


entity andor_2 is


y : out std_logic);

end andor_2;


signal t : std_logic;

Begin

process(a,b,c,t)

begin

t<=a and b;

y<=t or c;

end process;

end a;

library ieee;


entity andor_2 is


y : out std_logic);

end andor_2;


Begin

process(a,b,c)

variablel t : std_logic;

begin

t :=a and b;

y<=t or c;

end process;

end a;

Signal t 는 Process문이 끝나는

순간에 일괄적으로 값이 할당 .

Signal t 는 Process문이 끝나는

순간에 일괄적으로 값이 할당 .

선언되는 위치차이

선언되는 위치차이 Sensitiv

ity List차이

Sensitivity List

차이

1 1

2

2

3

Variable은 대입 즉시

값 할당 .

Variable은 대입 즉시

값 할당 .

56

참고문헌1. PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE .

2. FLOYD, DIGITAL FUNDAMENTALS WITH VHDL .

3. ARMSTRONG,GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS.

4. SKHILL, VHDL FOR PROGRAMMABLE LOGIC .

5. PELLERIN, VHDL MADE EASY.

6. LEE, VHDL CODING & LOGIC SYNTHESIS WITH SYNOPSYS.

02 vhdl 의 기본

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