1 lab7 design and implementation. 2 design example
Post on 22-Dec-2015
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1
Lab7Design and
Implementation
2
Design Example
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Computer to D2E Board
Print Port
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Boards Interconnection~~
D2E Connect to DIO1
Port APort B
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Power to D2E Board
變壓
整流器AC 110V DC 5V
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Create a New Project
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Enter a Name and Location for the Project
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2
3
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檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名
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Select Device Family, Package, Device and Speed Grade
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2
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Create a New Source
1010
Next Step
1111
Finish
1212
Create a New File
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2
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You can type Verilog on the New File
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You can type Verilog on the New File
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Type “logic.v”
Module name and File name must the same.
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Add Source
1.Right Click
2
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Select “logic.v”
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Add Test Bench Waveform
1.Right Click
2
34
5
檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名
Check Synthesize
Double Click
Select Source File
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1
2
New Source Information
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Select Design Type
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2
Waveform Created by HDL Bencher
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Select Behavioral Simulation
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1
2
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Give Input Value
1
2.Save
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Generate Expected Simulation Result
Double Click2
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Result F=(x & ~y) | (y | z)
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Add Implementation Constraints File
1.Right Click
2
3 4
5
檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名
New Source Information
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Select Synthesis/Implementation
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21
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Assign Package Pins
2. Double Click
1
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Assign Pins [1]
DIO1 D2E Signal
Sw1 P16 x Sw2 P18 y Sw3 P21 z LD1 P44 F
※請注意看板子，子板跟母板連接是使用哪一個 Port※
Port APort A DIO1 D2E
Signal Sw1 P126 x Sw2 P129 y Sw3 P133 z LD1 P154 F
Port CPort C
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Assign pins [2]
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Assign pins [3]
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2. Save
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4
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Run “Implement Design”
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2. Double Click
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View/Edit Routed Design
Double Click
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View Routed Design
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Select FPGA Start-Up Clock to JTAG Clock
1. Right Click
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3
4
3
4
5
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Generate Bitstream File
Double Click
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Run “Configure Device”
Double Click
此時請務必將版子接上
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Select Boundary.. and Automatically…
2
1
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Select “logic.bit file”
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3
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Right-click to select operation
21.Right Click
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Click “ok”
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Check the Results on Emulation Board
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Question and Answer
歷史人物中，誰跑最快 ?