3D Stacked Buck Converter with SrTiO3 (STO) Capacitors

on Silicon Interposer

Makoto Takamiya1, Koichi Ishida1, Koichi Takemura2,3, and Takayasu Sakurai1

1 University of Tokyo, Japan2 NEC Corporation, Japan

3 Association of Super-Advanced Electronic Technologies (ASET), Japan

2

Outline

▐ IntroductionFine-grained voltage engineering3D stacked DC-DC (buck) converter

▐ Silicon Interposer 1.5µF/cm2 SrTiO3 (STO) capacitor15µm thick inductor

▐ Measured Efficiency of Buck Converter

▐ Summary

3

Power Supply for High-Performance 3D-LSIs

▐ Heterogeneous integration ⇒ Various power supplies▐ Low-power and high-performance

⇒ Fine-grained voltage engineering

On-chip DC-DC (buck) converters are essential for 3D LSIs.

Package

Basechip

Stacked memoriesSensor, MEMS,High voltage generator,Analog, RF etc.(3D stacked)

Parallel processorswith own DC-DCconverters

Fine-grain power supply voltage

Interposer

4

On-Chip Buck Converters

▐ Disadvantages of on-chip inductorsSmaller inductance < 10 nHArea penaltyParasitic resistance due to thin conductors

Si LSI

Inductors should be thick and separated from a Si chip.

VIN

Driv

er

VOUT

SwitchOutput filter

5

Package

Basechip

Stacked memoriesSensor, MEMS,High voltage generator,Analog, RF etc.(3D stacked)

Parallel processorswith own DC-DCconverters

Fine-grain power supply voltage

Si interposerPackage

Basechip

Stacked memoriesSensor, MEMS,High voltage generator,Analog, RF etc.(3D stacked)

Parallel processorswith own DC-DCconverters

Fine-grain power supply voltage

Si interposer

Concept of 3D Stacked Distributed Power Supply

Output LC filters is embedded into a Si interposer.

InductorsCapacitors

Embedded

Power supply& other wires

Pads &bumps

L & Ccell array

Si interposer

6

Proposed 3D Stacked Buck Converter

Area penalty and parasitic resistance will be small.

Driv

er

Output80nH

PWM controller

Spiral inductor

Si CMOS LSI

Silicon interposer

(Flip chip)Si CMOS LSI

Silicon interposer

(Flip chip)

Si CMOS LSI

Interposer MIM capacitor

CMOS circuit

MIM: Metal-insulator-metalPWM: Pulse-width modulation

K. Takemura, K. Ishida, Y. Ishii, K. Maeda, M. Takamiya, T. Sakurai, and K. Baba, "Si Interposers with Thick Spiral Inductors for 3D Stacked Buck Converters," ICEP, TA4-1, Apr. 2011.K. Ishida, K. Takemura, K. Baba, M. Takamiya, and T. Sakurai, "3D Stacked Buck Converter with 15um Thick Spiral Inductor on Silicon Interposer for Fine-Grain Power-Supply Voltage Control in SiP’s," IEEE International 3D System Integration Conference, pp. 1-4, Nov. 2010.

7

Outline

▐ IntroductionFine-grained voltage engineering3D stacked DC-DC (buck) converter

▐ Silicon Interposer 1.5µF/cm2 SrTiO3 (STO) capacitor15µm thick inductor

▐ Measured Efficiency of Buck Converter

▐ Summary

8

Silicon Interposer

SiO2(300nm)

p-TEOS(1µm)

Silicon substrate

MIM capacitor

15µm thick electroplated Cu

(3 layers)

Chemically amplified positive resin

Via hole =30µmØ

Minimum Line/Space =20µm/20µm

9

Fabrication Process of Silicon Interposer

Cu electroplating

ILD resin formation

MIM cap. fabrication

Repetition

MIM capacitor

Si

p-TEOS

Cu

Resin

ILD: Interlayer dielectric

10

Outline

▐ IntroductionFine-grained voltage engineering3D stacked DC-DC (buck) converter

▐ Silicon Interposer 1.5µF/cm2 SrTiO3 (STO) capacitor15µm thick inductor

▐ Measured Efficiency of Buck Converter

▐ Summary

11 11

Capacitor Dielectrics

0

1

2

3

4

5

0 100 200 300 400

d (nm)

Cs (

F/cm

2 )

εr =300200100

50

3.9

Dielectrics thickness (nm)

Cap

acita

nce

dens

ity (μ

F/cm

2 )

On-chip planar capacitors

εr>100 for 1μF/cm2

When the target capacitance density is higher than 1μF/cm2,ferroelectric and related oxides are preferable.

Dielectrics εrSiO2 3.9Si3N4 7 ~ 9Ta2O5 20 ~ 50SrTiO3 (thin film) 100 ~ 600Pb(Zr,Ti)O3 (thin film) 500 ~ 1000

This work (100nm, 1.5µF/cm2, εr>100)

12

SrTiO3 Thin Film Capacitor Fabrication

AdvantagesLow crystallization temperatureEase of composition control

Examples of STO capacitor applicationsDRAM cell capacitor (on-chip)GaAs MMIC (on-chip)Polyimide-based flexible capacitor (discrete)

Reactive sputtering conditions

SrTiO

RuTop ElectrodeRu/TaBottom Electrode400°CDeposition Temp.80% Ar - 20% O2Sputtering GasSrTiO3 ceramicsTarget

RuTop ElectrodeRu/TaBottom Electrode400°CDeposition Temp.80% Ar - 20% O2Sputtering GasSrTiO3 ceramicsTarget

13 13

Properties for Sputtered STO Thin Films

Capacitor size: 100μm x 100μmSTO thickness: 100nm

Higher εr than 100, and good insulating properties

050

100150200250300

300 400 500 600 700

Deposition Temperature (℃)

Die

lect

ric C

onst

ant

Ru/TaPt/Ta

1μF/cm2

K. Takemura, A. Ohuchi, and A. Shibuya, "Si Interposers Integrated with SrTiO3 Thin Film Decoupling Capacitors and Through-Si-Vias," IEEE 9th VLSI Packaging Workshop in Japan, pp. 127-139, 2008.

This work

14

Outline

▐ IntroductionFine-grained voltage engineering3D stacked DC-DC (buck) converter

▐ Silicon Interposer 1.5µF/cm2 SrTiO3 (STO) capacitor15µm thick inductor

▐ Measured Efficiency of Buck Converter

▐ Summary

15

Process Issues for 15-μm-Thick Cu Wiring

▐ Fine Cu patteringHigher-aspect-ratio (smaller space) resist pattern

▐ Interlayer dielectric resinThicker than metal layersHigh sensitivity, high resolution

Conventional Cu wiring1 ~ 5 μm thick

This work15 μm thick

Cu wiring

16

Fabricated 15-μm-Thick Cu Wiring

L/S = 20μm/20μm

15μm thick, Line/Space = 20μm/20μm

17

Photographs of Fabricated Si Interposer (1)

7mm7m

m

Top view

Cross-sectional view

200 μm

200 μm

500 μmMIM capacitor

18

Photographs of Fabricated Si Interposer (2)

100 μm100 μm

Cu thickness: 15 μm Cu thickness: 5 μm

Top of cover layerTop of cover layer

19

Properties for Embedded SrTiO3 Capacitors

▐ Leakage current ▐ Capacitance

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

0 2 4 6 8 10

Voltage (V)

Cur

rent

den

sity

(A/c

m2 )

Capacitor properties are not affected by Cu thickness.

Cu thickness5 μm15 μm

0

5

10

15

20

25

0 5 10 15 20

Cu thickness (mm)C

apac

itanc

e (n

F)

Capacitor size: 1mm × 1mmSrTiO3 thickness: 100nm

Capacitor size: 1mm × 1mmSrTiO3 thickness: 100nm

1.5μF/cm2

(μm)

20

Properties of Cu Wirings and Spiral Inductors

▐ Sheet resistance ▐ Inductance

0

1

2

3

4

5

0 5 10 15 20Cu Thickness (μm)

Shee

t Res

ista

nce

(mΩ

/□)

0

50

100

150

200

40 60 80 100 120Line Width (�m)

Indu

ctan

ce (n

H)

Cu thickness△ 5 μm× 15 μm

After Crols et al.

After Mohan et al.

4 turns6 turns

9 turns

Space: 20 μm

According to Cu thickness, only sheet resistance reduces.

(μm)

21

Outline

▐ IntroductionFine-grained voltage engineering3D stacked DC-DC (buck) converter

▐ Silicon Interposer 1.5µF/cm2 SrTiO3 (STO) capacitor15µm thick inductor

▐ Measured Efficiency of Buck Converter

▐ Summary

22

Fabricated Buck Converter

VIN=1.8V

VOUT= 1V80nH Ri

0.1µF

MIM capacitorSpiral inductor

0.18µm CMOS LSI Silicon interposer

Non-overlap clocks(36MHz)

Metal thickness:5µm or 15µm

370µm

560µm

IOUT

2000µm

2000µmCMOS switch

23

Measured Efficiency of Buck Converter

A 15-μm-thick inductor improves power efficiency by 12 %.

100

0102030405060708090

0 20 40 60 80 100 120Output current [mA]

Pow

er e

ffici

ency

[%]

t=5µm

t=15µm

12%

VIN=1.8V, VOUT=1.0V, 36MHz

24

Summary

▐ 3D stacked buck converter with C and L on Si Interposer

▐ 1.5µF/cm2 SrTiO3 (STO) capacitor100nmεr>100

▐ 15µm thick inductor2mm x 2mm80nH

▐ Si interposer with a 15-μm-thick inductor improves power efficiency of the buck converter by 12 %.

25

Acknowledgement

This work was entrusted by NEDO “Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology” project that is based on the Japanese government's METI “IT Innovation Program”.