4.4 处理器接口电路、中断系统的设计

4.4 4.4.1 /GPIO4.4.2 4.4.3 4.4.4 USB4.4.5 JTAG4.4.6 A/D

4.4.1 /GPIO GPIOS3C44BO71S3C2410117PXA25584GPIO, PXA270120GPIOI/OGPIOGPIOGPIO GPIOI/O10-20

1I/OI/O

I/O close( )I/OI/Oxxx_close( )open( )

1 GPIO GPIO,GPIOI/OPCONA-PCONG,PDATA-PDATG,PUPA-PUOG,A-G GPDR(GPIO GPSR()GPSRGPIO GPCR ()GPCRGPIO

GPLR(GPLR(GPIOGPERGFERGEDRGAFR

2GPIO ARMI/OAMBAI/O3232/

3 ARMI/OI/O S3C44B0X717110A111B116C28DG29EF

PXA27X120GPIO AI/O B; C; D; E F G

2S3C2410GPIO

S3C2410X8117/AGPA23BGPB11/CGPC16/DGPD16/EGPE16/FGPF8/GGPG16/HGPH11/I/O

1

4

Register Address R/W Description Reset Value GPXCON0x560000x0 R/W X X GPXDAT 0x560000x4 R/W XX GPXUP0x560000x8 R/W XX RESERVED0x560000xCR/W X-

GPADAT

23[220]

1A 21A

Register Address R/W Description Reset Value GPACON0x56000000 R/W A 0x7FFFFF GPADAT 0x56000004 R/W A- RESERVED0x56000008 -A- RESERVED0x5600000C-A-

A

:0 1 :0 122GPA22nFCE10GPA10ADDR2521GPA21nRSTOUT9GPA9ADDR2420GPA20nFRE8GPA8ADDR2319GPA19nFWE7GPA7ADDR2218GPA18ALE6GPA6ADDR2117GPA17CLE5GPA5ADDR2016GPA16nGCS54GPA4ADDR1915GPA15nGCS43GPA3ADDR1814GPA14nGCS32GPA2ADDR1713GPA13nGCS21GPA1ADDR1612GPA12nGCS10GPA0ADDR011GPA11ADDR26FCE:Flash

GPBDAT---11[100]GPBUP---B[100] 01

B/2B

Register Address R/W Description Reset Value GPBCON0x56000010 R/W B 0x0 GPBDAT 0x56000014 R/W B- GPBUP0x56000018 R/W B0x0RESERVED0x5600001C- B-

B

:00 01 10 1121,20GPB10nXDREQ0Reserved19,18GPB9nXDACK0Reserved17,16GPB8nXDREQ1Reserved15,14GPB7nXDACK1Reserved13,12GPB6nXBACKReserved11,10GPB5nXBREQReserved9,8GPB4TCLK0Reserved7,6GPB3TOUT3Reserved5,4GPB2TOUT2Reserved3,2GPB1TOUT1Reserved1,0GPB0TOUT0Reserved

GPCDAT---16[150]GPCUP---C[150] 01

C/3C

Register Address R/W Description Reset Value GPCCON0x56000020 R/W C 0x0 GPCDAT 0x56000024 R/W C- GPCUP0x56000028 R/W C0x0RESERVED0x5600002C- C-

C

000110110001101131,30GPC15VD715,14GPC7LCDVF229,28GPC14VD613,12GPC6LCDVF127,26GPC13VD511,10GPC5LCDVF025,24GPC12VD49,8GPC4VM23,22GPC11VD37,6GPC3VFRAME21,20GPC10VD25,4GPC2VLINE19,18GPC9VD13,2GPC1VCLK17,16GPC8VD01,0GPC0VEND

GPDDAT---16[150]GPDUP---D[150] 01[1512][110] D/4D

Register Address R/W Description Reset Value GPDCON0x56000030 R/W D 0x0 GPDDAT 0x56000034 R/W D- GPDUP0x56000038 R/W D0xF000RESERVED0x5600003C- D-

D

000110110001101131,30GPD15VD23nSS015,14GPD7VD1529,28GPD14VD22nSS113,12GPD6VD1427,26GPD13VD2111,10GPD5VD1325,24GPD12VD209,8GPD4VD1223,22GPD11VD197,6GPD3VD1121,20GPD10VD185,4GPD2VD1019,18GPD9VD173,2GPD1VD917,16GPD8VD161,0GPD0VD8

GPEDAT---16[150]GPEUP---E[150] 01 E/5E

Register Address R/W Description Reset Value GPECON0x56000040 R/W E 0x0 GPEDAT 0x56000044 R/W E- GPEUP0x56000048 R/W E0x0RESERVED0x5600004C- E-

E

000110110001101131,30GPE15IICSDA15,14GPE7SDDAT029,28GPE14IICSCL13,12GPE6SDCMD27,26GPE13SPICLK011,10GPE5SDCLK25,24GPE12SPISI09,8GPE4IISSDO23,22GPE11SPISO07,6GPE3IISSDI21,20GPE10SDDAT35,4GPE2CDCLK19,18GPE9SDDAT23,2GPE1IISSCLK17,16GPE8SDDAT11,0GPE0IISLRCK

GPFDAT---8[70]GPFUP---F[70] 01 F/6F

Register Address R/W Description Reset Value GPFCON0x56000050 R/W F 0x0 GPFDAT 0x56000054 R/W F- GPFUP0x56000058 R/W F0x0RESERVED0x5600005C- F-

F

0001101115,14GPF7EINT713,12GPF6EINT611,10GPF5EINT59,8GPF4EINT47,6GPF3EINT35,4GPF2EINT23,2GPF1EINT11,0GPF0EINT0

GPGDAT---16[150]GPGUP---G[150] 01[15:11] G/7G

Register Address R/W Description Reset Value GPGCON0x56000060 R/W G 0x0 GPGDAT 0x56000064 R/W G- GPGUP0x56000068 R/W G0xF800RESERVED0x5600006C- G-

GLCD-PEN:POWER_ENABLEnSS0:SPI0_SELECT

000110110001101131,30GPG15EINT23nYPON15,14GPG7EINT15SPICLK129,28GPG14EINT22YMON13,12GPG6EINT14SPISI127,26GPG13EINT21nXPON11,10GPG5EINT13SPISO125,24GPG12EINT20XMON9,8GPG4EINT12LCD-PEN23,22GPG11EINT19TCLK17,6GPG3EINT11nSS121,20GPG10EINT185,4GPG2EINT10nSS019,18GPG9EINT173,2GPG1EINT917,16GPG8EINT161,0GPG0EINT8

GPHDAT---11[100]GPHUP---H[100] 01

H/8H

Register Address R/W Description Reset Value GPHCON0x56000070 R/W H 0x0 GPHDAT 0x56000074 R/W H- GPHUP0x56000078 R/W H0x0RESERVED0x5600007C- H-

HUCLKUSB

:00 01 10 1121,20GPH10CLKOUT1Reserved19,18GPH9CLKOUT0Reserved17,16GPH8UCLKReserved15,14GPH7RXD2nCTS113,12GPH6TXD2nRTS111,10GPH5RXD1Reserved9,8GPH4TXD1Reserved7,6GPH3RXD0Reserved5,4GPH2TXD0Reserved3,2GPH1nRTS0Reserved1,0GPH0nCTS0Reserved

9

Register Address R/W Description Reset Value MISCCR0x56000080 R/W 0x10330 DCLKCON0x56000084 R/W D0x0

nEN_SCKE---SCLKSDRAM0 1nEN_SCLKx---SCLKxSDRAM0SCLKx= SCLK 1nRSTCON---nRSTOUT0nRSTOUT01nRSTOUT1MISCCR---

151413121110987USBSUSPND1 USBSUSPND0 CLKSEL1

3120191817160nEN_SCKE nEN_SCLK1 nEN_SCLK0 nRSTCON

65432 10CLKSEL0 USBPAD MEM_HZ_CONSPUCR_L SPUCR_H

USBSUSPND1---USB101USBSUSPND0---USB001CLKSEL1 --- CLKOUT1000MPLL CLK001UPLL CLK 010FCLK011HCLK100PCLK 101DCLK111xCLKSEL0 --- CLKOUT0000MPLL CLK001UPLL CLK 010FCLK011HCLK100PCLK 101DCLK011x

151413121110987USBSUSPND1 USBSUSPND0 CLKSEL1

USBPAD---USB0USB1USBMEM_HZ_CON---MEM0Hi-Z 1SPUCR_L---16[150]01SPUCR_H---16[3116]01

65432 10CLKSEL0 USBPAD MEM_HZ_CONSPUCR_L SPUCR_H

DCLKCON---DDCLK1(0)CMP---DCLK1(0)mm< DCLK1(0)DIVm+1DCLK1(0)DIV-m DCLK1(0)DIV---DCLK1(0) DCLK1(0) frequency = source clock / ( DCLK1(0)DIV + 1 )

151211109876543210DCLK0CMPDCLK0DIVDCLK0SelCKDCLK0EN

3128272625242322212019181716DCLK1CMP DCLK1DIV DCLK1SEL DCLK1EN

DCLKCON---DDCLK1(0)SelCK---DCLK1(0) source clock 0 PCLK1UCLK ( USB )DCLK1(0)EN---DCLK1(0) Enable01

151211109876543210DCLK0CMPDCLK0DIVDCLK0SelCKDCLK0EN

3128272625242322212019181716DCLK1CMP DCLK1DIV DCLK1SEL DCLK1EN

10

Register Address R/W Description Reset Value EXTINT00x56000088 R/W 00x0 EXTINT10x5600008C R/W 10x0 EXTINT20x56000090 R/W 20x0

EINT0~7---00000101x10x11x37111519232731---EXTINT0---0

1514131211109876543210XEINT3XEINT2XEINT1XEINT0


EINT8~15---00000101x10x11x37111519232731---EXTINT1---1



EINT16~23---00000101x10x11x37111519232731---FILTEN01EXTINT2---2

1514131211109876543210F19EINT19F18EINT18F17EINT17F16EINT16

31302928272625242322212019181716F23EINT23F22EINT22F21EINT21F20EINT20

11

Register Address R/W Description Reset Value EINTFLT00x56000094 R/W - EINTFLT10x56000098 R/W - EINTFLT20x5600009C R/W 20x0EINTFLT30x560000A0R/W30x0

FLTCLK16~19---16~190PCLK1/OMEINTFLT16~19---16~19EINTFLT2---2

15148760FLTCLK17EINTFLT17FLTCLK16EINTFLT16


FLTCLK20~23---20~230PCLK1/OMEINTFLT20~23---20~23EINTFLT3---3



12

Register Address R/W Description Reset Value EINTMAK0x560000A4 R/W 0x00FFFFF0 EINTPEND0x560000A8 R/W 0x0

01 EINT0--- EINT3SRCPND

23EINT2315EINT157EINT722EINT2214EINT146EINT621EINT2113EINT135EINT520EINT2012EINT124EINT419EINT1911EINT11318EINT1810EINT10217EINT179EINT9116EINT168EINT80

0110.

23EINT2315EINT157EINT722EINT2214EINT146EINT621EINT2113EINT135EINT520EINT2012EINT124EINT419EINT1911EINT11318EINT1810EINT10217EINT179EINT9116EINT168EINT80

GSTATUS340

13

Register Address R/W Description Reset Value GSTATUS00x560000AC R GSTATUS10x560000B0 RID()0x32410000GSTATUS20x560000B4 R/W0x1GSTATUS30x560000B8R/W0x0GSTATUS40x560000C0R/W0x0

nWEIT---nWEIT

nCON---nCON

RnB---R/nB

nBATT_FLT---nBATT_FLT

01GSTATUS0---

3143210 nWEITnCONRnBnBATT_FLT

WDTRST---10OFFRST---10PWRST---10GSTATUS2---13

313210 WDTRSTOFFRSTPWRST

static void __irq Eint0Int(void){ ClearPending(BIT_EINT0); Uart_Printf("EINT0 interrupt is occurred.\n");}

static void __irq Eint1Int(void){ ClearPending(BIT_EINT1); Uart_Printf("EINT1 interrupt is occurred.\n");}

#define ClearPending(bit) {\rSRCPND = bit;\ rINTPND = bit;\ rINTPND;\ }

void Test_Eint(void){ int i; int extintMode;//

Uart_Printf("[External Interrupt Test]\n");

Uart_Printf("1.L-LEVEL 2.H-LEVEL 3.F-EDGE 4.R-EDGE 5.B-EDGE\n"); Uart_Printf("Select the external interrupt type.\n"); extintMode=Uart_Getch();

//extintMode='3'; rGPFCON = (rGPFCON & 0xfffa)|(1

switch(extintMode) { case '1': rEXTINT0 = (rEXTINT0 & ~((7

case '4': rEXTINT0 = (rEXTINT0 & ~((7

Uart_Printf(Press the EINT0/1 buttons or Press any key to exit.\n);//

pISR_EINT0=(U32)Eint0Int;// pISR_EINT1=(U32)Eint1Int;;// rEINTPEND = 0xffffff; //EINTPND EINTPND rSRCPND = BIT_EINT0|BIT_EINT1; //to clear the previous pending states rINTPND = BIT_EINT0|BIT_EINT1;

rINTMSK=~(BIT_EINT0|BIT_EINT1);

Uart_Getch();

rEINTMASK=0xffffff; rINTMSK=BIT_ALLMSK;} void Test_Eint(void)#define BIT_ALLMSK (0xffffffff)

4.4.2 FIQI/OIRQ I/ODMADMAI/O

1 CPUCPU

1 CPUACK 2CPU

1 GPIO GPIOI/O S3C44BOX301,6,6UART,8,4DMA,2RTC,1ADC,1IIC1SIO

S3C44B0X S3C44B0XFIQIRQ 0X180X1C

2(1)(2)(3)(4)(5)IRQ(6)IRQ/FIQ(7)(8)

3(reset)

ARM PC ARM ARM084

4 (1) I/O PGPG47PG3: rPCONG= 11 11 11 11 xx xxxxxxB: rPUPG= 0000xxxxB (2):

: rEXTINT= 01x 01x 01x 01x xxx xxxxxxxxxB;: rEXTINT=10x 10x 10x 10x xxx xxxxxxxxxB;: rEXTINT=11x 11x 11x 11x xxx xxxxxxxxxB;: rEXTINT=000 000 000 000 xxx xxxxxxxxxB;

2S3C2410

S3C2410X5624DMAUARTIICS3C2410XARM920TIRQFIQCPU

1S3C2410X

4

385

Register Address R/W Description Reset Value SRCPND0x4A000000 R/W 0x00000000 INTMOD 0x4A000004 R/W 0x00000000 INTMSK0x4A000008 R/W 0xFFFFFFFF PRIORITY0x4A00000CR/W 0x7FINTPND0x4A000010 R/W 0x00000000 INTOFFSET0x4A000014R0x00000000 SUBSRCPND0x4A000018R/W 0x00000000INTSUBMSK0x4A00001CR/W 0x7FF

1001.SRCPND---

31INT_ADC23INT_UART115INT_UART27nBATT_FLT30INT_RTC22INT_SPI014INT_TIM4629INT_SPI121INT_SDI13INT_TIM35EINT8_2328INT_UART020INT_DMA312INT_TIM24EINT4_727INT_IIC19INT_DMA211INT_TIM13EINT326INT_USBH18INT_DMA110INT_TIM02EINT225INT_USBD17INT_DMA09INT_WDT1EINT12416INT_LCD8INT_TICK0EINT0

FIQIRQ1FIQ0IRQINTMOD---


10INTMSK---


PRIORITY---ARB_SELn---n00REQ0, 1, 2, 3, 4, 5 01REQ0, 2, 3, 4, 1, 510REQ0, 3, 4, 1, 2, 5 11REQ0, 4, 1, 2, 3, 5ARB_MODEn---n0 1REQ0REQ5

31:21 12:11ARB_SEL24ARB_MODE420:19ARB_SEL610:9ARB_SEL13ARB_MODE318:17ARB_SEL58:7ARB_SEL02ARB_MODE216:15ARB_SEL46ARB_MODE61ARB_MODE114:13ARB_SEL35ARB_MODE50ARB_MODE0

10010SRCPNDINTPND---


INTPND1INTPNDSRCPNDINTPND00INTOFFSET---

INT_ADC31INT_UART123INT_UART215nBATT_FLT7INT_RTC30INT_SPI022INT_TIM4146INT_SPI129INT_SDI21INT_TIM313EINT8_235INT_UART028INT_DMA320INT_TIM212EINT4_74INT_IIC27INT_DMA219INT_TIM111EINT33INT_USBH26INT_DMA118INT_TIM010EINT22INT_USBD25INT_DMA017INT_WDT9EINT1124INT_LCD16INT_TICK8EINT00

SUBSRCPND---1010

31:11 7INT_TXD23INT_RXD110INT_ADC6INT_RXD22INT_ERR09INT_TC5INT_ERR11INT_TXD08INT_ERR24INT_TXD10INT_RXD0

INTSUBMSK---10

31:11 7INT_TXD23INT_RXD110INT_ADC6INT_RXD22INT_ERR09INT_TC5INT_ERR11INT_TXD08INT_ERR24INT_TXD10INT_RXD0

2410init.s

bResetHandler bHandlerUndef;handler for Undefined modebHandlerSWI;handler for SWI interruptbHandlerPabort;handler for PAbortbHandlerDabort;handler for DAbortb.;reservedbHandlerIRQ;handler for IRQ interrupt bHandlerFIQ;handler for FIQ interrupt

LTORG ;HandlerFIQ HANDLER HandleFIQHandlerIRQ HANDLER HandleIRQHandlerUndef HANDLER HandleUndefHandlerSWI HANDLER HandleSWIHandlerDabort HANDLER HandleDabortHandlerPabort HANDLER HandlePabort

; MACRO$HandlerLabel HANDLER $HandleLabel;Label=IRQ , ( HandlerIRQ )$HandlerLabelsubsp,sp,#4stmfdsp!,{r0} ldr r0,=$HandleLabel ldr r0,[r0]str r0,[sp,#4]ldmfd sp!,{r0,pc}MEND

IRQIsrIRQ subspsp#4 ;reserved for PCstmfdsp!{r8-r9}

ldrr9=INTOFFSET;ldrr9[r9]ldrr8=HandleEINT0;addr8r8r9lsl #2ldrr8[r8]strr8[sp#8]ldmfdsp!{r8-r9pc}

;IntVectorTableHandleEINT0 # 4HandleEINT1 # 4HandleEINT2 # 4HandleEINT3 # 4HandleEINT4_7# 4HandleEINT8_23# 4HandleRSV6# 4HandleBATFLT # 4HandleTICK # 4HandleWDT# 4HandleTIMER0 # 4HandleTIMER1 # 4

4.4.3 CPUCPU

1UART UARTUARTTTLRS-232

1S3C44BOXUART S3C44B0X UARTDMA115.2kbps, 16FIFO UART

2 S3C2410UART S3C2410 UARTI/O UART0UART1UART2DMA UART230.4kbpsUART PCLKUCLK116 FIFO S3C2410 3UART1.0 UART0UART1MODEMFIFO TxDnRxDnFIFO

2

15 8 112ULCONn0 0 FIFO FIFO

UART S3C2410 PCLKUCLK UBRDIVnUBRDIVn UBRDIVn=(int)CLK/ f B*16 1 CLK f Bf B= CLK/16/ UBRDIVn 1 115200bps PCLK UCLK 40MHz,UBRDIVn UBRDIVn =int(40000000)(115200*16)) 1 = (int)(21.7) 1 = 21 1 = 20

UART10bit1.873/160t_true = (UBRDIVn + 1)1610 / PCLK10bit t_ideal = 10 / baud_rate10UART error( ( t_true t_ideal ) / t_ideal )100%

UART0UART1UMCONnnRTSnCTSFIFOnRTSnCTSnRTSnCTSUARTMODEM

FIFO

FIFOUFSTATnFIFO1DMA2MODEMUMSTATn[0]1FIFOUFSTATn11UTXHnFIFO1DMA2FIFOUFSTATn11MODEMMCONn1UARTnnRTSUFSTATn1

FIFO/UTRSTATnDMAMODEMUMSTATn[0]1/UTRSTATn[1]11UTXHnDMA/UTRSTATn[0]11MODEMMCONn1UARTnnRTSUFSTATn1

DMA

UART37DMA73 FIFOFIFORx FIFOFIFO FIFOTx FIFO

4FIFO FIFORx FIFO12DMADMA3

S3C2410XUARTTXDRXD

2UART

3UART1129

Register Address R/W Description Reset Value ULCONn0x5000x000 R/W 0x00UCONn0x5000x004 R/W 0x00UFCONn 0x5000x008 R/W FIFO0x00UMCONn0x5000x00C R/W MODEM*0x00UTRSTATn0x5000x010R/0x6UERSTATn0x5000x014 RRx0x0UFSTATn0x5000x018 RFIFO0x00UMSTATn0x5000x01C RMODEM*0x0UTXHn0x5000x020/23 W - URXHn 0x5000x024/27 R-UBRDIVn0x5000x028R/W-

1ULCON

Register Address R/W Description Reset Value ULCON00x50000000 R/W UART00x00ULCON10x50004000 R/W UART10x00ULCON20x50008000 R/W UART20x00

-7 0Infra-Red-Mode6 0:1:0Parity Mode5:3 0xx 100 101 1101 1110000Num of stop bit2 01120Word Length1:0 005 016 107 11800

2UCON

Register Address R/W Description Reset Value UCON00x50000004 R/W UART00x00UCON10x50004004 R/W UART10x00UCON20x50008004 R/W UART20x00

2UCON

Clock Selection100PCLK1UCLK0Tx Int Type90 10Rx Int Type80 10Rx Time OV Ena7010Rx ERR Int Ena6010Loopback Mode50 = 1 = 0Send Break Signal4 0 = 1 = 0 0Transmit Mode3:2 /00/ 0110UART02DMA0DMA311UART1DMA100Receive Mode1:000

3FIFOUFCON

Register Address R/W Description Reset Value UFCON00x50000008 R/W UART0 FIFO0x00UFCON10x50004008 R/W UART1 FIFO0x00UFCON20x50008008 R/W UART2 FIFO0x00

3FIFO

Tx FIFO Tri Leve7:6 Tx FIFO 00 014108111200lRx FIFO Tri Level5:4 Rx FIFO 004 018 101211 1600reserved3 0Tx FIFO Reset2 Tx FIFO010Rx FIFO Reset1 Rx FIFO010FIFO Enable0 FIFO 010

4MODEMUMCON

Register Address R/W Description Reset Value UMCON00x5000000C R/W UART0 FIFO0x00UMCON10x5000400C R/W UART1 FIFO0x00reserved0x5000800C - -

reserved7:50000Auto Flow Control (AFC)4 010reserved3:10000Request to Send0 nRTS 0nRTS 1nRTS0

5/UTRSTAT

Register Address R/W Description Reset Value UTRSTAT00x50000010 RUART00x06UTRSTAT10x50004010 RUART10x06UTRSTAT20x50008010 RUART20x06

Transmitter empty2 0 11Transmitbuffer empty1 01 FIFODMA1Receive buffer data ready0 01 FIFODMA0

6RxUERSTAT

Register Address R/W Description Reset Value UERSTAT00x50000014 RUART0Rx0x0UERSTAT10x50004014 RUART1Rx0x0UERSTAT20x50008014 RUART2Rx0x0

Break Detect 3 0 1()0Frame Error2 0 1()0Parity Error 1 0 1()0Overrun Error0 0 1()0

7FIFOUFSTAT

Register Address R/W Description Reset Value UFSTAT00x50000018 RUART0 FIFO0x00UFSTAT10x50004018 RUART1 FIFO0x00UFSTAT20x50008018 RUART2 FIFO0x00

Reserved15:10 00Tx FIFO Full9 FIFO 0 10Rx FIFO Full8 FIFO 0 10Tx FIFO Count7:4 FIFO0Rx FIFO Count3:0 FIFO0

8MODEMUMSTAT

Register Address R/W Description Reset Value UMSTAT00x5000001C RUART0 Modem0x0UMSTAT10x5000401C RUART1 Modem0x0Reserved0x5000801C R-

Reserved3 00Delta CTS 2 nCTS 010Reserved1 00Clear to Send0 nCTS 0nCTS 1nCTS0

9UTxH

Register Address R/W Description Reset Value UTxH00x50000020(L)0x50000023(B)W(byte)UART0 -UTxH10x50004020(L)0x50004023(B)W (byte)UART1-UTxH20x50008020(L)0x50008023(B)W (byte)UART2-

Tx DATAn7:0 UARTn-

10URxH

Register Address R/W Description Reset Value URxH00x50000024(L)0x50000027(B)R(byte)UART0 0x00URxH10x50004024(L)0x50004027(B)R (byte)UART10x00URxH20x50008024(L)0x50008027(B)R (byte)UART20x00

Rx DATAn7:0 UARTn-

11UBRDIV

Register Address R/W Description Reset Value UBRDIV00x50000028 R/WUART0 -UBRDIV10x50004028 R/WUART1 -UBRDIV20x50008028 R/WUART2 -

UBRDIV15:0 UBRDIVn >0-

3UART S3C2410XUART2/FIFO81125kb/sPclk50MHzUART21 UBRDIVn=(int)CLK/ f B*16 1 Pclk=50MHz f B = 125kb/s UBRDIVn=25 -1=242UART2 ULCON2=0b 0 000 0 11=0x03 1 8

UCON2=0b 0 0 0 0 0 0 0 01 01=0x05Pclk//FIFOUFCON2=0b 10 01 0 0 0 1=0x91/FIFO80/FIFOFIFO3 TxD2RxD2GPH6GPH7GPHGPHCON0b 1 0 1 0 GPHCON= GPHCON&~(0xF

4INTMOD&=~(1

2RS-232-C RS-232-CDTEDCE()9D2500P3K7K-3V-15V+3V+15V

(1) ;; ;

(3)RS-232 UARTRS-232nRTSnCTSnDSRnDTRnDCDNri 3.3V TTL RS-232-CSP3243MAX32231 -3V-15V0+3V+15V

RS232 9

RS232 3

(4)PCPC

PC

2

3

5

2

3

5

RS-232

RS-232

PC RS232LVTTLLVTTL12V3.3V00V0.4VRS232C1-3V-15V0+3V+15VMAX3223

3SPISPIMotorola4SCLKSDISDOCS5MbpsSPIMSB)LSB)CS

4.4.4 USB USBUniver Serial BusIntelCompaqMicrosoftPC199621.0200042.0 USBUSBS3C2410USBUSBS3C44B0

1 USB (1) (2):USB1.1 1.5Mb/s12Mb/s USB2.0480Mb/sUSB 2.0USB1.1USB 2.0USB 1.11.5Mb/s12Mb/s480Mb/s USB4

(3):Hub127USB (4):USB USBUSBUSBUSBUSBUSB USBUSB

2USB5USBUSBUSBUSB

34 1 2 3 4USB

4USB USBHOSTUSBCypressSL811DeviceUSBPhilipsPDIUSBD12Device USBPCUSB HOSTUSBU

1USBhostUSBUSB.2USBdeviceUSB

S3C2410USB HOST

S3C2410USB DEVICE

6S3C2410USB

S3C2410USB HOSTUSB host 1USB Device1USB USB 1.1 USB(1.5Mb/s)(12Mb/s)

5FIFO116FIFOEP0464FIFOEP1---EP4DMAEP1---EP4USB

2S3C2410USB

5USB5FIFO4DMAUSB

3USB DEVICE

460x52000000

FUNC_ADDR_REG140 PWR_REG144 EP_INT_REG(EP0EP4)0---4148 USB_INT_REGUSB158 EP_INT_EN_REG (EP0EP4)15C USB_INT_EN_REGUSB16C

USB DEVICE1

FRAME_NUM1_REG170 FRAME_NUM2_REG174 INDEX_REG178 EP0_FIFO_REG0 FIFO 1C0 EP1_FIFO_REG1 FIFO 1C4 EP2_FIFO_REG2 FIFO 1C8 EP3_FIFO_REG3 FIFO 1CC EP4_FIFO_REG4 FIFO 1D0

USB DEVICE2

n=1234424

EPn_DMA_CONn DMA2xxEPn_DMA_UNITn DMA2xxEPn_DMA_FIFOn DMA FIFO2xxEPn_DMA_TTC_Ln DMAL2xxEPn_DMA_TTC_Mn DMAM2xxEPn_DMA_TTC_Hn DMAH2xx

USB DEVICE3

IN_CSR1_REG /EP0_CSR1/0184 IN_CSR2_REG2188 MAXP_REG18C OUT_CSR1_REG1190 OUT_CSR2_REG2194 OUT_FIFO_CNT1_REG1198 OUT_FIFO_CNT2_REG219C

4.4.5 JTAG 1JTAG JTAGJoint Test Action GroupIEEE1149.1bootloaderJTAGTAPTest Access Port,)JTAG JTAG1420

1JTAG JTAGPCBJTAGARMI/O

2) JTAG 1 2 3JTAGI/OFlash 4

2) JTAG5 IEEE 1149.1ARMARM7ARM9ARM10Xscale ATMELSumsungIntelPhilipSharpJTAG

3)ARMJTAG JTAGPCJTAGJTAGJTAG JTAGJTAGJTAGJTAGTDOTDIJTAG

JTAG JTAG(BSCJTAGTDITDOBSCTDI JTAGJTAG

4JTAG14VCC113GND24681014nTRST3JTAGJTAGMacro cellTDI5TMS7 Test Mode SelectTMSJTAGTCK9 JTAGTDO11 NC12

JTAG14

JTAG 20

5 ARM JTAGJTAG ADS V1.2ARM JTAG ARM

JTAG14

4.4.6 A/D ADCA/DDACD/A

1A/D A/DSARD/ASARD/AVc,VxSAR10SARSAR10D/AVcVcVx

A/D VAD/A

A/D VxVcSAR1Vx

2 S3C440BXA/D S3C440BXA/D810SARSleep100Ksps0-2.5V100-100HZ/ ARMA/DAIN[7:0]8,ADCAREFTAREFBAVCOM

3S3C2410XA/D

S3C2410X10 A/D A/D S3C2410XA/D A/D101LSB 1.5---2.0LSB500KSPS0~3.3v/X/Y

1A/D

S3C2410 A/D 1

681A/D

2

1A/D PCLK 50MHz4910 A/D =50MHz /49+1=1MHz=1/1MHz/5 =1/200KHz=5usA/D 2.5MHz 500KSPS

23

XXPX+XMX-YPnYPON=1nYMON=0nXPON=0nXMON=1YX

YYPY+YMY-XPnYPON=0nYMON=1nXPON=1nXMON=0YX

2S3C24120X A/D

5X/YX/Y2---41A/DADCDAT0XPDATA2X/YX/YADCDAT0XPDATAADCDAT1YPDATAINT_ADC3X/YXYADCDAT0XPDATAADCDAT1YPDATAINT_ADC

4INT_TCX/YX/YXP=XM=YP=AIN[5]YM=5ADCCONSTDBM1A/D

3ADC

5

Register Address R/W Description Reset Value ADCCON0x58000000 R/W ADC 0x3FC4 ADCTSC 0x58000004 R/W 0x058 ADCDLY0x58000008 R/W ADC0x00FF ADCDAT00x5800000CRADC0-ADCDAT10x58000010 RADC1-

ECFLG---01PRSCEN---01PRSCVL---N1---2551N+1 2N

SEL_MUX ---000AIN0001AIN1010AIN2011AIN3111AIN7STDBM---01A/DREAD_START---01ENABLE_START---01A/D0READ_START1

543210SEL_MUXSTDBMREAD_STARTENABLE_START

YM_SEN---YMON00YM=1 1YM=GNDYP_SEN---nYPON00YP=11YPAIN[5]XM_SEN---XMON00 XM=1 1XM=GNDXP_SEN---nXP00XP=11XPAIN[7]2ADCTSC---ADC

8765432100YM_SENYP_SENXM_SENXP_SENPULL_UPAUTO_PSTXY_PST

PULL---0XP1 XPAUTO_PST---XY0A/D1X/YXY_PST---XY0001X10X11

8765432100YM_SENYP_SENXM_SENXP_SENPULL_UPAUTO_PSTXY_PST

X/YX/Yms3ADCDLY---ADC

UPDOWN---01AUTO_PST---X/Y01X/YXY_PST---X/Y0001X10Y11XPDATA[90]XADC0---0x3FF4ADCDAT0---ADC011

1514131211109 0UPDOWNAUTO_PSTXY_PST0XPDATAADC

UPDOWN---01AUTO_PST---X/Y01X/YXY_PST---X/Y0001X11Y11YPDATA[90]10Y0---0x3FF 5ADCDAT1---ADC1

1514131211109 0UPDOWNAUTO_PSTXY_PST0YPDATA

3100x400000AREA ADCCODEREADONLYENTRYSTART

#define rADCCON (*(volatile unsigned *)0x58000000)#define rADCDAT0 (*(volatile unsigned *)0x5800000c)#define pref 49#define ch 3void adc(void){int adc_data[10], i; rADCCON=(1

4.4 处理器接口电路、中断系统的设计

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