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6-1 6-2 6-3 6-4 6-5 6-6 6-7 ( ) 6-8 6-9 / Slide 2 P309 A B Slide 3 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Pp286 half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). Half-Adder A B C out The logic symbol and equivalent circuit are: A B C out Slide 4 P310 Slide 5 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Full-Adder pp288a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. A full-adder can be constructed from two half adders as shown: A B C out A B A B Sum C out C in A B C out C in Symbol Slide 6 P313 6-2 2 bits Slide 7 P315 4 Slide 8 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parallel Adders Pp291 Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. AB C out C in AB C out C in AB C out C in AB C out C in A 1 B 1 C0C0 C1C1 C2C2 C3C3 C4C4 A 2 B 2 A 3 B 3 A 4 B 4 The output carry (C 4 ) is not ready until it propagates through all of the full adders. This is called ripple carry, delaying the addition process. Slide 9 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Parallel Adders pp292The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled (C 0 ) and a Carry out (labeled C 4 ). The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the output carry delay. For the 74LS283, the maximum delay to the output carry is 17 ns. Binary number A Binary number B Input carry 4-bit sum Output carry 12341234 12341234 12341234 C0C0 C4C4 Slide 10 P367 Slide 11 Slide 12 P318 6-3 XOR 4 8 Slide 13 P319 Slide 14 2 Bit Magnitude Comparator Slide 15 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Comparators pp300. In the simplest form, a comparator can test for equality using XNOR gates. How could you test two 4-bit numbers for equality? AND the outputs of four XNOR gates. A1B1A1B1 A2B2A2B2 A3B3A3B3 A4B4A4B4 Output Slide 16 P320 Slide 17 4 P321 Slide 18 P323 Slide 19 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Comparators pp302IC comparators can be expanded using the cascading inputs as shown. The lowest order comparator has a HIGH on the A = B input. Outputs A1A1 A0A0 A2A2 A3A3 B1B1 B0B0 B2B2 B3B3 COMP A = B A < B A > B A = B A < B A > B 0 0 3 3 A A A5A5 A4A4 A6A6 A7A7 B5B5 B4B4 B6B6 B7B7 +5.0 V COMP A = B A < B A > B A = B A < B A > B 0 0 3 3 A A LSBsMSBs Slide 20 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Decoders pp3004A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence of the binary code 0011 are shown. The first has an active HIGH output; the second has an active LOW output. A1A1 A0A0 A2A2 A3A3 X Active HIGH decoder for 0011 A1A1 A0A0 A2A2 A3A3 X Active LOW decoder for 0011 Slide 21 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Decoders Assume the output of the decoder shown is a logic 1. What are the inputs to the decoder? Slide 22 Slide 23 2-Line-to-4-Line Decoder Slide 24 Figure 5.8 Slide 25 Truth Table for 3 to 8 Decoder Output Y1 ~Y7: Active LOW Input D0~D2 Slide 26 4 P325 Slide 27 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Decoders pp306A specific integrated circuit decoder is the 74HC154 (shown as a 4-to-16 decoder). It includes two active LOW chip select lines which must be at the active level to enable the outputs. These lines can be used to expand the decoder to larger inputs. CS 2 A1A1 A0A0 A2A2 A3A3 CS 1 X/Y EN 74HC154 Slide 28 4 P326 6-8 5 4 16 (16 1) 16 1 4 5 5 A4 6-21 15 15 Slide 29 4 P326 6-8 ( ) 10110 6-21 6-21 16 1 5 Slide 30 Seven Segment Decoder/Drivers I Slide 31 Slide 32 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver Pp310 Another useful decoder is the 74LS47. This is a BCD-to-seven segment display with active LOW outputs. The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). BCD inputs Outputs to seven segment device GND V CC BCD/7-seg BI/RBO LT RBI LT RBI 74LS47 Slide 33 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver pp310 Here the 7447A is an connected to an LED seven segment display. Notice the current limiting resistors, required to prevent overdriving the LED display. Slide 34 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver Blanked pp311 The 74LS47 features leading zero suppression, which blanks unnecessary leading zeros but keeps significant zeros as illustrated here. The BI/RBO output is connected to the RBI input of the next decoder. Depending on the display type, current limiting resistors may be required. Slide 35 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed BCD Decoder/Driver Blanked Decimal point pp311 Trailing zero suppression blanks unnecessary trailing zeros to the right of the decimal point as illustrated here. The RBI input is connected to the BI/RBO output of the following decoder.