8086 lecture notes 10

1INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE

611 37100 Lecture 10-2

INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE

10.1 Core and Special-Purpose I/O Interfaces10.2 Byte-Wide Output Ports Using Isolated

I/O10.3 Byte-Wide Input Ports Using Isolated I/O10.4 Input/Output Handshaking and a

Parallel Printer Interface10.5 82C55A Programmable Peripheral

Interface10.6 82C55A Implementation of Parallel

Input/Output Ports

611 37100 Lecture 10-3

INPUT/OUTPUT INTERFACE CIRCUITS AND LSI PERIPHERAL DEVICE

10.7 Memory-Mapped Input/Output Ports10.8 82C54 Programmable Interval Timer10.9 82C37A Programmable Direct Memory

Access Controller10.10 Serial Communication Interface10.11 Programmable Communication

Interface Controller10.12 Keyboard and Display Interface10.13 8279 Programmable Keyboard/Display

Controller

611 37100 Lecture 10-4

10.1 Core and Special-Purpose I/O Interfaces

Special-Purpose I/O interfacesKeyboard interfaceDisplay interfaceParallel printer interfaceSerial communication interfaceLocal area network interface

Core I/O interfacesParallel input/output portsInterval timersDirect memory access control

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10.2 Byte-Wide Output Ports Using Isolated I/O

Sixty-four-line parallel output circuit for an 8088-based microcomputer

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1XXXXXXXXXXX11102Port 71XXXXXXXXXXX11002Port 61XXXXXXXXXXX10102Port 51XXXXXXXXXXX10002Port 41XXXXXXXXXXX01102Port 31XXXXXXXXXXX01002Port 21XXXXXXXXXXX00102Port 11XXXXXXXXXXX00002Port 0

I/O AddressI/O Port

I/O Address decoding for ports 0 through 7

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Sixty-four-line parallel output circuit for an 8086-based microcomputer

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EXAMPLETo which output port in the 8088-based microcomputer are

data written when the address put on the bus during an output cycle is 800216? Solution:

Express the address in binary form, we getA15A0 = A15LA0L = 10000000000000102

That is A15L = 1, A0L = 0 and A3LA2LA1L = 001Moreover, whenever an output bus cycle is in progress, IO/M is logic 1, Therefore the enable inputs of the 74F138 decoder are

G2B = A0L = 0G2A = IO/M = 0G1 = A15L = 1

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These inputs enable the decoder for operation. At the same time,its select inputs are supplied with the code 001. This input causes output P1 to switch to logic 0:

P1 = 0

The gate at the CLK input of port 1 has as its inputs P1 and WR. When valid output data are on the bus, WR switches to logic 0. Since P1 is also 0, the CLK input of the 74F374 for port 1 switches to logic 0. At the end of the WR pulse, the clock switches from 0 to 1, a positive transition. This causes the data on D0 through D7 to be latched and become available at output lines O8 through O15 of port 1.

611 37100 Lecture 10-10


EXAMPLEWrite a series of instructions that will output the byte contents

of the memory address DATA to output port 0 in the circuit shownin the previous figure of the 8088-base microcomputer.

Solution:To write a byte to output port 0, the address is

A15A14 A0 = 1XXXXXXXXXXX00002Assuming that the dont-care bits are all made logic 0, we get

A15A14 A0 = 10000000000000002 = 800016The instruction sequence is

MOV DX, 8000HMOV AL, [DATA]OUT DX, AL

611 37100 Lecture 10-11


Time-delay loop and blinking an LED at an output port

Driving an LED connected to an output port

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Time-delay loop and blinking and LED at an output port

MOV DX, 8000H ; Initialize address of port 0MOV AL, 00H ; Load data with bit 7 as logic 0

ON_OFF OUT DX, AL ; Output the data to port 0MOV CX, 0FFFFH ; Load delay count of FFFFH

HERE: LOOP HERE ; Time delay loopXOR AL, 80H ; Complement bit 7 of ALJMP ON_OFF ; Repeat to output the new bit 7

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10.3 Byte-Wide Input Ports Using Isolated I/O

Sixty-four-line parallel input circuit for an 8088-based microcomputer

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EXAMPLEWhat is the I/O address of port 7 in the circuit of the previous

figure? Assume all unused address bits are at logic 0

Solution:For the I/O address decoder to be enable, address bits A15 and

A0 must beA15 = 1 and A0 = 0

To select port 7, the address applied to the CBA inputs of the decoder must be

A3LA2LA1L = 111Using 0s for the unused bits gives the address

A15 A1LA0L = 10000000000011102 = 800E16

611 37100 Lecture 10-15


EXAMPLEFor the circuit in the previous figure, write an instruction

sequence that inputs the byte contents of input port 7 to the memory location DATA_7

Solution:In the previous example we found that the address of port 7 is

800E16. This address is loaded into the DX register byMOV DX, 800EH

Now the contents of this port are input to the AL register byIN AL, DX

Finally, the byte of data is copied to memory location DATA_7 byMOV DATA_7, AL

611 37100 Lecture 10-16


Polling the setting of a switch

Reading the setting of a switch connected to an input port

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Polling the setting of a switch

MOV DX, 8000H POLL_I7: IN AL, DX

SHL AL, 1JC POLL_I7

CONTINUE:

611 37100 Lecture 10-18

10.4 Input/Output Handshaking and a Parallel Printer Interface

I/O synchronization is achieved by implementing what is known as handshaking as part of the input/output interface.

Three general types of signals at the printer interface: Data Control Status

ParallelPrinter

Port

Data

PrinterControl

Status

Parallel printer interface

Status

Send data

Send control

True

False

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Parallel printer port in assignments and types of interface signals

Select13Paper Empty12

Busy11Ack10

Data 79Data 68Data 57Data 46Data 35Data 24Data 13Data 02Strobe1

AssignmentPin

Ground25Ground24Ground23Ground22Ground21Ground20Ground19Ground18Slctin17

Initialize16Error15

Auto Foxt14AssignmentPin

Data: Data0, Data1, , Data7

Control: StrobeAuto FoxtInitializeSlctin

Status: AckBusyPaper EmptySelectError

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I/O interface that employs handshaking

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Handshake sequence flowchart

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Handshaking printer interface circuit

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EXAMPLEWhat are the addresses of the ports that provide the data lines,

strobe output, and busy input in the circuit shown in the previous figure? Assume that all unused address bits are 0s.

Solution:The I/O address that enable port 0 for the data lines, port 1 for

the strobe output, and port 2 for the busy input are found as follows:

Address of port 0 = 10000000000000002 = 800016Address of port 1 = 10000000000000102 = 800216Address of port 2 = 10000000000001002 = 800416

611 37100 Lecture 10-24


EXAMPLEWrite a program that will implement the sequence for the

circuit in the previous figure. Character data are held in memory starting at address PRNT_BUFF, and the number of characters held in the buffer is identified by the count at address CHAR_COUNT. Use the port address from the previous example.

Solution:First, the character counter and the character points are setup

with the instructionsMOV CL, CHAR_COUNT ; (CL) = character countMOV SI, PRNT_BUFF ; (SI) = character pointer

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Next, the BUSY input is checked with the instructionsPOLL_BUSY MOV DX, 8004H ; Keep polling till busy = 0

IN AL, DXAND AL, 01HJNZ POLL_BUSY

The character is copied into AL, and then it is output to port 0:MOV AL, [SI] ; Get the next characterMOV DX, 8000HOUT DX, AL ; and output it to port 0

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Now, a strobe pulse is generated at port 1 with the instructionsMOV AL, 00H ; STB = 0MOV DX, 8002HOUT DX, ALMOV BX, 0FH ; Delay for STB duration

STROBE: DEC BXJNZ STROBEMOV AL, 01H ; STB = 1OUT DX, AL

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At this point, the value of PRNT_BUFF must be incremented, and the value of CHAR_COUNT must be decremented:

INC SI ; Update character counterDEC CL ; and pointer

Finally, a check is made to see if the printer buffer is empty. If it is not empty, we need to repeat the prior instruction sequence. To do this, we execute the instruction

JNZ POLL_BUSY ; Repeat till all character; have been transferred

DONE: -The program comes to the DONE label after all characters are transferred to the printer

611 37100 Lecture 10-28

10.5 82C55A Programmable Peripheral Interface

The 82C55A is an LSI peripheral designed to permit easy implementation of parallel I/O in the 8088- and 8086-microcomputer system.

Flexible parallel interface: Single-bit, 4-bit, and byte-wide input and output ports Level sensitive inputs Latched outputs Strobed inputs or outputs Strobed bidirectional input/outputs

Timing of the data transfers to the 82C55A is controlled by the read/write control (RD and WR) signals.

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Block diagram and pin layout of the 82C55A

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The source or destination register within the 82C55A is selected by a 2-bit register select code (A1A0).

The chip-select (CS) input must be logic 0 during all read or write operations to the 82C55A.

The reset (RESET) is used to initialize the 82C55A. Three byte-wide ports (port A, port B, port C) can be

configured for input or output operation. This gives us a total of 24 I/O lines.

The 82C55A contains an 8-bit internal control register for software control.

A write bus cycle to the 82C55A with register-select code A1A0 = 11, and an appropriate control word is used to modify the control register.

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Addressing an 82C55A using the microcomputer interface signals

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EXAMPLEWhat is the addresses of port A, port B, port C of the 82C55A

device?

Solution:To access port A, A1A0 = 00, A15 = A14 = 1, A13 = A12 = = A2

= 0, which gives the port A address as

1100 0000 0000 00002 = C00016

Similarly, it can be determined that the address of port B equals C00116, that of port C is C00216, and the address of the control register is C00316.

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Control-word bit functions

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Mode 0 Simple I/O operation

Mode 0 port pin functions

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EXAMPLEWhat is the mode and I/O configuration for ports A, B, and C of

an 82C55A after its control register is loaded with 8216?

Solution:Expressing the control register contents in binary form, we get

D7D6D5D4D3D2D1D0 = 100000102Since D7 is 1, the modes of operation of the ports are selected by the control word.

D0 = 0 Lower four bits of port C are outputs.D1 = 1 Port B is an input port.D2 = 0 Mode 0 for both port B and the lower four

bits of port C.

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The next for bits configure the upper part of port C and port A:D3 = 0 Upper four bits of port C are outputs.D4 = 0 Port A is an output port.D6D5 = 00 Mode 0 for both port A and the upper four

bits of port C

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Mode 0 control words and corresponding input/output configurations.

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Mode 1 Strobed I/OIn mode 1, the A and B ports are configured as

two independent byte-wide I/O ports, each of which has a 4-bit control/data port associated with it. The control/data ports are formed from the lower and upper nibbles of port C, respectively.In mode 1, data applied to an input port must be

strobed in with a signal produced in external hardware.An output port in mode 1 is provided with

handshake signals that indicate when new data are available at its outputs and when an external device has read these values.

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Mode 1 Strobed I/O


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Mode 1 Strobed I/O

Mode 1, port A output and input configuration

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Mode 1 Strobed I/O

Mode 1, port A input and output timing diagram

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EXAMPLEThe following figures show how port B can be configured for

mode 1 operation. Describe what happens in the left figure when the STBB input is pulsed to logic 0. Assume that INTEB is already set to 1.

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SOLUTION:

As STBB is pulsed, the byte of data at PB7 through PB0 is latched into the port B register. This causes the IBFB output to switch to 1. Since INTEB is 1, INTRBswitches to logic 1.

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Mode 2 Strobed bidirectional I/O


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Mode 2 input/output configuration

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Mode 2 bit set/reset format

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EXAMPLEThe interrupt-control flag INTEA for output port A in mode 1 is

controlled by PC6. Using the set/reset feature of the 82C55A, what command code must be written to the control register of the 82C55A to set it to enable the control flag?

Solution:To use the set/reset feature, D7 must be logic 0. Moreover,

INTEA is to be set; therefore, D0 must be logic 1. Finally, to select PC6, the code at bits D3D2D1 must be 110. The rest of the bits are dont-care states. This gives us the control word

D7D6D5D4D3D2D1D0 = 0XXX11012Replacing the dont-care states with the 0 logic level, we get

D7D6D5D4D3D2D1D0 = 000011012 = 0D16

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Mixed modes

Combined mode 2 and mode 0 (input) control word and I/O configuration

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Mixed modes

Combined mode 2 and mode 1 (output) control word and I/O configuration

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EXAMPLEWhat control word must be written into the control register of

the 82C55A such that port A is configured for bidirectional operation and port B is set up with mode 1 outputs?Solution:

To configure the operating mode of the ports of the 82C55A, D7must be 1. Port A is set up for bidirectional operation by making D6logic 1. In this case, D5 through D3 are dont-care states:

D5D4D3 = XXX2Mode 1 is selected for port B by logic 1 in D2 and output operation by logic 0 in D1. D0 is a dont-care state.This gives the control word

D7D6D5D4D3D2D1D0 = 11XXX10X2= 110001002 = C416

611 37100 Lecture 10-54


EXAMPLEWrite the sequence of instructions needed to load the control

register of an 82C55A with the control word formed in the previous example. Assume that the control register of the 82C55A resides at address 0F16 of the I/O address space?Solution:

First we must load AL with C416 . This is the value of the control word that is to be written to the control register at address 0F16. The move instruction used to load AL is

MOV AL, 0C4HThese data are output to the control register with OUT instruction

OUT 0FH, ALBecause the I/O address of the control register is less than FF16, this instruction uses direct I/O.

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When the 82C55A is configured in mode 1 or mode 2 operations, most of the pins of port C perform I/O control functions.

Mode 1 status information for port C Mode 1 status information for port C

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10.6 82C55A Implementation of Parallel Input/Output Ports

82C55A parallel I/O ports in an 8088-based microcomputer

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EXAMPLEWhat must be the address bus inputs of the circuit in the

previous figure if port C of PPI 14 is to be accessed?Solution:

To enable PPI 14, the 74F138 must be enabled for operation and its O7 output switched to logic 0. This requires enable input G2B= 0 and chip select code CBA = 111. This in turn requires from the bus that

A0 = 0 to enable 74F138and A5A4A3 = 111 to select PPI 14Port C of PPI 14 is selected with A1A0 = 10, which from the bus requires that

A2A1 = 10The rest of the address bits are dont-care states.

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EXAMPLEAssume that in the previous figure, PPI 14 is configured so that

port A is an output port, both ports B and C are input ports, and all three ports are set up for mode 0 operation. Write a program that will input that data at port B and C, find the difference (port C) (port B), and output this difference to port A.Solution:

Port A address = 001110002 = 3816Similarly, Port B address = 3A16,, Port C address = 3C16Therefore, IN AL, 3AH ; Read port B

MOV BL, AL ; Save data from port BIN AL, 3CH ; Read port CSUB AL, BL ; Subtract B from COUT 38H, AL ; Write to port A

611 37100 Lecture 10-59


82C55A parallel I/O ports in an 8086-based microcomputer

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10.7 Memory-Mapped Input/Output Ports

The full 20-bit address is available for addressing I/O. Therefore, memory-mapped I/O devices can reside anywhere in the 1Mbyte memory address space of the 8088.

During I/O operations, memory read and write bus cycles are initiated instead of I/O bus cycles.

Memory instructions, not input/output instructions, are used to perform data transfer.

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Memory-mapped 82C55A parallel I/O ports in an 8088-based microcomputer

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EXAMPLEWhich I/O port in the previous figure is selected for operation

when the memory address output on the bus is 0040216?Solution:

We begin by converting the address to binary form. This givesA19A1A0 = 000000000100000000102

In this address, bits A10 = 1 and A0 = 0. Therefore, the 74F138 address decoder is enabled whenever IO/M = 0.

A5A4A3 = 000 This input code switches decoder output O0 to logic 0 and chip selects PPI 0 for operation.The address bits applied to the port select inputs of the PPI are A2A1 = 01. These inputs cause port B to be accessed. Thus, the address 0040216 selects port B on PPI 0 for memory-map I/O.

611 37100 Lecture 10-63


EXAMPLEWrite the sequence of instructions needed to initialize the

control register of PPI 0 in the circuit of the previous figure so that port A is an output port, ports B and C are input ports, and all three ports are configured for mode 0 operation.

Solution:The control byte required to provide this configuration is:

611 37100 Lecture 10-64


From the circuit diagram, the memory address of the control register for PPI 0 is found to be

000000000100000001102 = 0040616

Since PPI 0 is memory mapped, the following move instructions can be used to initialized the control register:

MOV AX, 0 ; Create data segment at 00000HMOV DS, AXMOV AL, 8BH ; Load AL with control byteMOV [406H], AL ; Write control byte to PPI 0 control

; register

611 37100 Lecture 10-65


EXAMPLEAssume that PPI 0 in the previous figure is configured as

described in the previous example. Write a program that will input the contents of ports B and C, AND them together, and output theresults to port A.Solution:

The addresses of the three I/O ports on PPI 0 are:Port A = 0040016 Port B = 0040216 Port C = 0040416

Now we set up a data segment at 0000016 and the program is:AND AX, 0 ; Create data segment at 00000HMOV DS, AXMOV BL, [402H] ; Read port BMOV AL, [404H] ; Read port CAND AL, BL ; AND data at port B and CMOV [400H], AL ; Write to port A

611 37100 Lecture 10-66


Memory-mapped 82C55A parallel I/O ports in an 8086-based microcomputer

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10.8 82C54 Programmable Interval Timer

Block diagram of the 82C54The 82C54 is an LSI peripheral designed to permit

easy implementation of timer and counter functions in a microcomputer system.The 82C54C can be memory-mapped into the

memory address space or I/O-mapped into the I/O address space.The microcomputer interface of the 82C54 allows

the MPU to read from and write into its internal registers.The 3 counters in 82C54 are each 16 bits in length

and operate as down counters.

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Block diagram of the 82C54

Block diagram and pin layout of the 82C54 interval timer

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Block diagram of the 82C54

Clock or pulse output of counter 0OUT0

Gate must be switched to logic 1 to enable the counter 0

GATE0

Pulses applied to the clock input are used to decrement counter 0

CLK0

Chip-select input to enable the 82C54s microprocessor interface

CS

Control signals indicating whether 82C54 is to be read from or written into

RD, WR

Register address inputs used to select the register to be accessed

A0, A1

8-bit bidirectional data busD7 D0

FunctionsSignals

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Architecture of the 82C54

Internal architecture of the 82C54 interval timer

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Control word format of the 82C54 interval timer

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EXAMPLEAn 82C54 receive the control word 100100002. What

configuration is set up for the timer?

Solution:SC bits = 10 indicating counter 2 is selected.RW bits = 01 sets counter 2 for the read/write sequence

identified as the least significant byte only.The mode code M2M1M0 is 000, this selects mode 0 operation for

counter 2.The last bit, BCD, is also set to 0 and selects binary counting.

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Accessing the registers of the 82C54 interval timer

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EXAMPLEWrite an instruction sequence to set up the three counters of

the 82C54 in the figure that follows:Counter 0: Binary counter operating in mode 0, value = 1234HCounter 1: BCD counter operating in mode 2, value = 0100HCounter 2: Binary counter operating in mode 4, value = 1FFFH

Solution:First, we need to determine the base address of the 82C54. The

base address, which is also the address of counter 0, is determined with A1A0 set to 00. In the figure, we find that to select 82C54, CS must be logic 0. This requires that

A15A14A7A6A5A2 = 000000000100002

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Combining this part of the address with the 00 at A1A0, gives the base address as

00000000010000002 = 40HSince the base address of the 82C54 is 40H, and to select the mode register requires A1A0 = 11, its address is 43H. Similarly, the three counters 0, 1, and 2 are at addresses 40H, 41H, 42H, respectively. Lets determine the mode words for the three counters.

Mode word for counter 0 = 001100002 = 3016Mode word for counter 1 = 010101012 = 5516Mode word for counter 2 = 101110002 = B816

611 37100 Lecture 10-77


MOV AL, 30H ; Set up counter 0 modeOUT 43H, ALMOV AL, 55H ; Set up counter 1 modeOUT 43H, ALMOV AL, 0B8H ; Set up counter 2 modeOUT 43H, ALMOV AL, 1234H ; Initialize counter 0 with 1234HOUT 40H, ALMOV AL, 12HOUT 40H, ALMOV AL, 0100H ; Initialize counter 1 with 0100HOUT 41H, ALMOV AL, 01HOUT 41H, ALMOV AL, 1FFFH ; Initialize counter 2 with 1FFFHOUT 42H, ALMOV AL, 1FHOUT 42H, AL

611 37100 Lecture 10-78


EXAMPLEWrite an instruction sequence to read the contents of counter 2

on the fly. The count is to be loaded into the AX register. Assume that the 82C54 is located at I/O address 40H.Solution:

First, we latch that contents of counter 2 and then read this value from the temporary storage register.

MOV AL, 1000XXXXB ; Latch counter 2, XXXX must be as per; the mode and counter type

OUT 43H, ALIN AL, 42H ; Read the low byteMOV BL, ALIN AL, 42H ; Read the high byteMOV AH, ALMOV AL, BL ; (AX) = counter 2 value

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Architecture of the 82C54 Read-back mode permits a programmer to capture the

current count values and status information of all three counters with a single command.

A read back command has bits D6 and D7 both set to 1.

Read-back command format

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Read-back command examples

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Status byte format

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Operating modes of 82C54 counters

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Operating modes of 82C54 counters

Effect of the GATE input for each mode

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EXAMPLEThe counter in the following figure is programmed to operate in

mode 0. Assuming that the decimal value 100 is written into the counter, compute the time delay (TD) that occurs until the positive transition takes place at the counter 0 output. The counter is configured for BCD counting. Assume the relationship between theGATE0 and the CLK0 signal as shown in the figure.Solution:

Once loaded, counter 0 needs to count down for 100 pulses at the clock input. During this period, the counter is disabled by logic 0 at the GATE0 input for two clock periods. Therefore, the time delay is calculated as

TD = ( n + 1 + d)( TCLK0)= (100 + 1 + 2)( 1/1.19318) s= 86.3 s

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EXAMPLECounter 1 of an 82C54 is programmed to operate in mode 1

and is loaded with the decimal value 10. The gate and clock inputs are as shown in the figure below. How long is the output pulse? Assume that the counter is configured for BCD counting.

Solution:The GATE1 input in the figure show that the counter is operated

as a nonretriggerable one-shot. Therefore, the pulse width isT = (counter contents)(clock period)

= (10)( 1/1.19318) s= 8.38 s

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EXAMPLECounter 1 of an 82C54, as shown, is programmed to operate in

mode 2 and is loaded with the decimal value 18. Describe the signal produced at OUT1. Assume that the counter is configured for BCD counting.

Solution:In mode 2 the output goes low for one period of the input clock

after the counter contents decrement to 0. Therefore,T2 = 1/1.19318 MHz = 838 ns

andT = 18 x T2 = 15.094 s

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EXAMPLEThe 82C54 counter, as shown, is programmed to operate in

mode 3 and is loaded with the decimal value 15. Determine the characteristics of the square wave at OUT1. Assume that the counter is configured for BCD counting.Solution:

TCLK1 = 1/1.19318 MHz = 838 nsT1 = TCLK1(N+1)/2

= 838 ns x [(15+1)/2] = 6.704 sT2 = TCLK1(N-1)/2

= 838 ns x [(15-1)/2] = 5.866 sT = T1 + T2 = 6.704 s + 5.866 s

= 12.57s

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EXAMPLEThe 82C54 counter, as shown, is programmed to operate in

mode 4. What value must be loaded into the counter to produce a strobe signal 10 s after the counter is loaded?Solution:

The strobe pulse occurs after counting down the counter to zero. The number of input clock periods required for a period of 10 s is given by

N = T/TCLK= 10 s/(1/1.19318 MHz)= 1210 = C16 = 000011002

Thus, the counter should be loaded with thenumber n=0B16 to produce a strobe pulse10 s after loading.

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10.9 82C37A Programmable Direct Memory Access Controller

The 82C37A is an LSI controller IC that is widely used to implement the direct memory (DMA)function in the 8088/8086 microcomputer.

DMA capability permits devices to perform high-speed data transfers between either two sections of memory or between memory and an I/O device.

The memory or I/O bus cycles initiated as part of a DMA transfer are not performed by the MPU; instead, they are performed by DMA controllers, such as 82C37A.

A single DMA device supports up to four peripheral devices for DMA operation.

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Microprocessor interface of the 82C37A

Block diagram and pin layout of the 82C37A DMA controller

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Microprocessor interface of the 82C37A

Microprocessor interface of 82C37A to the 8088

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DMA interface of the 82C37A

Microprocessor interface of 82C37A to the 8088

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DMA interface of the 82C37A 82C37A contains four independent channels, channel 0

through 3.When a peripheral device wants to perform DMA, it makes a

request for service at 82C37A DREQ input by switching it to login 1.

During DMA bus cycles, the DMA controller, not the MPU, drives the system bus. The 82C37A generates the address and all control signals to perform the memory or I/O data transfer.

The 82C37A performs both the memory-to-I/O and I/O-to-memory DMA bus cycles in just four clock periods. The memory-to-memory data transfer takes 8 clock periods.

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Internal architecture of the 82C37A

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Internal architecture of the 82C37A The timing and control part of the 82C37A generates the

timing and control signals needed by the external bus interface.

The priority logic circuitry resolves priority for simultaneous DMA requests from peripheral devices based on either fixed priority or rotating priority scheme.

The command control circuit decodes the register commands applied to the 82C37A through the microprocessor interface.

Each DMA channel has two address register: the base address register and the current address register.

Each DMA channel has two word-count register to specify the number of bytes of data to be transferred.

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Internal architecture of the 82C37A 82C37A has 12 different types of internal registers.

14 bitsRequest Register14 bitsMask Register46 bitsMode Register18 bitsTemporary Register18 bitsCommand Register18 bitsStatus Register116 bitsTemporary Word Count Register116 bitsTemporary Address Register416 bitsCurrent Word Count Registers416 bitsCurrent Address Registers416 bitsBase Word Count Registers416 bitsBase Address Registers

NumberSizeName

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Internal architecture of the 82C37A

Accessing the registers of the 82C37A

611 37100 Lecture 10-99


Internal architecture of the 82C37A The command register is used to control operating modes that

apply to all channels of the DMA controller.

Command register format

611 37100 Lecture 10-100


EXAMPLEIf the command register of an 82C37A is loaded with 0116, how

does the controller operate?Solution:

Bit 0 = 1 = Memory-to-memory transfers are disabledBit 1 = 0 = Channel 0 address increment/decrement normallyBit 2 = 0 = 82C37A is enabledBit 3 = 0 = 82C37A operates with normal timingBit 4 = 0 = Channels have fixed priority, channel 0 having the

highest priority and channel 3 the lowest priorityBit 5 = 0 = Write operation occurs late in the DMA bus cycleBit 6 = 0 = DREQ is an active high (logic 1) signalBit 7 = 0 = DACK is an active low (logic 0) signal

611 37100 Lecture 10-101


Internal architecture of the 82C37A The mode register is used to configure operation features of

the 82C37A.

Mode register format

611 37100 Lecture 10-102


EXAMPLESpecify the mode byte for DMA channel 2 if it is to transfer data

from an input peripheral device to a memory buffer starting at address A00016 and ending at AFFF16. Ensure that the microprocessor is not completely locked off the bus during the DMA cycle. Moreover, at the end of each DMA cycle, the channel is to be reinitialized so that the same buffer is filled when the next DMA operation is initiated.

Solution:For DMA channel 2, B1B0 = 10Transfer of data from an I/O device to memory represents a write

bus cycle. Therefore,B3B2 = 01

18

611 37100 Lecture 10-103


Selecting autoinitialization will set up the channel to automatically reset. Making bit 4 equal to 1 enables this feature:

B4 = 1The address that points to the memory buffer must increment after each data transfer. Therefore

B5 = 0To ensure that the 8088 is not locked off the bus during the complete DMA cycle, we will select the single-transfer mode:

B7B6 = 01Thus, the mode register byte is

B7B6B5B4B3B2B1B0 = 010101102 = 5616

611 37100 Lecture 10-104


Internal architecture of the 82C37A The request register is used to respond to software-initiated

requests for DMA services. Any channel used to software-initiated DMA must be

programmed for block-transfer mode of operation.

Request register format

611 37100 Lecture 10-105


Internal architecture of the 82C37A The 4-bit mask register is used to mask out (to ignore

hardware request) the DREQ input to the DMA channels.

Single-channel and four-channel mask-register command format

611 37100 Lecture 10-106


Internal architecture of the 82C37A The status register contains the information about the

operating state of the four channels of the 82C37A.

Status register

611 37100 Lecture 10-107


EXAMPLEWrite an instruction sequence to issue a master clear to the

82C37A and then enable all its DMA channels. Assume that the device is located at base I/O address DMA < F0H.

Solution:The master clear command is performed by simply writing into

the register a relative address D16. For instance, the instructionOUT DMA+0DH, AL

To enable the DMA request inputs, all 4 bits of the mask register must be cleared. The clear-mask register command is issued by performing a write to the register at relative address E16.

OUT DMA+0EH, AL

611 37100 Lecture 10-108


DMA interface for the 8088-based microcomputer using the 82C37A

19

611 37100 Lecture 10-109

10.10 Serial Communication Interface

Synchronous and asynchronous data communication

Synchronous communications interface and data-transmission format

611 37100 Lecture 10-110


Synchronous and asynchronous data communication

Asynchronous communications interface and data-transmission format

611 37100 Lecture 10-111


Simplex, half-duplex, and full-duplex communication links

Simplex communication link

MicrocomputerTransmit line

PrinterRS-232 RS-232

611 37100 Lecture 10-112



Half-duplex communication link

MicrocomputerTransmit/Receive line CRT

terminalwith

keyboard

RS-232 RS-232

611 37100 Lecture 10-113



Full-duplex communication link

Microcomputer

Transmit lineCRT

terminalwith

keyboard

RS-232 RS-232Receive line

611 37100 Lecture 10-114


Baud rate and the baud-rate generatorThe rate at which data transfers take place over

the receive and transmit lines is known as the baud rate. By baud rate we mean the number of bits of data

transferred per second.Baud rate is set by a part of the serial

communication interface called the baud-rate generator.

20

611 37100 Lecture 10-115


EXAMPLEThe data transfer across an asynchronous serial data

communications line is observed and the bit time is measured as 0.883 ms. What is the baud rate?

Solution:

Baud rate is calculated from the bit time as

Baud rate = 1 / tBT = 1 / 0.833 ms = 1200 bps

611 37100 Lecture 10-116


The RS-232C interfaceThe RS-232C interface is a standard hardware

interface for implementing asynchronous serial data communication ports on devices such as printers, CRT terminals, keyboards, and modems.Three signal lines can be used to connect the

peripheral to the MPU via RS-232C interface: a receive-data line, a transmit-data line, and signal common.The RS-232C standard defines a 25-pin interface.The RS-232C is specified to operate correctly over

a distance of up to 100 feet.

611 37100 Lecture 10-117


The RS-232C interface

RS-232 interface pins and functions

611 37100 Lecture 10-118


The RS-232C interface

A DTE-to-DTE serial communication connection

611 37100 Lecture 10-119

10.11 Programmable Communication Interface Controller

USART Universal Synchronous and Asynchronous Receiver TransmitterThe programmability of the USART provides for a

very flexible asynchronous communication interface.Typical USART can be configured through

software for communication of data using formats with character length between 5 and 8 bits, with even or odd parity, and with 1, 1.5, or 2 stop bits.A USART has the ability to automatically check

characters during data reception to detect the occurrence of parity, framing, and overrun errors.

611 37100 Lecture 10-120


8251A USART8251A USART includes 4 key sections

Bus interface section Transmit section Receive section Modem-control section

A UART can not stand alone in a communication operation; its operation must typically be controlled by a microprocessor.Data transfers over the bidirectional data bus (D0

through D7) are controlled by the signals C/D, RD, WR, CS.

21

611 37100 Lecture 10-121


8251A USART

Block diagram and pin layout of the 8251A

611 37100 Lecture 10-122


8251A USART

Read/Write operations

Data bus 3-state1XXXData bus 3-state011X

1010

RD

0000

CS

0101

WR

Data bus Control1Status Data bus1Data bus 8251A Data08251A Data Data bus0

OperationC/D

611 37100 Lecture 10-123


EXAMPLEWhat type of data transfer is taking place over the bus if the

control signals are at CS = 0, C/D = 1, RD = 0, and WR = 1?

Solution:Looking at the previous table , we see that CS = 0 means that

the 8251As data bus has been enabled for operation. Since C/D is 1 and RD is 0, status information is being read from the 8251A.

611 37100 Lecture 10-124


8251A USARTThe baud rate of the 8251A must be externally

generated and applied to the Rxc input of the receiver.Through software the 8251A can be set up to

internally divide the clock signal input by 1, 16 or 64 to obtain the desired baud rate.The receiver performs serial data to parallel data

operation while the transmitter performs parallel to serial data operation.

611 37100 Lecture 10-125


8251A USART

Receiver and transmitter driven at the same baud rate

611 37100 Lecture 10-126


8251A USARTThe 8251A can be configured for various modes of

operation through software.Control registers:

Mode-control register Command register Status register

Instruction format Baud rate factor (D0, D1) Character length (L1, L2) Parity enable (PE) Even parity check (EP) Number of stop bits (S1, S2)

22

611 37100 Lecture 10-127


EXAMPLEWhat value must be written to the mode-control register in order

to configure the 8251A such that it works as an asynchronous communication controller with the baud rate clock internally divided by 16? Character size is 8 bits; parity is odd; and one stop bit is used.Solution:

Baud rate factor: B1B0 = 10Character length: L2L1 = 11Odd parity: EP PEN = 01Stop bit: S2S1 = 01

Therefore, the complete control word isD7D6D0 = 010111102 = 5E16

611 37100 Lecture 10-128


8251A USARTCommand register formatTransmit enable, TxENData terminal, DTRReceiver enable, RxENSend break character, SBRKError reset, ERRequest to send, RTSInternal reset, IREnter hunt mode, EH

611 37100 Lecture 10-129


8251A USARTStatus register formatParity error, PEOverrun error, OEFraming error, FE

611 37100 Lecture 10-130


8251A USART

8251A initialization flowchart

611 37100 Lecture 10-131


EXAMPLEThe circuit in the figure below implements serial I/O for the 8088

microprocessor using an 8251A. Write a program that continuously reads serial characters from the RS-232 interface, complements the received characters with software, and sends them back through the RS-232 interface. Each character is received and transmitted as an 8-bit character using 2 stop bits and no parity.

611 37100 Lecture 10-132


SolutionWe must first determine the addresses for the registers in the

8251A that can be accessed from the microprocessor interface. Chip select (CS) is enabled for I/O read or write operations to addresses for which

A7A6A5A4A3A2A1A0 = 1000000Bit A0 of the address bus is used to select between the data and control (or status) registers. As shown in the figure below, theaddresses for the data and control register are XX80H and XX81H.

23

611 37100 Lecture 10-133


SolutionNext we must determine the mode word to select an 8-bit

character with 2 stop bits and no parity. As shown in the figurebelow, the mode word is EEH. Here we have used a baud-rate factor of 16, which means that the baud rate is given as

Baud rate = Baud-rate clock/16 = 19,200/16 = 1200 bpsTo enable the transmitter as well as receiver operation of the 8251A, the command word is equal to 15H.

611 37100 Lecture 10-134


SolutionFlow chart and program for the initialization of the 8251A is

shown below

611 37100 Lecture 10-135


SolutionThe receive operation starts by reading the contents of the

status register at address 81H and checking if the LSB, RxRDY is at logic 1. If it is not 1, the routine keeps reading and checking until it does become 1. Next we read the data register at 80H for the received data. The byte of data received is complemented and then saved for transmission.

The transmit operation also starts by reading the status register at address 81H and checking if bit 1, TxRDY, is logic 1. If it is not, we again keep reading and checking until it becomes 1. Next, the byte of data that was saved for transmission is written to the data register at address 81H. This causes it to be transmitted at theserial interface. The receive and transmit operations are repeated by jumping back to the point where the receive operation begins.

611 37100 Lecture 10-136


8250/16450 UART8250 and 16450 are newer devices than the

8251A UART and implement a more versatile I/O operation.New functions include a built-in programmable

baud-rate generator, double buffering on communication data registers, and enhanced status and interrupt signaling.

611 37100 Lecture 10-137


8250/16450 UART

Pin layout and RS-232 interface of the 8250/16450 UART

611 37100 Lecture 10-138


8250/16450 UART

Register-select codes of the 8250/16450 UART

Division Latch(most significant byte)

1001

Division Latch(least significant byte)

0001

Scratch111X

Modem Status011X

Line Status101X

Modem Control001X

0

0

0

0

A2

1

0

1

0

A0

1

1

0

0

A1

Line ControlX

Interrupt identification (read only)X

Interrupt Enable0

Receiver buffer (read),Transmitter HoldingRegister (write)

0

RegisterDLAB

24

611 37100 Lecture 10-139


8250/16450 UART

Register bit functions and word-length select bits of the 8250/16450 UART

1

0

1

0

Bit 0

8 bits1

7 bits1

6 bits0

5 bits0

Word LengthBit 1

611 37100 Lecture 10-140


8250/16450 UART

Baud rates and corresponding divisors of the 8250/16450 UART

-538400

-1019200

-209600

1.23277200

-404800

0.628543600

-802400

-962000

0.3121071800

-1601200

-320600

-640300

-1280150

1428

1745

2560

3840

Divisor Used to Generate 16 x

Clock

0.034134.5

0.026110

-75

-50

Percent Error Difference Between Desired and Actual

Desired Baud-rate

611 37100 Lecture 10-141


EXAMPLEWhat count must be loaded into the divisor latch registers to set

the data communication rate to 2400 baud? What register-select code must be applied to the 8250/16450 when writing the bytes ofthe divider count into the DLL and DLM register?

Solution:For 2400 baud rate, the divisor is 80. When writing into DLL,

the address must takeA2A1A0 = 0002 with DLAB = 1

and the value that is written is DLL = 80 = 50HFor DLM, the address must take

A2A1A0 = 0012 with DLAB = 1and the value is DLM = 0 = 00H

611 37100 Lecture 10-142


8250/16450 UART

RS-232 interface with EIA drivers

611 37100 Lecture 10-143

10.12 Keyboard and Display Interface

The size of the keyboard array is usually described in terms of the number of rows and columns.

The microcomputer scans the keyboard array to determine which key is pressed.

Keyboard debouncing is achieved by resamplingthe column lines a second time, about 10 ms later, to assure the the same column line is at the 0 logic level.

Two-key lockout method and N-key rollover method are usually used to resolve the problem of multiple key depression.

The way in which the display is driven by the microcomputer is said to be multiplexed.

611 37100 Lecture 10-144


Keyboard Interface

Keyboard interface to a microcomputer

25

611 37100 Lecture 10-145


Display Interface

Display interface to a microcomputer

611 37100 Lecture 10-146


Seven-segment LED

Seven-segment display

611 37100 Lecture 10-147

10.13 8279 Programmable Keyboard/Display Controller

The 8279 can drive an 8x8 keyboard switch array and a 16-digit, eight-segment display.

8279 has four signal sections: The MPU interface The key data inputs The display data outputs Scan lines used by both the keyboard and display

The operation of the 8279 must be configured through software. Eight command words are provided for this purpose.

611 37100 Lecture 10-148


Block diagram and pin layout of the 8279

611 37100 Lecture 10-149


The scan lines (SL0-SL3) are used as row-drive signals for the keyboard and digit-drive signals for the display.

The scan line can be configure for two different modes of operation through software Decoded mode Encoded mode

Decoded-mode scan line signals Encoded-mode scan line signals

611 37100 Lecture 10-150


System configuration using the 8086 and 8279

26

611 37100 Lecture 10-151


Keyboard and display signal timing

611 37100 Lecture 10-152


If logic 0 is detected at a return line during key scanning, the number of the column is coded as 3-bit binary number and combined with the 3-bit row number to make a 6-bit key code. This key code input is first debounced and then loaded into an 8x8 key code FIFO within the 8279.

Two other input signals, CNTR and SHIFT, are also stored as part of the key code when a switch closure is detected.

Key code byte format

CNTL SHIFT

MSB LSB

RETURNSCAN

611 37100 Lecture 10-153


A status register is provided within the 8279 that contains the flags indicating the status of the key code FIFO.

Status register

611 37100 Lecture 10-154


The command word 0 is used to set the mode of operation for the keyboard and display.

Display mode select code

Command word 0 format

0 0 0 D D K K

MSB LSB

K

101

0

D

16 8-bit character display Right entry18 8-bit character display Right entry116 8-bit character display Left entry0

8 8-bit character display Left entry0

Display operationD

611 37100 Lecture 10-155


The command word 0

Keyboard select codes

Strobed Input, Decoded Display Scan111Strobed Input, Encoded Display Scan011Decoded Scan Sensor Matrix101Encoded Scan Sensor Matrix001

101

0

K

110

0

K

Decoded Scan Keyboard N-Key Rollover0Encoded Scan Keyboard N-Key Rollover0Decoded Scan Keyboard 2-Key Lockout0

Encoded Scan Keyboard 2-Key Lockout0

Keyboard operationK

611 37100 Lecture 10-156


EXAMPLEWhat should be the value of command word 0 if the display is

to be set for eight 8-segment digits with right entry and the keyboard for decoded scan with N-key rollover?

Solution:The three MSBs of the command word are always 0. The next

2 bits, DD, must be set to 10 for eight 8-segment digits with right entry. Finally, the three LSBs are set to 011 for decoded keyboard scan with N-key rollover. This gives

Command word 0 = 000DDKKK= 000100112= 1316

27

611 37100 Lecture 10-157


The command word 1 is used to set the frequency of operation of the 8279. It is designed to run at 100 kHz; however, in most applications a much higher frequency signal is available to supply its CLK input. For this reason, a 5-bit programmable prescaler is provided within the 8279 to divide down the input frequency.


0 0 1 P P P P

MSB LSB

P

611 37100 Lecture 10-158


The command word 6 is used for initialization of the 8279. It is used to initialize the complete display memory, the FIFO status, and the interrupt request output line.


1 1 0 CD CD CD CA

MSB LSB

CF

CD CD CD

0 X All zeros (X = Dont Care)1 0 AB = Hex 20 (0010 0000) 1 1 All ones

Enable clear display when = 1 (or by CA = 1)

CD coding

611 37100 Lecture 10-159


EXAMPLEWhat clear operations are performed if the value of command

word 6 written to the 8279 is D216?

Solution:First, we express the command word in binary form. This gives

Command word 6 = D216= 100100102

Note that the three CD bits are 100. This combination causes display memory to be cleared. The CF bit is also set, and this causes the FIFO status and IRQ output to be reset.

611 37100 Lecture 10-160


Only one bit of command word 7 is functional. This bit is labeled E and is an enable signal for what is called the special-error mode. When this mode is enabled and the keyboard has N-key rollover selected, a multiple-key depression causes the S/E flag of the FIFO status register to be set. This flag can be read by the microprocessor through software.


1 1 1 E X X X

MSB LSB

X

611 37100 Lecture 10-161


The command word 2 is used to issue the read FIFO command for accessing the the key code FIFO.

The command word 4 is used to send new data to the display RAM.

The command word 3 is used the read the contents of the display RAM

Command word 7 format0 1 0 AI X A A

MSB LSBA X = Dont Care


1 0 0 AI A A AMSB LSB

A

Command word 3 format0 1 1 AI A A A

MSB LSBA

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