a multiple-valued single-electron sram by the padox process

8/6/2019 A mUltiple-Valued Single-Electron SRAM by the PADOX Process

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A Multiple-valued Single-ElectronSRAM by the PADOX ProcessHiroshi Inokawa, Akira Fujiwara, andYasuoTakahashihTTBasic Research Laboratories, hTT Corporation3-1Morinosato Wakamiya,Arsugi-shi,Kanagawa P&, 243-0198JapanEmail: [email protected]

Abstract (b) 3-terminal Id-VgPMultiple-valued static memory consisting of asingle-electron transistor (SET) and a MOSFET isproposed. The. memory operation is verified by usingtransistors fabricated by the CMOScompatiblepattemdependent oxidation (PADOX) rocess. Theresults indicate that a dramatic increase of CMOSmemory density can be attained by the use of a SETwith multiple-valued capability.

Fig. 1 (a) Schematicof the proposed multiple-valued memory.(b) 3-terminal I c V , characteristics of a SET. (c) 2-terminalthe SETgate shorted to theMOSFET rain.

IntroductionIn contrast to floating-gate singleelectron I-v haracteristics of the combined SET-MOSFET circuit withmemories, such as nanocrystal memories [1-5], staticmemories feature a fast simple write operation andstable retention while the power is on. Thus we believethat the static type will have a wide range ofapplications different from those of the floating-gatetype. Multiple-valued operation has been reported forfloating-gate singleelectron memories [SI,but is notexclusive, o that type of memory. We propose here amultiple-valued static memory comprised of asingle-electron transistor (SET) and a MOSFET anddemonstrate its characteristics using transistorsfabricated by the pattemdependent oxidation(PADOX) 6-81 n the same silicon-on-insulator (SO0wafer.

Principle of OperationFigure l(a) is a schematic of the proposedmultiple-valued static memory. The source of aMOSFET with fixed gate bias V is connected to thedrain of a SET. As illusmted in Fig. l(b), the SET'drain currentI,+increases and decreases periodically asa function of the gate voltage V, 9-111. However, the

Id has such large dependence on the drain voltage V,that the peak current is almost proportional to the V,,and the valley current increases more rapidly when theCoulomb-blockade condition breaks. The MOSFETc o ~ e ~ t e do the SET eliminates this large Vdependence of the SET characteristics by keeping theV , nearly constant around V=-V&. where V is thethreshold voltage of the MOSFET. This V-V is set

Fig. 2 (a) A possible layout of the integrated SET andMOSFET. b) Circuit diagram corresponding to the layoutabove. (c) Potential profile along the length of the narrow wirewhere, aSETiscreated [ 8 ] .low enough to sustain the Coulomb-blockadecondition. By connecting the SET gate to theMOSFET drain, the multipeak negative differentialresistance characteristics shown in Fig. l(c) areobtained as 2-terrninal I- V characteristics. If aconstantarrent source I,, is connected to theSET-MOSFET circuit, the periodic nature of the I-Vcharacteristics results in a number of stability points,and th is enables the multiple-valued memoryoperation.

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0-7803-6520-8/01/$10.0002001 IEEE.
mailto:[email protected]:[email protected]


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7 1 1

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10n" 1 2 3 4

"w 0Fig. 3 I,V, (3-terminal) characteristics of a SET abricated byPADOX[MI,easured at27 K nd 10mV of V,.

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0.5 1 1.5 2 2.5 3"e90

Fig. 4 IcV, characteristics of a MOSFET abricated OR thesame SO1wafer for the above SET, easured at 27 K.EXpehents

Both the SET and the MOSFET were fabricated ona thin silicon-on-insulator (SOI) layer. A possiblelayout and the corresponding circuit diagram of theintegratedSET nd MOSFET are shown in Figs. 2(a)and (b). The SET is creiited in a narrow wire region bypattemdependent oxidation (PADOX) [6-81. Thequantum size effectraises he potential in the wire, butin the middle of the wire the high compressive stressgenerated by the oxidation reduces the bandgap pi g.2(c)] [8]. This creates two tunnelbarriers and an islandsandwiched between them, which constitute a SET.Since the areas outside the wire can easily be used forMOSFETs, PADOX is highly compatible with theCMOSprocess.Figure 3shows the IKVp characteristics of a SET.Periodic draincurrent peaks are clearly seen alongwith the effect of tunnel resistance modulation by thegate voltage. From this figure and a Coulomb diamondplot, gate capacitance, sourcddrain capacitance, and

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I2 3 4 5v oFig. 5 I- V (2-tenninal)characteristicsof the proposed circuitmeasured at 1.08 V of V Stabilitypoints a-f) expected forthe current load of4.5 nA are also shown.tunnel resistance were calculated to be 0.27 aF,2.7 aF,and 80-220 kn, espectively.Figure 4 shows the subthreshold characteristics ofa MOSFET fabricated on the same SO1wafer for drainvoltages of 5 V and 10mV. The gate length, width andthe gate oxide thickness are 14 pm , 12 pm and 90 nm,respectively. The device exhibits a sharp cutoff and asmall shift due to the drain voltage, which are suitablefor the proposed application.Figure 5 shows the I-V characteristics of thecombined SET-MOSFET circuit. The currentincreases and decreases periodically, reflecting the 2,V , characteristics of the SET (Fig. 3). If a currentsource of 4.5 nA is C O M W ~ ~ ~o the circuit, stabilitypoints a-f should appear. Note that these multipeakcharacteristics originate from the characteristics of asingle SET, and the number of peaks is infinite inprinciple. This is an amactive feature of the device,and is not available in other negative-resistance devicelike resonant-tunneling diodes(RTDs) [12-14]Memory operation was confirmed by currentsweep measurements, which are shown in Fig. 6 . If thecurrent starts from stability point a and increases, thevoltage jumps when the current exceeds the secondpeak n the I- V characteristics (Fig. 5 ). If the currentsweep is reversed at th is moment, stability point b canbe reached. Other stability points, c-e, can also bereached by choosing higher current-sweep reversalpoints. Note that stability point f cannot be attained bythis current-mode operation, because the last peak inthe I-V characteristics (Fig. 5) is lower than theprevious one. Direct access to any stability point canbe made by the voltage-mode operation exemplified inFCEl memory devices [12].Discussion

Here we discuss the twomajor issues in large-scale'memory applications, i.e. ce ll area and operatingspeed.


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E321 2 4 6 8

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BL

I (nN Fig. 7 (a)A multiple-valued singleelectronSRAM cell withtwo depletion-mode MOSFETs (M1 and M2) and oneenhancement-mcde MOSFET (M3). (b) An example of theSRAM layout.

Fig. 6 current Sweep n m ~ ~ ~ m e n Bf the Pr OP O~ emory.The complianceof the curientsource is 5 v.Table 1Comparisonof cell shuchues to improvethe operating speed of the multiple-valuedSRAM.

WL

Iwl storage capacttor I wl readoutTrs.5 I 6 II

Destrudlve Nobdestrudlve

MultlplevaluedDRAM Multlplevalued FlashFigure 7(a) shows a four-transistor memory cell as

a practical design. A depletion-mode grounded-gateMOSFET M1 s used to sustain the SET drain voltagearound the absolute threshold voltage of M1.Anotherdepletion-mode MOSFET, M 2, with its gate andsource shorted serves as a current source, andpass-transistor M3 controls the access to the cell. Inwrite operation, the voltage applied to the bit line(BL)is transferred through M3, nd is quantized to astability point after M 3 is cut off.As described in theprevious section, any stability point can be directlyreached by this voltage-mode operation. Figure 7(b)shows an example of the cell layout. It has an area of31 .19 , where F is half the minimum wiring pitch.Thus this cell not only has a multiple-valued function,

but is much smaller than an ordinary 6-transistorSRAM cell.The write-in speed of the proposed SRAM shouldbe fast since the capacitance connected to the memorynode (the crossing point of the three MOSFETterminals) is comparable to that of the ordinarySRAM,and that associated with the SET is very small (-aF).The read-out speed of the original cell [Fig. 7(a)] isslow, because the current that can be supplied to thebit line (BL) ithout deseoying the memory status isless than a nanoampere, as can be understood from Fig.5. If we assume the bit line capacitance of 100fFanda voltage swing of one volt, the read-out speedbecomes of the order of 100p.To improve the read-out speed, we considered two


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additional cell structures (Table 1).If we add a storage capacitor C, to the memorynode as shown in the center column of Table 1, thecharges stored in C,can be driven out to the BL n a

short time. The small voltage difference on the BL sread by a sense amplifier. The speed should becomparable to that of multiple-valued DRAM [15].Although the read-out operation isdestructive, the datacan be refreshed immediately by the sense amplifier,and of course the proposed SRAM does not requireperiodic refreshing. Also note that the area penalty dueto the storage capacitor is negligible, since the areaabove the storage node is open in the proposed cellAnother way to improve the speed is to addMOSFETs specialized for read+ut operation (See heright column of Table 1). M4 converts voltages at thememory node to current levels, and M5 controls theaccess from the sense line (SL).By using a specialread-out scheme, such as parallel charge sensing,speed comparable to that of multiple-valued flashmemory [16,17] should be attainable. Although thiscell structure enables nondesauctive read-out, the cellarea is sacrificed considerably due to the increasednumber of transistors.

Fig. 7co)i.

ConclusionsWe have devised a novel multiple-valued SRAMcomprised of a SET and a MOSFET, and verified thebasic operation using devices fabricated bysilicon-based PADOX technology. Discussion of theSRAM cell design and its operating speed revealedthat the area should be much smaller than,and the

speed should be comparable to that of conventionalmemories. The results open up the possibility ofdramatically increasing the memory density of futurescaled-down CMOS.

Acknowledgments

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We thank Dr. Yukinori Ono for helpful discussions,and technical advice in electrical measurements.

a multiple-valued single-electron sram by the padox process

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