access ic lab graduate institute of electronics engineering, ntu multirate processing of digital...
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ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Multirate Processing ofMultirate Processing ofDigital Signals: FundamentalsDigital Signals: Fundamentals
VLSI Signal Processing台灣大學電機系吳安宇
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Outline
Introduction
Sampling Rate Conversion
Multistage Implementation
Practice Structure
Polyphase Implementation
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Motivation
DefinitionMore than one sampling rate (clock) are used in a system
Module 1 Module 2
clock 1
clock 2
?
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Conversion Approach
Analog approach
Digital approach (multirate DSP system)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Analog Approach
nITmtc nTTmhnxtxmy
AdvantagesSimple
Straightforward
Arbitrary sampling rate
DisadvantagesD/A & A/D converter are needed
Ideal (near perfect) lowpass filter is needed
Introduced noise and distortion
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Digital Approach
Sampling rate conversionInterpolation
Increase the sampling rate
DecimationDecrease the sampling rate
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Sampling TheoryIf the highest frequency component in a signal is fmax, then the signal should be sampled at the rate of at least 2fmax for the samples to describe the signal completely, i.e.,
max2 fFs
For Fs < 2fmax, alias occurs in the sampling process. Alias Distortion (aliasing)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Aliasing
fmax Fs
f
-Fs
X(f)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Interpolation by L
s
s
F
F
LT
T
1
otherwise ,0
,L
GH I
L h(m) nx mw my
sF
ss LFF sF
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Interpolation by L
2 2 L/
/L 2
nx mw my
X W Y
L h(m) nx mw my
sF sF
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Decimation by M
s
s
F
FM
T
T
otherwise ,0
,1MH I
h(m) M nx mw my
sF
MFF ss sF
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
h(m) M nx mw my
sF sF
Decimation by M
nx nw my
2 2 2 4 6 8M/
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Conversion by a Rational Factor M/L
Cascade of two process
s
s
F
F
L
M
T
T
L h1(m) nx mw my
sFss F
M
LF
'
h2(m) M
ss LFF ''
Interpolation by L Decimation by M
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Conversion by a Rational Factor M/L
A more efficiency implementation
L h (m) nx mw my
sF ss FM
LF
'
M
ss LFF ''
mw'
''sF
otherwise ,0
,min ,ML
LH I
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Multistage Implementation
I
iiLL
1
L h(m) nx mw my
sF sF
L1 h(m)L2 LI
nx my
L1
nxh1(m) L2 h2(m) L1 h1(m)
my
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Multistage Implementation
AdvantagesReduce the complexity
Reduce storage devices (registers)
Simplify (relax) filter design problem
Reduce the finite wordlength effect
DisadvantagesIncrease the control circuit
Difficulty in choosing I and best Lj for 1 i I
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Interpolated FIR (IFIR) Approach
Nothing to do with interpolation and decimation
Conceptually similar
Suitable for narrowband FIR filter designLPF
HPF
BPF
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
p s
2p 2s
p s
p
s
Desired narrowband responseAssume required filter order is N.
Stretched filterRequired filter order is reduced to N/2.
zG
2zG
Interpolated version of stretched filterRequired filter order is still N/2.
Desired Undesired
zI Image suppresserRequired filter order is M.Order (N/2+M) is needed to implement!(N/2+M) << N for small M
Application: Interpolated FIR (IFIR)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Interpolated FIR (IFIR)
(a) G(z) (a) G(z2)
(a) G(z2)I(z)(b) I(z)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Interpolated FIR (IFIR)
Quantity Compared
Filter order
Number of Multipliers
Number of Adders
ConventionalMethod
233
117
233
IFIR Method
131
66
131
G(z) I(z) Total
6
4
6
268
70
137
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Some Useful Operations
Duality and TranspositionA dual system is that performs a complementary operation to that of an original system, and it can be constructed form the original system through the process of transposition.
The transposition operation is one in which the direction of all branches in the network are reversed, and the roles of the input and output of the network are interchanged.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Duality and Transpositiontransposition
z-1
z-1
z-1z-1
z-1
z-1
nx nx ny ny
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
L
Duality and Transposition
They are not true in time-varying system, but can be treated as sampling rate reverse process.
L
M M
Mh(n) Mh(n)
Mh(n)L Mh(n) L
transposition
transposition
transposition
transposition
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Practical Structure
Decimation Mh(n)
z-1
z-1
z-1
M
z-1
z-1
z-1
M
M
M
M
z-1
z-1
z-1
M
M
M
M
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Practical Structure
Interpolation L h(n)
z-1
z-1
z-1
L L
z-1
z-1
z-1
z-1
z-1
z-1
L
L
L
L
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Application: Polyphase FIR Filter
Polyphase decomposition
n
nznhzH
lMnhne
znezE
zEzzH
l
n
nll
M
l
Ml
l1
0
h(n) nx ny
z-1
z-1
z-1
E0(zM)
E1(zM)
EM-1(zM)
nx ny
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Polyphase FIR Filter
Noble identity
E (zM) M nx ny
E (z)M nx ny
E (z) L nx ny
E (zM)L nx ny
Noble identity
Noble identity
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Polyphase FIR Filter
H (z) 3 nx ny
z-1
z-1
z-1
3
z-1
z-1
h0
h1
h2
h3
h4
h5
h0
z-3
3
z-3
z-3
h3
h1
h4
h2
h5
z-1
z-1
3z-1
z-1
E0(z3)
E1(z3)
E2(z3)
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Polyphase FIR Filter
z-1
z-1
E0(z3)
E1(z3)
E2(z3)
3
3
3
h0
z-3
z-3
z-3
h3
h1
h4
h2
h5
z-1
z-1
3
3
3
z-1
z-1
E0(z)
E1(z)
E2(z)
3
3
3
z-1
z-1
3
3
3
h0
z-1
z-1
z-1
h3
h1
h4
h2
h5
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Structure Comparison
z-1
z-1
3
3
3
h0
z-1
z-1
z-1
h3
h1
h4
h2
h5
z-1
z-1
z-1
3
z-1
z-1
3
3
3
3
3
h0
h1
h2
h3
h4
h5
Direct implementation Polyphase implementation