amit resume
TRANSCRIPT
Amit Ranjan #101, Gangothri Circle, 6
th Cross
BTM 1st Stage Mob.No: 08553545259, 07677832148
Bengaluru-560068 Email: [email protected]
Objective:
To grow in leadership and knowledge, excel in innovative technology application, interact and share with team members and colleagues, and develop world class solutions to real world challenges.
Educational Qualification:
Passed Masters of Technology degree in VLSI Design discipline from Institute of Radio Physics and Electronics, University of Calcutta with 7.48 CGPA in the year 2016.
Passed Master of Science degree in Electronics and Communication from School of Electronics, Devi Ahilya Vishwavidyalaya Indore with 7.80 CGPA in the year 2013.
Passed Bachelor of Science (Hons.) degree in Electronics from Sri Aurobindo College, University of Delhi with 66.13% in the year 2011.
Percentage in 12th
(BSEB) is 70.1% from A.N.College, Magadh University (Bihar).
Percentage in 10th
(CBSE) is 82% from Kiddy Convent High School (Bihar).
Key Skills:
Interest: VLSI, Semiconductor, Digital Electronics, Functional Verification.
EDA Tools: QuestaSim (Mentor Graphics), Xilinx ISE 10.1, Tanner Tools, P-Spice, Silvaco TCAD, Keil
µVision, Proteus.
Hardware Description Languages: Verilog, VHDL.
Hardware Verification Language: System Verilog.
Platform (OS): Red Hat Linux, Ubuntu, Windows.
Hardware Expertise: Altera FPGA Board (Processor Based System Design).
Projects:
AXI VIP Development using SystemVerilog
a. Description:
i. VIP component development for AXI3.0 protocol with support for various features
like burst type, burst size, protection, out of order, overlapping, aligned, etc. As part
of this project, developed BFM, Generator, Monitor, and Coverage models. Also
developed scenarios targeting validating above features.
b. Tools used: Questasim
c. Duration: 4 months
d. Responsibilities:
i. Developing VIP architecture
ii. Coding VIP components
iii. Validating AXI VIP using AXI slave model.
M.Tech. Final Year Project
Design & Implementation of Trigonometric and Logarithmic Functions using FPGA.
In this project, I am interfacing a 2x16 LCD to a FPGA kit (Spartan-3). My coding is for trigonometric
functions (sine and cosine) and logarithmic function (log2).
My Role: Understanding, Coding and logic implementations.
Technology /Tools Used -- Xilinx ISE 10.1, VHDL, Spartan-3 Kit.
M.Sc. Final Year Project
A small model of Home Security System
It basically provides the security at the home in case of fire or any theft or any leakage of gas like-LPG.
My Role: Understanding, Coding and logic implementations.
Technology /Tools Used -- µC AT89C52, Keil µVision, Proteus.
B.Sc. Final Year Project
Access Control System
It basically provides security at home in case of theft.
My Role: Understanding, Coding and logic implementations.
Technology /Tools Used -- 8085µP.
Trainings & Certificates:
6 months VLSI Training in Functional Verification Domain from VLSIGURU, Bengaluru.
Attended a Short Term Training Program on Embedded System Program based on ARDUINO organized by the DAVV, Indore in FEB-2012.
Completed a 6 month French Speaking Certificate Course from The Ramakrishna Mission Institute of Culture, School of Languages, Kolkata.
Achievements:
Qualified GATE 2013 in EC with the percentile of 96.47.
Qualified GATE 2014 in EC with the percentile of 92.64.
Got 2nd
position in B.Sc.(H) Electronics.
Personal Details:
Name : Amit Ranjan Date of Birth : 25-01-1991 Sex : Male Nationality : Indian Language Known : Hindi, English, Bengali, French Hobbies : Playing and watching cricket.
References:
Dr. Raj Kamal, Ex-Vice Chancellor DAVV, Indore (M.P.) & Ex- Head of the Department, School of Electronics, DAVV, Indore. Email: [email protected], [email protected] Prof. Susanta Sen, Professor, IRPEL, University of Calcutta. Email: [email protected]
Declaration:-
I hereby declare that all the information stated above is true to the best of my knowledge and belief.
Date: (Amit Ranjan)