1 مرتضي صاحب الزماني 1 routing architectures. 2 مرتضي صاحب الزماني 2...

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Routing Architectures

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معيارها

• routablility.

سرعت: تعداد سوييچها در مسير.•

فضا.•

کاهش امکان پياده منابع اتصالي کم •سازي مدار مورد نظر

اتالف مساحت و منابع اتصالي زياد •کاهش بخش هاي منطقي.

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مدل کلي

LC

Connection

Block

Switch

Block

LC

Connection

Block

Switch

Block

LC

Connection

Block

Switch

Block

LC

Connection

Block

Switch

Block

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اصطالحات

LE

LE

channel

channelch

anne

lch

anne

lSW

SW

• Wire Segment قطعه سيمي که به يک سوييچ برنامه پذير :منتهي شده است.

وصل wire segment يک يا چند سوييچ مي تواند به يک •شده باشد.

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اصطالحات

LE

LE

channel

channelch

anne

lch

anne

lSW

SW

• Track شيار(: دنباله اي از يک يا چند( wire segment در امتداد يک خط.

• Channel گروهي از :Track.هاي موازي

• Connection Box اتصال از : LCوروديها و خروجيهاي يک

هاي کانال.wire segmentبه

• Switch Box اتصال بين :wire segment هاي افقي و

عمودي.

channel

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Intermediate wiring channels

• A wire runs for L logic blocks:

LE LE LE LE

L=2

L=4

switchL=1

switch

switch

switch switch

switch

switch

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rouingمالحظات .wire segment (XC4000) چند نوع •

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rouingمالحظات

1 12 23 3 4 4

MPGA

1 12 23 3 4 4

آنتي فيوز برنامه ريزي نشده )اتصال آنتي فيوز برنامه ريزي شده )اتصال افقي قطع است(افقي وصل است(

آنتي فيوز برنامه ريزي شده )همه ي اتصالها وصلند(

افقيها به هم و عموديها به هم وصلند )مگرآنکه برنامه ريزي شود(

Fully Segmented Channel

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rouingمالحظات

1 12 23 3 4 4

MPGA

1 12 23 3 4 4

آنتي فيوز برنامه ريزي نشده )اتصال آنتي فيوز برنامه ريزي شده )اتصال افقي قطع است(افقي وصل است(

آنتي فيوز برنامه ريزي شده )همه ي اتصالها وصلند(

افقيها به هم و عموديها به هم وصلند )مگرآنکه برنامه ريزي شود(

Fully Segmented Channel

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Architecture of FPGA

• Logic elements

• Interconnects

• I/Os

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Styles of FPGA interconnect

• Local

• Intermediate

• Global:– clock– Set/reset

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I/O Blocks

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IO Blocks

• Provide access to the outside world

• Contain:– Buffers– Input registers– Output registers– MUXs– …

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Altera Cyclone IOE

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IO Blocks

• Today FPGAs support multiple standards– Standard: Electrical aspects (e.g. voltage

levels)– Each bank can be configured to

generate/accept signals of a particular standard FPGA can also be used to interface between

different standards

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I/O Block: Termination Resistors

• Fast signal edges signal bounces back when different impedance at I/O– Discontinuities in the signals– Must add external termination resistors at

pins Very hard with today small pitch size

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I/O Block: Termination Resistors

• Today FPGAs have internal configurable resistors to accommodate different board environments and I/O standards– DCI: Digitally-Controlled Impedance

• Simple rule of thumb:– For any signals with rise/fall times of < 500 ps,

use termination resistors

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Gigabit Transceiver

– Traditional communication of large amount of data b/w devices: Bus

– Large bus width (e.g. 64):• Needs lots of pins

• Needs lots of tracks to connect devices

• Very hard to route these tracks in complex boards

– Needs same length and impedance

• Hard to manage signal integrity

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Gigabit Transceiver

• Gigabit Transceiver:– In high-end FPGAs, gigabit transceiver

blocks use one pair of differential signals for very fast communication

– Each block may have a number of (e.g. 4) such transceivers.

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FPGA as Interface Between Devices

• Gigabit Xceiver blocks can be configured to support several standards:– PCI Express

– InfiniBand

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Gigabit Transceiver

• Serial interface

• Point-to-point Each Xceiver can only talk to a single

Xceiver on another device– Unlike buses with some devices hanging off

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Gigabit Transceiver• Differential Pair:

– A pair of tracks carrying complementary logic levels

– Advantage: Less susceptible to noise (both affected equally)

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Inside Xceiver Block (TX)

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Inside Xceiver Block (RX)

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8b/10b Encoder

• In high data rate, circuit board and its track absorbs a lot of high frequency content of signal– Attenuated– Phase-shifted

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8b/10b Encoder

• Not serious problem in this case

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Consecutive Bits

• Inter-symbol Interference (ISI):• Pessimistic view:

– Receiver sees all ‘1’s!

• In reality: Must avoid sending 5 consecutive identical bits (‘1’s or ‘0’s)

• 8b/10b block: 8b data is augmented to 10b to guarantee that.

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FIFO Buffer

• Store data temporarily when too many words are arrived too closely together

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Polarity Flipper

• Flips ‘0’ to ‘1’ and vice versa if the receiving device expects data in flipped form

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Configurable Options

• Pre-emphasis (@ TX):– High-speed data rates cause signal

attenuation– Pre-emphasis: first ‘0’ in a string of ‘0’s

(first ‘1’ in a string of ‘1’s) are boosted with a slightly higher voltage

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Pre-Emphasis• The amount of pre-emphasis can be

configured for different circuit board environment:– E.g. 10%, 20%, 25%, and 33%

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Pre-Emphasis

• The amount of pre-emphasis depends on– Position of FPGA in relation to other

components– High-speed standard being employed– Board characteristics

• Can be determined by simulation

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Equalization

• More loss for high-frequency signals than low-frequency signals

• Equalization (@RX):– Boosting higher frequency signals more than

lower ones– Can configure the amount of equalization– Can do pre-emphasis or equalization or both

for a signal

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Equalization

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Pre-Emphasis & Equalization

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References

• Maxfield, Design Warrior’s Guide to FPGA, 2004.

• RocketIO™ Transceiver User Guide, Xilinx, Gigabit Transceiver-ug024.pdf

• Equalization for High-Speed Serial Interfaces in Xilinx 7 Series FPGA Transceivers, Xilinx, 2012.