distributed dll

Graduate Institute of Electronics Engineering, NTU NTU Confidential

GIEE High-Speed Circuits Lab

Distributed DLL

學生：馮楷倫指導教授：李泰成

GIEE High-Speed Circuits Lab

Outline Motivation System Architecture Circuit Details Behavior Simulation Results Conclusion

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Introduction Multiple-Phase Clock Generators

Time-Interleaved System I/O Interface Circuits DLL-Based Frequency Multiplier

Issues Phase Accuracy Jitter Performance

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Multiphase Clock Generation(i) Time-interleaved System

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Multiphase Clock Generation(ii) Effect of timing error

Static timing error Dynamic timing error

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Conventional DLL

Only one output phase is monitored.

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DLL with Phase Calibration Circuit

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Jitter Accumulation Jitter accumulates along the delay line. More delay cells = Larger jitter.

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Distributed DLL(DDLL) All output phases are monitored. Reduce phase mismatch and jitter.

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Locking Process of the DDLL

Conceptual demonstration of the DDLL.

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System Architecture

Each delay cell is independently tuned.

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PD Mismatch (i)

PD mismatch will deteriorate the phase accuracy.

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PD mismatch (ii)

1 2

1 2 3 4

2 3 4 5

4 5

1 2 3 4 5 0

err err

err err err err

err err err err

err err

err err err err err

t t

t t t t

t t t t

t t

t t t t t

PD1

PD2

PD3

PD4

t

t

t

t

1 1

2 1 2

3 1 2 3

4 1 2 3 4

5 1 2 3 4 5

err err

err err err

err err err err

err err err err err

err err err err err err

phase t

phase t t

phase t t t

phase t t t t

phase t t t t t

PDiterrit

: the phase deviation caused by the ith PD: the phase deviation of the output of the ith delay cell

1 1 2 3 4

2 1 2 3 4

3 1 2 3 4

4 1 2 3 4

5

8 4 1 2

15 15 15 151 8 2 4

15 15 15 154 2 8 1

15 15 15 152 1 4 8

15 15 15 150

err PD PD PD PD

err PD PD PD PD

err PD PD PD PD

err PD PD PD PD

err

phase t t t t

phase t t t t

phase t t t t

phase t t t t

phase

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PD Rotation

PD1 PD2 PD3 PD4

PD2 PD3 PD4 PD1

PD3 PD4 PD1 PD2

PD4 PD1 PD2 PD3

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PD Mismatch (iii)

1 1 2 3 4

2 1 2 3 4

3 1 2 3 4

4 1 2 3 4

5

8 4 1 2

15 15 15 151 8 2 4

15 15 15 154 2 8 1

15 15 15 152 1 4 8

15 15 15 150

err PD PD PD PD

err PD PD PD PD

err PD PD PD PD

err PD PD PD PD

err

phase t t t t

phase t t t t

phase t t t t

phase t t t t

phase

The original With PD rotation

1 2 3 4

1 1 2 3 4

2 1 2 3 4

3 1 2 3 4

4 1 2 3

1 1 1 1

4 4 4 4

1 1 1 1

4 4 4 41 1 1 1

4 4 4 41 1 1 1

4 4 4 41 1 1 1

4 4 4 4

PDi PD PD PD PD

err PD PD PD PD

err PD PD PD PD

err PD PD PD PD

err PD PD PD PD

t t t t t

phase t t t t

phase t t t t

phase t t t t

phase t t t t

4

5 0errphase

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4 phases DDLL Architecture

Without PD rotation With PD rotation

Delay Line

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Clock Diagram

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PD

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V/I converterVI 1 (use VI sample1) & VI 3 (use VI sample2)

VI 2 ( use both VI sample1 & VI sample2)

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V/I converter 1

Vdn represents the time difference between ck0 and ck1Vup represents the time difference between ck1 and ck2

V/I 1 compares ⊿T01 and ⊿T12

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V/I converter 2

Vdn1 represents the time difference between ck0 and ck1Vdn2 represents the time difference between ck1 and ck2Vup1 represents the time difference between ck2 and ck3Vup2 represents the time difference between ck3 and ck0

V/I 2 compares ⊿T02 and ⊿T20

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V/I converter 3

Vdn represents the time difference between ck2 and ck3Vup represents the time difference between ck3 and ck0

V/I 3 compares ⊿T23 and ⊿T30

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Delay Cell

Current-starved Delay cell

Dcell

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Behavior Model Simulation ck0, ck1, ck2, ck3 come from the output clock of the behavior

model Give PD2 a 1ps time deviation intentional

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Behavior Model Simulation (i)

Without PD rotation (SNR = 67.3dB)

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Behavior Model Simulation (ii)

With PD rotation (SNR = 80.2dB)

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Conclusion By rotating the PDs, we can average out the timing erro

r caused by the PD mismatch. 1GHz reference clock, four clock phases output.

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Future Word Willing to tape out in this November. Will use UMC65nm fabrication.