distributed amplifier

Survey of Distributed Amplifier

ADVISER:DR.M.KAMAREISTUDENT: M.BAHRAMI

بررسی تقویت کننده توزیع شده

Contents:

INTRODUCTION

REVIEW

NEW PAPERS

REFERENCES

2

INTRODUCTIONShanon law

C=BWLog(1+SNR)

Distributed Amplifier

a method for wideband implemention

The key idea

divide and conquer

3

REVIEWBasic circuit :

The key idea :absorb parasitic capacitance

to artificial Transmission-lines overcome to substantiality tradeoff

Distributed amplifiers are attractive candidates

for UWB systemswide input-matching

wide gain bandwidth

excellent linearity

4

Figure 1 :basic DAFigure 2 :OFDM Receiver

REVIEW 5

Ali Medi MMIC COURSE NOTE ,2015

REVIEW 6

Ali Medi MMIC COURSE NOTE ,2015Figure 3 : Gain versus frequency for the DA

High-gain DA architectures 7

Cascaded

Matrix DAFigure 4 : Cascaded DA

Figure 5 : Matrix DA

Xin 09-06 (Low power-Wide band-High gain)

implemented in a standard 0.18 m CMOS technology.(In HG and LP)

Most of designs are based on the gaincell topology and do not

provide enough gain and bandwidth at very low power

consumption.

A major drawback of distributed amplifiers for UWB applications is

their large dc power consumption

Increasing Gain (n or gm)

8

Xin 09-06 Gain cell configurations used in CMOS distributed amplifiers

a) used at very long time, decent

gain, very large bandwidth

c) higher gm,mobility difference

9

Figure 6 : Gain cell configurations used in CMOS DAFigure 7 : Calculated gm of the proposed gain cell

and a CS gain cell stage.

Figure 8: Small-signal equivalent circuit

b) used to enhance reverse

isolation, does not provide significantly

high gm

d) proposed cascade

Xin 09-06

Peaking Inductance effect

10

=

Figure 9: frequency response of the gm of the proposed

gain cell for different values of inductance.

Xin 09-06Simulation Result :

11

Figure 11: S21 and S11 at low power state

Figure 12: S21 and S11

at high gain state

Figure 13: NF

Table 1:Performance summary

Figure 10: Microphotograph of the

low power distributed LNA (1.60×9𝑚𝑚2 )

Chien 07 (High-Gain)

implemented in a standard 0.18 m CMOS technology.

Conventional DA:

1)The gain in the DA is limited by the attenuation

2)The DAs exhibit an additive gain mechanism

In order to effectively improve the gain increment with the

number of cells, cascaded DAs have been proposed.

12

Chien 07

Cascaded DA :

13

Figure 14: Cascaded DA

Figure 15: Matrix DA

Matrix DA :low frequency Gain

haigh frequency Gain

loading effect at the interstage

artificial transmission line

Chien 07

Proposed DA : full advantage of themultiplicative gain mechanism

Advantages:gain grows exponentiallyonly one terminationcharacteristic impedance

14

Figure 16: Proposed DA

Chien 07Bandwidth Considerations:

the parasitic capacitance at the cascode node creates a

nondominant pole within the required bandwidth .

inductive shunt and series-peaking technique:

L1,L2,L3 are inserted to split the capacitances at the internal

15

Figure 17: Proposed DAFigure 18: Gain of DA

Chien 07

Stagger tuning technique:

down-scaling the interstage L3 from the input linetoward the output

16

Figure 19: the stagger-tuning technique.

Chien 07 Simulation Result :

17


Chien 07 18


Figure 21: Sparam of proposed DA

Moez 08 (Low-Noise)


Used a technique for the design of ultra-wide-band low-noise amplifiers.

NOISE SOURCES IN CMOS Das

a)Transistors

b)Termination Resistor

c)Input Source Resistor

d)On-Chip T-L

19

Figure 22: Noise source in DA

Moez 08NOISE FIGURE CALCULATION :

A significant contributor to the DA’s noise

20

Figure 23: Noise contribution of

gate line terminating resistor

Passive termination

(dominant) Transistors

Resistive load

Moez 08

Proposed low noise DA

the terminating resistorreplaced with a resistive-inductivenetwork.

in low frequency Rg2

in high frequency Rg2+Rg1

intentional mismatch

21

Figure 24: CDA and Proposed DA

Moez 08

Simulation Result :

22

Figure 25: S11 and NF in CDA and LNDA

Figure 26: Noise Figure


Lin 2011 (Gain Cell)

implemented in a standard 0.13 m CMOS technology.(LG,HG,LP)

using cascaded gain cell

Proposed two stage DA

23

Figure 27: Proposed gain cell


Lin 2011

Formed by an inductively parallel-peaking

cascode-stage low Q and an inductively

series-peaking common-source stage

RL network termination

24

Figure 29: Effect inductive peaking

Figure 30: Effect termination on S11

Lin 2011

Simulation Result :

25

Figure 32:Proposed DA

Lin 2011 26

Figure 31:simulation results

Lin 2011Simulation Result :

27


Mesgari 2014(Low-Noise)


DA with a feed forward path is presented

1) reduce noise (-.6dB) effects

2)improves the amplifier gain (+2dB)

3) without increasing its power consumption

Resolve the low gain in past papers

cascaded multi-stage DA

matrix DA

cascaded single-stage DA

negative capacitance

28

Mesgari 2014 Resolve the noise issue in past papers

RL network termination

Trans-Conductance coefficients of different stage

Active termination

CDA and ATDA

29

Figure 33: a)CDA , b)ATDA

a)b)

Mesgari 2014ATDA:

matching condition

1) Reverse isolation.

2) Noise and signal polarity

3) Increases the amplifier gain

30

Figure 34: ATDA

Mesgari 2014

Simulation Result :

31

Figure 35: Noise figure Figure 36: SParam

Mesgari 2014

Simulation Result :

Pass band gain 16dB (+2dB)

S11 and S22 are less then -10dB

The average NF for 100MHZ to 12

GHZ is 1.8 dB(-.6 dB)

32

Figure 37: Sparam

Chen 2014

DC-8O GHz Distributed Amplifier

DA plays a critical building block in many system

applications

high data-rate communications

broadband radio transceivers

high-resolution imaging systems

40-nm CMOS digital process

based on the CDA with CSSDA gain cell

33

Chen 2014 High gain and output power

The number of cascade stage of CSSDA and CDA are 4 and

2

34

Figure 38: a)DA , b)4-stages CSSDA

b)

a)

Chen 2014

1) In order to minimize the chip size, the artificial transmission-

line sections of DA are implemented with microstrip-line

instead of coplanar-waveguide (CPW)

2) Not offer the metal-insulator-metal (MIM) capacitor, the

inter-digital architecture is used in the de-coupling capacitor.

In order to obtaining more bandwidth,the ground plane

under the de-coupling capacitor is used to reduce the

parasitic effect.

35

Chen 2014 Simulation Result :

36


Figure 39: SParam

REFERENCES:

[1] D. M. Pozar, Microwave Engineering, 3rd ed. New York: Wiley, 2005, pp.

422–496, 632–641.

[2] Ali Hajimiri, “Distributed Integrated Circuits: An Alternative Approach to

High-Frequency Design,” IEEE communication Magazine, vol. 40,no. 2, pp. 168-173, Feb 2002

[3] Behzad Razavi, Design of Integrated Circuits for Optical communication

Systems , 2nd ed. McGraw-Hill, 2012.

[4] K. Moez and M. I. Elmasry, “A low-noise CMOS distributed amplifier for

ultra-wide-band applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55,

no. 2, pp. 126–130, Feb. 2008.

[5] X. Guan and C. Nguyen, “Low-power-consumption and high-gain

CMOS distributed amplifiers using cascade of inductively coupled

common-source gain cells for UWB systems,” IEEE Trans. Microw. Theory

Tech., vol. 54, no. 8, pp. 3278–3283, Aug. 2006.

37

REFERENCES:

[6] Mesgari, B.; Saeedi, S.; Jannesari, A., "A wideband low noise distributed amplifier with active termination," Telecommunications (IST), 2014 7th International Symposium on , vol., no., pp.170,174, 9-11 Sept. 2014.

[7]Y. –S. Lin , J. –F. Chang and S. –S. Lu “Analysis and Design of CMOS Distributed Amplifier Using Inductively Peaking Cascaded Gain Cell for UWB Systems” , IEEE Trans. Microw. Theory Techn., vol. 59, no. 10, pp.2513 -2524 2011

[8] J.-C. Chien and L.-H. Lu, “40-Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18-nmCMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2715–2725, Dec. 2007.

[9] Po-Han Chen; Kuang-Sheng Yeh; Jui-Chih Kao; Huei Wang, "A high performance DC-80 GHz distributed amplifier in 40-nm CMOS digital process," Microwave Symposium (IMS), 2014 IEEE MTT-S International , vol., no., pp.1,3, 1-6 June 2014.

[10] Ali Medi MMIC COURSE NOTE ,2015

38

Thank You

39