asml 20070914 2007 09 14 db london sept 14
DESCRIPTION
ASML Deutsche European Technology ConferenceTRANSCRIPT
/ Slide 1<file name><version 00><author>
Deutsche Bank 2007 Technology ConferenceLondon
Franki D’HooreDirector Investor Relations14 September, 2007
/ Slide 2
Safe Harbor
“Safe Harbor” Statement under the U.S. Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements that are
subject to risks and uncertainties including, but not limited to: economic conditions, product demand and semiconductor
equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors (the
principal product of our customer base), competitive products and pricing, manufacturing efficiencies, new product
development, ability to enforce patents, the outcome of intellectual property litigation, availability of raw materials and
critical manufacturing equipment, trade environment, and other risks indicated in the risk factors included in ASML’s Annual
Report on Form 20-F and other filings with the U.S. Securities and Exchange Commission.
/ Slide 3
ASML overview - The world’s leading provider of lithography systems for the semiconductor industry
Established: 1984Headquarters: Veldhoven, the NetherlandsMarket cap ~ €10 BEmployees ~ 6,200Customers: Serving 17 of the top 20 semi mfg.Equity Listing: Nasdaq and Euronext
Key facts
Key financials
€ million 2005 2006 H1 2007
Market share (based on revenue) 57% 63% 66%
Net sales 2,529 3,597 1895
Gross profit 974 1,462 777
EBIT 449 871 405
Leaders in InnovationASML TWINSCAN
Ranked in the top 3 for customer satisfaction for the
5th consecutive year
/ Slide 4
Sources: ASML MCC, VLSI Research, iSuppli, SIA
Industry growth drives Lithography tool consumption - NAND Flash fastest growing
DRAM
LOGIC
NAND
NOR
ANALOGMICRO
Other
00
10
20
30
40
50
60
0 5 10 15 20 25 30CAGR Exposure Area 06-09 [%]
Expo
sure
are
a 20
06 [S
I*10^
9]
Segment size: 20 Bio. US$
/ Slide 5
NAND Flash
Customer Roadmaps drive Lithograph tool development
Jan-00 Jan-02 Jan-04 Jan-06 Jan-08 Jan-10 Jan-12
Hal
f Pitc
h (n
m)
200
100
80
60
40
Logic
DRAM
Half Pitch status : Half Pitch status : Logic = 65~90nm Logic = 65~90nm DRAM = 60~80nm DRAM = 60~80nm NAND = 55~65nmNAND = 55~65nm
/ Slide 6
ASML Lithography Roadmap 300mm λ Res. NA
32nm 0.25 40nm 0.25
<40nm >1.5
45nm 1.20 57nm65nm 70nm 0.85 80nm 0.93 90nm110nm130nm 0.70 XT:760F
XT:1000H
XT:870FXT:875F
XT:450GXT:450F
2011
1.35
XT:1700Fi
XT:1400FXT:1450G
XT:1250D
EUV 13 nm
i-Line 365 nm 350nm
ADT
XT:875GXT:870G
0.65
>1.5 NA?
220nm
2006 2007XT:400F
0.93
0.80
201020092008XT:400G
KrF 248 nm
ArFi 193 nm
ArF 193 nm
Hi Index
40nm NextXT:1900Gi
PPT
Decision point
/ Slide 7
ASML TWINSCAN™ Product Specifications
λ System Res. 300mm Throughput [WPH) & Overlay Roadmap
Next <40nmXT:1900 40nm G 131 , 6nm
XT:1700i 45nm F 122 , 7nm
XT:1450 57nm G 145 , 6nm
XT:1400 65nm F 133 , 6nm
XT:1250 70nm D 120 , 8nm
XT:1000 80nm H 165 , 6nm
XT:875 90nm F 135 , 8nm G 150 , 6nm
XT:870 110nm F 135 , 8nm G 150 , 6nm
XT:760 130nm F 130 , 12nm
Year
XT:450XT:400
>131 <6nm
KrF 248nm
ArFi 193nm
ArF 193nm
FF 135 ,25nm
2010200920082006 2007
220nmi-Line 365nm 350nm
131 ,12nm G 141 ,12nm149 ,25nmG
2011
ContinuousContinuousImprovementImprovement
/ Slide 8
ASML roadmap enables shrink for Logic, DRAM, and NAND flash at time required
Source: Various customers, dates determine production start/qualification
10 12
200
100
80
60
40
1107 090804 060501 030200Res
olut
ion/
half
pitc
h “S
hrin
k”[n
m]
Year
ASML Product Introduction
XT:1400
XT:1700i
AT:1200
AT:850
XT:1900i
k1=0.4
k1=0.27
LogicDRAM
R&DR&D
R&DR&D
NAND
To enable continued shrink for
memory: EUV is needed, Double
Patterning to bridge gap until
EUV mature
Litho technology will allow Logic
to shrink
XT:1450Double Patterning
/ Slide 9
0%
20%
40%
60%
80%
84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06
Technology in Time helps grow market share
Total market: €4,800 millionTotal market: €463 million
ASML market share (revenue) – Nearly tripled in 10 years
1984 2006Perkin Elmer
Canon
GCA
Ultratech
EatonNikon
ASET
Hitachi
ASML63%
Canon16%
Nikon21%
Source: SEMI, Gartner Dataquest
8” & i-line6” & early i-line
KrF & Step & Scan
12” & ArF Immersion
/ Slide 10
Immersion - Leadership continues
Over 50 systems shipped to date to all applications and geographies in the world25 immersion machines in backlog valued at € 728 M Received repeat orders from major Japanese customers including multiple XT:1900i machinesASML plans to ship about 35 immersion machines in 2007
Backlog in value
i-line 6%KrF 15%
ArF dry 37 %ArF Immersion
is 42% of backlog
/ Slide 11
First TWINSCAN XT:1900i shipped on schedule early July
First tool in the world capable of printing features below 40 nmin volume production
/ Slide 12
Over 2 Million wafers processed on ASML immersion systems with steep production ramp since April 2007
0
500
1000
1500
2000
2500Ja
n-05
Feb-
05
Mar
-05
Apr
-05
May
-05
Jun-
05
Jul-0
5
Aug
-05
Sep-
05
Oct
-05
Nov
-05
Dec
-05
Jan-
06
Feb-
06
Mar
-06
Apr
-06
May
-06
Jun-
06
Jul-0
6
Aug
-06
Sep-
06
Oct
-06
Nov
-06
Dec
-06
Jan-
07
Feb-
07
Mar
-07
Apr
-07
May
-07
Jun-
07
cumulative
Expo
sed
waf
ers
(x10
00)
Wafers exposed on ASML immersion equipment
/ Slide 13
180nm
130nm
90nm
65nm
The layout designers draw, is not quite what gets printed by scanners
/ Slide 14
Why is this happening? Because the litho process is not an error-free transfer function
Mask-writing Wafer exposure Resist development Etch
H ≠ 1
/ Slide 15
What can we do about it? Software compensation for the distortion
H
…… …
~1/H
/ Slide 16
Mask(with correction,or “RET/OPC”)
Silicon Image w/o correction
Design Layout
Mask(no correction)
Silicon Image with RET/OPC
In practice…
/ Slide 17
What does Brion do?
Mask-writing Wafer exposure Resist development Etch
H ≠ 1
Accurate mathematical model of “H”
Designers drawingSimulated wafer,
before you print anything
/ Slide 18
With an accurate mathematical model of H, we can do two things:
Compensateon design
Compensateon scanner
i.e. Approximate 1/H
i.e. Find H’ so distortion is lessand/or easier to compensate for
Brion’s Tachyon OPC+ product line
Scanner tuning
/ Slide 19
Through accurate model, we can fine tune many system settings for optimum exposure of each device pattern, reticle & wafer
LensLens
IlluminatorIlluminator
SigmaPupicomPSEsDOEsDoseUnicomEtc.
StagesStages
LaserLaser
Bandwidth
NAManipulators
FocusTilt XTilt YReticle heightSynchronization
/ Slide 20
Synergies of owning the scanner and the litho model for scanner-tuning
System setting ranges : NA range Illumination option/ranges standard & custom DoseMapper correction rangeetc.
Actual system dataLens heating characteristics Aberration dataStray light Laser bandwidthetc.
Wafer metrology & exposure data:Focus & Leveling & focus hot spot dataDose error, Laser dataetc.
Optimum system settings :NA Illumination setting (standard, custom)Focus, Dose settingsetc.
Real time system optimisation :Lens manipulator settings Exposure dose & DoseMapper offsets Focus & tilt by shot / waferLaser bandwidthAlignment & wafer grid offsets / field/waferOther
/ Slide 21
The holy-grail of optimisation: today, only ASML can do this
Optimized
Scanner (e.g. Illumination)
Non - Optimized
Mask
Top-downphotoresist
Optimize both the scanner and
the mask, together, as a
unified optimization
problem
/ Slide 22
With Brion, ASML now can… (1/2)
Leverage a whole new dimension of possibilities for optimizing imaging performance (mask optimization, RET/OPC) as an integral part of its solution package
Use an accurate model of the lithography process to tune the dozens of scanner knobs available so to further optimize imaging performance (scanner tuning)
Through the two points above, enable faster shrink and higher yield for our customers
/ Slide 23
With Brion, ASML now can… (2/2)
Further secure the ArF roadmap until EUV is ready
Prevent value-migration to EDA by capturing software solutions to printability
Penetrate a new and growing market at the interface with EDA, capturing new value streams and enabling growth beyond “hardware”
/ Slide 24
1
10
100
1985 1990 1995 2000 2005 2010
Year
Lithography System costs will continue to riseR
elat
ive
List
Pric
e
ii--line line
300mm300mm200mm200mm150mm150mm
KrF KrF ArF ArF ArFi ArFi EUV? EUV?
Wafer SizeWafer SizeWafer Size
WavelengthWavelengthWavelengthStepper Stepper
Platform Platform Platform
Step & Scan Step & Scan
Dual Stage Dual Stage
0.4 0.4 0.5 0.5 0.6 0.6
0.7 0.7 0.8 0.8
0.93 0.93 1.2 1.2
1.35 1.35
ApertureApertureAperture
/ Slide 25
Average Selling Price (ASP) grows
0
2
4
6
8
10
12
14
16
mill
ion
Euro
1997 1998 1999 2000 2001 2002 2003 2004 2005 2006
ASML ASP new systems
KrF &Step & Scan
300mm & ArF
ArF volume& ArFi
/ Slide 26
Are lithography systems becoming unaffordable?
1
10
100
1,000
10,000
1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008
150mm 200mm 300mm
Relative price increase = 40% / generation
Relative price increase Relative price increase = 40% / generation = 40% / generation
Relative productivity increase (mm2/hour) = 30% / generation
Relative productivity Relative productivity increase (mmincrease (mm22/hour) /hour) = 30% / generation = 30% / generation
Relative shrink increase (pixels/field) = 100% / generation
Relative shrink Relative shrink increase (pixels/field) increase (pixels/field) = 100% / generation = 100% / generation
Relative cost reduction (pixels/hour/MEuro) = 60% / generation
Relative cost reduction Relative cost reduction (pixels/hour/(pixels/hour/MEuroMEuro) ) = 60% / generation = 60% / generation
/ Slide 27
Lithography Affordability for Future Shrink R
elat
ive
Perf
orm
ance
00.20.40.60.8
11.21.41.61.82.0
AT:1150C XT:1400E XT:1900i NEXTi EUVL90nm 65nm 40nm 28* 22
2003 2005 2007 2009 20114GB 8GB 16GB 32GB 64GB
Relative System CostRelative System WPHRelative Cost / Function / Hour
ModelResolution
YearNAND Flash
2.6
2.22.4
* Double Patterning
/ Slide 28
ASML Competitive Advantage
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2004 2005 2006 2007 2008
ASML ArFCompetition ArFASML ArFiCompetition ArFi
Pixe
ls p
er H
our p
er M
illio
n Eu
ro
/ Slide 29
Summary
Shrinking design rules have been the economical driver of the ICindustry. Lithography remains the key enabler
Providing the right product at the right time allows market share gains for ASML
Shrinking design rules require increasingly more sophisticated lithography systems resulting in a steady growth in their cost and resulting ASP’s
ASML insures that the increasing cost of advanced lithography systems remain acceptable by developing solutions that result inmaximum usable shrink while driving increased productivity to ensure steady improvement in cost per function
Future lithography technologies will likely ensure that the economics of shrink will remain attractive for at least several more generations
/ Slide 30
Commitment