Communication Interface Circuit

Design

Chapter 1 :

CMOS Digital Model and Passive

Elements

2

The digital model is deemed as the very

simplified model for CMOS IC design. It is

important to have a background knowledge in

this regard. By contrast, the passive

elements, including R, C, and L, are basic

building blocks for interfacing circuits.

3Outline

Digital MOSFET model

Series connection of MOSFETs

Capacitor

Resistor

Inductor

4Digital MOSFET Model

When a step function signal is applied at the gate of a NMOS, the scenario is as follows.

1. An instantaneous current flows thru the

MOS.

2. The operating point and the current then

are moving toward the origin.

3. The estimated resistance between D and

S is the reciprocal slope of the line

between the origin and the point with VGS= VDD.

5View of Miller Capacitance (1)

Qinit = C (0 VDD) = - C x VDD

Qfinal = C (VDD 0) = C x VDD

Total Q to be shifted = 2C x VDD

6View of Miller Capacitance (2)

Total Q to be shifted = 2C x VDD

When you view the circuit from one single direction, it is simplified as follows.

7Drain Current in Saturation Region

The drain current is expressed as follows.

22

THNn

D VVDDL

WKPI

22

THND VVDDI

8Equivalent Channel Resistance

It is only an approximation!

WL

R

VVDDL

WKP

VDD

I

VDDR n

THN

nD

n

'

2

2

A Simplified Switching Model

9

10

An Equivalent Circuit of Switching Model

The simplified model is deemed as a switch and a Rn with the switching point at 1/2 VDD.

11

12

Parasitic Capacitance

Capacitive Effects : Assume in the triode region and the linear transition, the following

equation will likely be held.

CoxCgsCgd 2

1

t

VDDCox

t

VDDVDDCox

t

VgdCgdI

)(

2

A Simplified Model with Parasitic Caps

13

An Equivalent Circuit with Parasitic Caps

14

Definition of Delays

tLH : 10% VDD to 90% VDD at the output

tHL : 90% VDD to 10% VDD at the output

tPLH : 50% VDD at the input to 50% VDD of the corresponding output (rise edge)

tPHL : 50% VDD at the input to 50% VDD of the corresponding output (fall edge)

15

Illustrative Diagram of Delays

16

17

Simple RC Delay Estimation

tdelay = 0.7 RC

trise = 2.2 RC

tPHL = 0.7 Rn Ctot, tPLH = 0.7 Rp Ctot tHL = 2.2 Rn Ctot, tLH = 2.2 Rp Ctot

Design Example

18

Simulation Results of the Example

19

20

MOS-based Pass Gate

Pass gate (PG) is a very common digital design scheme for controlling, gating, or constructing basic

logic gates

It saves area and gate count by paying the price of

poor output swing and noise prone.

21

Price to Pay degraded output swing

Poor output swing by one Vth.

22

Delay of Cascaded Pass Gates

One single PG

Ctot = CL + Cox/2

td = 0.7 Rn Ctot

23

Design Examples

24

An Alternative : Transmission Gate

Tradeoff : area (gate count) delay and swing

25

Series-connected PGs

It is a not a good idea to have this kind of circuit in your chip unless there is no way out.

tdelay ~ 0.35 Rn Cox l2

26

Output Dynamic Range

Since the series connection of MOS is widely used in digital circuit design, it is helpful to

understand its DC behavior. Assume there

are 3 NMOSs connected serially. The gate

voltage and input are VDD. Then the

dynamic range of the output Z will be 0 to

VDD - VTHN. By contrast, if the PMOSs are

used the dynamic range is VTHP to VDD.

27

Equivalent Circuit Model

Total delay is the sum of the following terms :

RC transmission line delay = 0.35 Rn Cox l2

Load charging delay = 0.7 l Rn CL

28

Measurement Problem Using A Probe

Any probe (passive or active) possesses a significant R and C relative to the chip as well

as the pads.

The probe cable is not an idea cable, either.

The OSC itself also has big R and big C.

Therefore, the loading effect when you design your chip is better taken into account : 10

MEG // 10 pF.

29

Scenario of Using a Probe and an OSC

30

Passive Elements : R and C

For the 2P4M Process :

M1 : Used for local routing and basic cell routing

M2 : Used for local channel routing and power line routing

M3 and M4 : global routing and power lines

GPOLY : gate poly is used for the construction of MOSs

CPOLY : cap poly is used for construction of R (alone) and C (with GPOLY)

31

Resistors on Silicon

Resistance will be drifting by temperature variation and applied voltage

The dependence of resistance vs. temperature and voltage variation is, in fact,

quadratic, not linear.

])(2)(11[)()(

])(2)(11[)()(

2

000

2

000

VVVCRVVVCRVRVR

TTTCRTTTCRTRTR

32

Resistivities of poly tend to be in the vicinity of roughly 5-10 ohms per square.

Temperature coefficient defined as

T

R

RTC

1

Typically, TC depends on doping and composition

(about 1000 ppm/C).

Resistors

TC

What does the TC indicate ?

33

34

MOS-based Resistors

MOS transistor is used as a resistor, the incremental resistance of a long channel MOS in triode region is

It has loose tolerance because it depends on the mobility and threshold .

Aluminum is commonly used,it has a temperature coefficient about 3900ppm/C.

1

ox ]])[(L

WC [ DSTGSds VVVr

0

0)(T

TRTR

Counting Squares !!

A corner would be counted as about half a square.

Simple Way to Estimate Resistance

36

Using Unit Resistor Strips

37

Guard Ring Protection

Guard Ring (cont.)

38

39

Layout Matching Interdigitated Style

Layout Matching (Cont.)

40

41

Layout Matching (3)

42

Layout Matching (4) : 2-dimentional style

43

Protection Using Dummy Strips

Polysilicon Resistors

The best choice to implement resistors on silicon so far.

However, conductivity modulation and process gradient are the foes to beat.

44

45

Capacitors on Silicon

Two parallel poly layers are used to construct a capacitors.

Beware of the parasitic (stray) caps.

46

Typical Unit Capacitance

47

Parasitic Caps of the 2-poly Capacitor

48

Capacitor Considerations

1. The capacitance and resistance per unit

area must be referred to the SPICE model

file and the design reference manuals

provided by foundry, e.g., UMC, or TSMC.

2. Another alternative of cap is to utilize the

gate cap of a MOS with the S and D

grounded.

MOSFET

Lateral diffusion

Oxide encroachment

49

Unit Capacitor

50

51

Physical Layout Considerations of MOSFETs

Effective length is shorter than what you draw because of the over-diffusion of S and D.

The parasitic resistance and capacitance can be hand-estimated by counting unit squares

and unit length of the perimeters, respectively.

52

Layout of a long MOS

Snake back and forth or called serpentine style.

53

Layout of a Wide MOS

Have to be a finger type

54

Layout Example

It is in fact a W/(L1 + L2) layout.

Beware of Parasitic Caps

Take NMOS transistors as an example. The transistor with small cap should be away from

GND. Why ?

55

Qualitative Analysis of MOS Caps

Strong inversion vs. depletion

56

Capacitance Layout

C12 = Area(unit capacitance)

57

Layout of Capacitors

To save area and enlarge the cap, we need more layers.

58

Fringing Effect and Shielding

It is almost impossible to avoid. However, we can reduce it as much as we can by layout

skills.

59

60

The standard parallel plate capacitance formula,

H

LW

H

AC

It would be accurate as long as the place dimensions

are much larger than the plate separation H.

---------------------------------------------------------------------

A rough first order correction formula for the

fringing,

2L]2WH

WL[

H

2H)(L2H)(WC

Capacitance Estimation (RF domain)

61

CMOS processes as simply the gate capacitance

of an ordinary transistor.

Capacitance per unit area depends on the dielectric thickness, but it is typically in the range of

1-5 fF/m2.

MOS-based Capacitance

62

Another type of capacitor on silicon is to use a junction capacitance formed by p+ region in an n-

well.

The junction capacitance depends on bias.

n

F

j0

j)/V1(

CC

C j0 : incremental capacitance at zero bias.

VF : amount of forward bias applied across the

junction.

: built-in potential.

n : a parameter depends on the doping profile.

Junction Capacitance

63

Temperature coefficient of a junction

capacitance is

TC]/V-1

1n[n)TC-(1TC

F

si

TCsi is about 250ppm/C

TC (the TC of the built in junction potential) is doping-dependent and typically in the range of

about 1000 ppm/C to 1500 ppm/C

Junction Capacitance (cont.)

64

Interconnect Capacitance

If the IC is working toward RF (radio frequency) range, the interconnect

capacitance becomes very crucial which

might introduce high-freq poles or zeros.

The fringing capacitance is therefore significant. Simple formulas are often

unacceptably inaccurate. We might need to

estimate accurate parasitic capacitance of

interconnects.

65

H

T

HTTHH

W

2})/11)(/2(1ln{

2 CYuan

fringe termfringeless term

It works well as long as the ratio W/H is not too small.

Single Conductor over Ground Plane

66

222.0

Sakurai 8.215.0

CH

T

H

W

H

W

Directly apply function-fitting techniques to the

results of the two-dimensional (2D) field-solver

simulations.

fringe termfringeless term

Its accuracy is superior to Yuans formula at small W/H.

Single Conductor over Ground Plane (cont.)

67

An equation has been developed by Meijis and

Fokkema.

5.025.0

MF 06.177.0 CH

T

H

W

H

W

Its accuracy is better that 1 for dimensions

appropriate to ICs

Single Conductor over Ground Plane (cont.)

68

The capacitive load of a single wire between

two conducting planes can be calculated using

the formula for the previous case as a starting

point.

Sandwiched between Two Conducting

Planes

69

1. Sum only the area terms

2. Add a weighted average of the fringe terms that

compute for each plane separately.

A general function that has more or less the

right kind of behavior (as n approaches infinity)

is,n

nnxx

xxf

/1

2121

2),(

Sandwiched (cont.)

70

The total capacitance of the middle wire of three

adjacent ones over a single conducting plane can be

estimated.

Total capacitance as the sum of two components

is estimated as follows.

1. An ordinary wire-over-ground plane term.

2. The capacitance between the middle wire and its

adjacent neighbors (supposedly).

Three Adjacent Wires over A Single Plane

71

34.1222.0

222.0

07.083.003.0

8.215.1

2

H

S

H

T

H

T

H

WC

H

T

H

WC

CCC

mutual

single

mutualsingletotal

Note : The sum of this two terms is only equal to the

total capacitive load on the center wire.

Three Adjacent Wires over A Single Plane (cont.)

72

Inductor

Spiral Inductors

rn

rnrnL

26

272

0

10 2.1

10 4

L is in henries

n is the number of turns

73

The approximate design of a square spiral inductor

is ,3/1

6

3/1

0 10 2.1

PLPLn

where P is the winding pitch in turns/meter.

---------------------------------------------------------------An inductor design verification via a field solver,

ar

anL

1422

5 .37 220

a is defined as the distance

from the center of the inductor

to the middle of the windings

Inductance Estimation 2D

74

In silicon technology, the substrate is close by and

fairly conductive, creating a parallel plate capacitor

that resonates with the inductor .The resonant

frequency of the LC combination represents the

upper useful frequency limit of the inductor .

Model for on-chip spiral inductor

0

/

2

)1(

tew

lRs

is the conductivity of the material .

l is total length of the winding .

w and t are the width and thickness

of the interconnect .

(skin depth)

Inductance Estimation 3D

75

Inductance Estimation 3D (cont.)

The shunt capacitor Cp,

ox

oxp

twnC

2

tox is the thickness of the oxide between the

crossunder and the main spiral.

-----------------------------------------------------------------

The capacitor between the spiral and the substrate

is Cox,

ox

oxox

tlwC

76

Inductance Estimation 3D (cont.)

The substrate loss is modeled with R1,which accounts

for two distinct mechanisms.

1. loss associated with current flowing into the

substrate through Cox .

2. image currents induced in the substrate by currents

flowing in the spiral above.

subGlwR

21

The capacitance C1 reflects the capacitance of the

substrate as well as other reactive effects related to

the image inductance ,

21

subClwC

Gsub,Csub is the fitting parameter that

is constant for a given substrate and

distance of the spiral to the substrate.

77

Inductance of a bondwire is given by,

75.0

2ln10 275.0

2ln

2

7-0

r

ll

r

llL

Resistance per length as,

rl

R

2

1

Coupled bondwires

Mutual inductance between them is,

l

D

D

llM 1

2ln

2

0

Bondwire Inductor

78

Formula of inductance single-layer coils is ,

lr

rnL

109

10 220

Inductance of a single loop of wire,

0 rL

The error is better than about 25-30.

Inductance Formulas

79

Inductance Formulas (cont.)

2

8ln0

a

rrL

where a is the radius of the wire. The error

is better than about 11.

All loops with equal area have about the

same inductance,

AL 0