ch07 multilevel gate network v5 -...

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU複製母片

CH7 Multilevel Gate NetworkCH7 Multilevel Gate Network

Lecturer：吳安宇Date：2005/10/28

Graduate Institute of Electronics Engineering, NTU

pp. 2台灣大學吳安宇教授

ANDAND--OR and OROR and OR--AND NetworkAND Networkv AND-OR network : A

two-level network composed of a level of AND gate followed by an OR gate at the output.

vOR-AND network : A two-level network composed of a level of OR gate followed by an AND gate at the output.



OROR--ANDAND--OR networkOR networkOR-AND-OR network : A three-level network

composed of a level of OR gates, followed by a level of AND gates, followed by an OR gate at output.



FourFour--Level Realization of ZLevel Realization of Z

4 levels6 gates13 gate inputs

Figure 7-1Four-Level Realization of Z



ThreeThree--Level Realization of ZLevel Realization of Z


Figure 7-2: Three-Level Realization of Z



Network of AND Network of AND andand OR gatesOR gates

Z = (AB+C)(D+E+FG)+H

= AB(D+E)+C(D+E)+ABFG+CFG+H

Gate input ; CostLevel ; SpeedTrade-off among cost & speed !





EXAMPLE OF MULTIEXAMPLE OF MULTI--LEVEL DESIGN (1/6)LEVEL DESIGN (1/6)v Find a network of AND and OR gates to realize

f(a,b,c,d) = Σm(1,5,6,10,13,14)v Consider solutions with two levels of gates and three

levels of gatesv Try to minimize the number of gates and the total number

of gate inputs.v Assume that all variable and their complements are

available as inputs.v Solution: First simplify f

by using Karnaugh map:

(7-1)



MULTIMULTI--LEVEL DESIGN (2/6)LEVEL DESIGN (2/6)

v F = a’c’d + bc’d + bcd’ + acd’

v This leads directly to a two-level AND-OR gate network



MULTIMULTI--LEVEL DESIGN (3/6)LEVEL DESIGN (3/6)

v Factoring (7-1) yieldsF = c’d(a’ + b) + cd’(a + b) (7-2)

vWhich leads to three-level OR-AND-OR gate network:



EXAMPLE OF MULTIEXAMPLE OF MULTI--LEVEL DESIGN (4/6)LEVEL DESIGN (4/6)

v A two-level OR-AND network corresponds to a product-of-sums (POS) expression for the function.

v Obtained from the 0’s on the Karnaugh map:f’ = c’d’ + ab’c’ + cd + a’b’c (7-3)f = (c + d)(a’ + b + c)(c’ + d’)(a + b + c’) (7-4)

vEq. (7-4) leads directly to a two-level OR-AND network:



EXAMPLE OF MULTIEXAMPLE OF MULTI--LEVEL DESIGN (5/6)LEVEL DESIGN (5/6)v To get a 3-level network with an AND gate output, we

partially multiply out Eq. (7-4) using (X+Y)(X+Z) = X + YZ:

f = [c + d(a’ + b)][c’ + d’(a + b)] (7-5)v Eq. (7-5) would require 4 levels of gates to realize it.

v Multiply out d’(a + b) and d(a’ + b) we get

f = (c + a’d + bd)(c’ + ad’ + bd’) (7-6)



EXAMPLE OF MULTIEXAMPLE OF MULTI--LEVEL DESIGN (6/6)LEVEL DESIGN (6/6)

For this particular example:

v the best two-level solution has an AND gate at the output

v the best three-level solution had an OR gate at the output.

v In general, to be sure of obtaining a minimum solution, one must find both the network with the AND-gate output and the one with the OR-gate output.



OutlineOutlinev7.2 Other Types of Logic Gatesv7.3 Two-level NAND- and NOR- Gate

Networkv7.4 Multi-level NAND, NOR-gate circuitsv7.5 Circuit Conversion Using Alternative Gate

Symbolsv7.6 Design of Two-level Multiple-output

Networkv7.7 Multiple-Output NAND and NOR Circuits



NAND gateNAND gatev F = (ABC)’ = A’ + B’ + C’ (DeMorgan’s Law)

General = F = (X1X2…Xn)’ = X1’+X2’+…+Xn’



NOR gateNOR gate

v F = (A+B+C)’ = A’ • B’ • C’ (DeMorgan’s Law)

General form: F = (X1+X2+…+Xn)’ = X1’ •X2’ •… •Xn’



Majority and Minority Gates Majority and Minority Gates (seldom used)(seldom used)

Mabc

FM

mabc

Fm

abc FM Fm

000001010011100101110111

00010111

11101000

vFM = a’bc + ab’c + abc’ + abc = bc + ac +abFm = (bc + ac + ab)’ = (b’ + c’)(a’ + c’)(a’ + b’)



Functionally Complete Set (1/5)Functionally Complete Set (1/5)v A set of logic operations is functionally complete if

any Boolean function can be expressed by this set.

ex. {AND,OR,NOT} f = a’b + b’c + c’a

ex. {AND,NOT} , OR? (X+Y) = [X’•Y’]’ = X+Y(DeMorgan)



Functionally Complete Set (2/5)Functionally Complete Set (2/5)ex. {NAND}

a. (X•X)’ = X’ (NOT) b. [(A•B)’]’ = AB (AND)

c. [A’•B’]’ = A + B (OR)



Functionally Complete Set (3/5)Functionally Complete Set (3/5)ex. {OR,NOT} and {NOR} By yourself!

ex. {Minority gate}

mabc

Fm

Fm = b’c’ + a’b’ + a’c’

a b c Fm

4567

1 0 01 0 11 1 01 1 1

0123

0 0 00 0 10 1 00 1 1

11101000

abc 0 1

00

01

11

10

1

1

11



Functionally Complete Set (4/5)Functionally Complete Set (4/5)ex. If Minority gate is functionally complete?(NOT)

(AND) set A=1, F = B’C’= XY

mx

F = (X’•X’) + (X’•X’) + (X’•X’) = X’

X = B’Y = C’

m

m

m

X

Y

1

X’

Y’

(X’)’•(Y’)’ = X•Y

(a)



Functionally Complete Set (5/5)Functionally Complete Set (5/5)

mm

XY0

X’ + Y’

(X’ + Y’) = XY

mm

1XY

X’•Y’

(X’•Y’)’ = X+Y

(b) Set C = 0, F = A’ + B’, (A’ + B’) = AB (AND)

(OR)



OutlineOutlinev7.1v7.2 Other Types of Logic Gatesv7.3 Two-level NAND- and NOR- Gate

Networkv7.4 Multi-level NAND, NOR-gate circuitsv7.5 Circuit Conversion Using Alternative Gate

Symbolsv7.6 Design of Two-level Multiple-output

Networkv7.7 Multiple-Output NAND and NOR Circuits



DeMorganDeMorgan’’ss LawLawv (X1+X2+…+Xn)’ = X1’•X2’ •…•Xn’

(X1•X2•…•Xn)’ = X1’ + X2’ +…+Xn’

F = A + BC’ + B’CD = [(A+BC’+B’CD)’]’= [A’ •(BC’)’ •(B’CD)’]’= [A’ •(B’+C) •(B+C’+D’)]’= A+(B’+C)’+(B+C’+D’)’

(AND-OR)

(NAND-NAND)

(OR-NAND)

(NOR-OR)



F = A + BC’ + B’CD = [(A+BC’+B’CD)’]’= [A’ •(BC’)’ •(B’CD)’]’= [A’ •(B’+C) •(B+C’+D’)]’= A+(B’+C)’+(B+C’+D’)’

Figure 7Figure 7--14:14:Eight Basic Eight Basic Forms for TwoForms for Two--Level NetworksLevel Networks



To apply NORTo apply NOR--NOR gate (twoNOR gate (two--level)level)

v F = (A+B+C)(A+B’+C’)(A+C’+D)= {[(A+B+C)(A+B’+C’)(A+C’+D)]’}’= {(A+B+C)’+(A+B’+C’)’+(A+C’+D)’}’= (A’B’C’+A’BC+A’CD’)’= (A’B’C’)’•(A’BC)’ •(A’CD’)’

(OR-AND)

(NOR-NOR)(AND-NOR)(NAND-AND)



v F = (A+B+C)(A+B’+C’)(A+C’+D)= {[(A+B+C)(A+B’+C’)(A+C’+D)]’}’= {(A+B+C)’+(A+B’+C’)’+(A+C’+D)’}’= (A’B’C’+A’BC+A’CD’)’= (A’B’C’)’•(A’BC)’ •(A’CD’)’

Figure 7Figure 7--14:14:Eight Basic Eight Basic Forms for TwoForms for Two--Level NetworksLevel Networks



OthersOthersv AND-AND, OR-OR, OR-NOR, AND-NAND, NAND-

NOR, NOR-NAND are degenerate

ex.



Minimum 2Minimum 2--level NANDlevel NAND--NAND network (1/2)NAND network (1/2)

v (1) Find a minimum Sum-of-Productexpression of F

(2) Draw AND-OR (2-level) Network(3) Convert into NAND-NAND Network

v How about NOR-NOR??

ABCD

F

ABCD

F

ABCD

(X’ + Y’) = (XY)’

F = AB + CD (SOP Form)

F



Procedure to design a minimum Procedure to design a minimum NANDNAND--NAND network (twoNAND network (two--level) (2/2)level) (2/2)vFig.7-12 example (p.187)

F = l1+ l2+ …+P1+P2+…= (l1’ l2’•…•P1’•P2’•…)’



A procedure to design minimum 2A procedure to design minimum 2--level NORlevel NOR--NOR networkNOR network

Å Draw the two-level OR-AND networkÇ Find a minimum POS expression of FÉ Replace all gates with NOR gates

abcd

abcd

F F



OutlineOutlinev 7.1v 7.2 Other Types of Logic Gatesv 7.3 Two-level NAND- and NOR- Gate

Networkv 7.4 Multi-level NAND, NOR-gate circuitsv 7.5 Circuit Conversion Using Alternative Gate

Symbolsv 7.6 Design of Two-level Multiple-output

Networkv 7.7 Multiple-Output NAND and NOR Circuits



Procedure Procedure 1) Simplify the switching function.2) Convert into multi-level AND-OR network.3) Output gate is level 1, mark all levels.4) Leave inputs to levels 2,4,6,…unchanged.5) Invert inputs to levels 1,3,5,…



Design exampleDesign examplevF1 = a’ [ b’ + c(d + e’) + f’g’ ] + hi’j + k



OutlineOutline

v 7.2 Other Types of Logic Gatesv 7.3 Two-level NAND- and NOR- Gate






Gate SymbolsGate Symbols



Conversion of NAND gate networkConversion of NAND gate network



Conversion to NOR GatesConversion to NOR Gatesv Even if AND and OR gates do not alternate, we can

still convert an AND-OR circuit into a NAND OR NOR circuit, but may need extra inverters.

Figure 7-16Conversion to NOR Gates

Start with level 1

NOR Gate



Conversion of ANDConversion of AND--OR Circuit to OR Circuit to NAND GatesNAND Gates

Figure 7-17Conversion of AND-OR Circuit to NAND Gates

(1) 換成NAND gates

(2) Cannot cancel=> Inverter

(3) NAND gates Implement

NAND Gate



OutlineOutlinev 7.1v 7.2 Other Types of Logic Gatesv 7.3 Two-level NAND- and NOR- Gate






Design of a Logic Network with four Design of a Logic Network with four inputs and three outputsinputs and three outputs

F1(A,B,C,D) = Σm(11,12,13,14,15)F2(A,B,C,D) = Σm(3,7,11,12,13,15)F3(A,B,C,D) = Σm(3,7,12,13,14,15)

ACD CD A’CD



Logic Network Realization (1/2)Logic Network Realization (1/2)

CDAB

AB is shared (F1&F3)CD = A’CD + ACD (F1, F3 à F2)

DirectImplementation

9 gates21 gate

inputs



Logic Network Realization (2/2)Logic Network Realization (2/2)

v Note thatv AB is shared by F1

and F3v CD = ACD + A’CD

= CD(A + A’)

7 gates 18 gate inputs

=> Use of a minimum SOP => minimum cost solution

Guideline:(1) Minimize the total number of gates.(2) If the number of gates is the same, the one with minimum

number of gate input is chosen.



AA 44--inputs/3inputs/3--outputs outputs design (Fig.7.21)design (Fig.7.21)v f1 = Σm(2,3,5,7,8,9,10,11,13,15)

f2 = Σm(2,3,5,6,7,10,11,14,15)f3 = Σm(6,7,8,9,13,14,15) Figure 7-21

vbd (f1) à a’bd (f2) + abd (f3)vab’c’ (f1) à covered by ab’c’ (f3)



Example: A 4Example: A 4--inputs/3inputs/3--outputs design outputs design vIf each function is minimized separately,

=> f1 = bd + ab’ + b’cf2 = c + a’bdf3 = bc + ab’c’ +

vCheck K-map to see common minterms=> f1 = a’bd + abd + ab’c’ + b’c

f2 = c + a’bdf3 = bc + ab’c’ + abd

abdac’d

⇒10 gates25 gate inputs

⇒8 gates22 gate inputs



Case I (Fig. 7.22)Case I (Fig. 7.22)

(a) NOT to combine 1 with adjacent 1’s(b) c’d is essential to f1 for multiple-output realization

abd is not essential for multiple-output realization

But it is essential to f1 (cover m15)

c’d

abd



Case II (Fig. 7.23)Case II (Fig. 7.23)

(a) max number of common terms is not best(b) m2 = cover by a’d’ (essential to f1 & all)

m5 = cover by a’bc (essential to f1 & all)m12 = cover by bd’ (essential to f2 & all)

Å Basic = Identify EPI to all functionsÇ However, it cannot be applied to 7-21!É Very difficult to find global optimal solution!!



Determination of essential prime Determination of essential prime implicantsimplicants for for multiple output realization (1/2)multiple output realization (1/2)

v PI’s essential to an individual function may not be essential to the multiple-output realization.e.g. (Fig 7-22) bd is EPI to f1 (cover m5), but it is not

essential (m5 also appear on f2 map).

vModified procedure: check each 1 on the map to see if it is covered by only one PI.

v (Fig.7-22) cd’ is essential to f1 (m1)abd is not. (f1 and f2)



Determination of essential prime Determination of essential prime implicantsimplicants for for multiple output realization (2/2)multiple output realization (2/2)

v (Fig 7-23) m2 and m5 of f1 are not covered by f2Å m2 is covered by f1 (a’d’), a’d’ is essential to f1Ç M5 is covered by a’bc’ of f2, a’bc’ is essential to f2

on f2 map, bd’ is essential (Why?) (Check) É Once the EPI of f1 & f2 are looped, selection of

the remaining terms to form thr minimum solution is obvious.

v (Fig 7-21) Every minterm of f1 are covered by f2 & f3à More sophisticated solution is needed



MultipleMultiple--Output NAND and NOR CircuitsOutput NAND and NOR Circuitsv If all of the output gates are OR gates,

direct conversion to a NAND-gate circuit is possible.

v If all of the output gates are AND, direct conversion to a NOR-gatecircuit is possible.

v Figure 7-24:1-output circuit to NOR gates.

v Note that the inputs to the first and third levels of NOR gates are inverted.

F1 = [(a + b’)c + d](e’ + f) F2 = [(a + b’)c + g’](e’ + f)h

Figure 7-24

ch07 multilevel gate network v5 -...

Documents