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Synchronous Sequential Logic

MEC520 디지털 공학

Jee-Hwan Ryu

School of Mechanical Engineering

Korea University of Technology and Education


Outputs are function of inputs and present states

Present states are supplied by memory elements

Sequential Circuits


Two types of sequential circuit

Synchronous : behavior depends on the signals affecting storage elements at discrete time

Asynchronous : behavior depends on inputs at any instance of time, many difficulties on designers

Flip-flop: The storage elements used in clocked sequential circuits.

Sequential Circuits


Latches

The most basic types of flip-flops operate with signal levels

The latches introduced here are the basic circuits from which all flip-flops are constructed

Useful forStoring binary information

For the design of asynchronous sequential circuits

Not practical for use in synchronous sequential circuits


SR Latch

Consist of two cross-coupled NOR gatesS=1,R=0 then Q=1(set)

S=0,R=1 then Q=0(reset)

S=0,R=0 then no change (keep condition)

S=1,R=1 Q=Q′=0 (undefined)


Require the complement value of NOR latch

S′R′ Latch with NAND Gates


Add two NAND gate and control signal

C=0(no action), C=1(act as SR latch)

SR Latch with Control Input


SR Latch as a Debouncing Switch


Eliminate indeterminate state in SR latch

C=1, output value is equal to D (transparent)

D Latch


Application of D Latch

Output Q is retained until the clock is enabled again, even though the data input is changed


Graphic Symbols for Latches

S

R

SR

S

R

SR

D

C

D


Latch : output changes as input changes while the clock pulse is in the logic 1, case (a)

Unpredictable situation due to continuous state changing

Flip-flop : output only changes at clock edge

Flip-Flops


Negative edge triggered D flip-flopCLK=0 : master disable, slave enable

CLK=1 : master enable, slave disable

Positive edge triggered D flip-flopAttach inverter on the other way

Master-Slave D Flip-Flop


Negative Edge Triggered M-S D Flip-Flop


Consist of 3 SR-latches

When CLK=0, S=R=1 -> state is maintained

Q changes only when CLK becomes 0 to 1, no change when 1->0

If D=0 when CLK->1, R->0 (Reset state, Q=0)

If D->1 while CLK=1, R remains at 0

CLK->0, R->1, State is maintained

If D=1 when CLK->1, S->0 (Set state, Q=1)

D-type Positive Edge Triggered Flip-Flop

Dynamic


CLK

D

Q

Q’

Figure: Positive edge triggered D flip-flop timing diagram

D-type Positive Edge Triggered Flip Flop


CLK

D

Q

Q’

Q

Q’

Figure: Negetive edge triggered D flip-flop timing diagram

D-type Negative Edge Triggered Flip Flop


Performs three operations

Set(J=1,K=0), Reset(J=0,K=1), Complement(J=K=1)

D=JQ′+K′Q

J=1,K=0: D=Q’+Q=1->Sets Q=1 at the next clock edge

J=0,K=1: D=0 -> Resets Q=0 at the next clock edge

J=K=1: D=Q’ (Complement), J=K=0: D=Q (Unchanged)

JK Flip-Flop


Complementing flip-flop

From D flip-flopD=TQ′+T′Q

T Flip-Flop


CLK

T

Q

Q’

Figure: Positive edge triggered T flip-flop timing diagram

T Flip-Flop Positive Edge Triggered


Flip-flop characteristic tablesQ(t): present state prior to the application of a clock edge

Q(t+1): next state one clock period later

Characteristic Tables


D-flip flopQ(t+1)=D

J-K flip flopQ(t+1)=JQ’+K’Q

T flip flopQ(t+1)=TQ’+T’Q

Characteristic Equations


Direct Inputs

For bringing all flip-flops in the system to a known starting state prior to the clocked operation

Q

Q

S

R

CLK

Reset

D

(a) Circuit diagram

D Q

QR

C

(b) Graphic symbol

Data

CLK

Reset

R

011

C

X↑↑

D

X01

Q

001

Q

110

(b) Function table


Behavior of clocked sequential circuit is determined from input, output and present state

Output and next state are a function of input and present state

In this section, we introduce an algebraic representation for specifying the next-state condition in terms of the present state and inputs

Analysis Of Clocked Sequential Circuits


Specifies the next state and output as a function of the present state and inputs

A(t+1)=A(t)x(t) + B(t)x(t)

B(t+1)=A′(t)x(t)

y(t)=(A(t)+B(t))x′(t)

t+1: one clock edge later

State Equations (Transition Equations)


Time sequence of inputs, outputs, and flip-flop states

Two types of state table exist

One form may be preferable over the other, depending on the application

State Table (Transition Table)


A kind of flow diagram

Can be derived from state tableState-circle, transition-line, I/O

State Diagram


Analysis with D Flip-Flops

Input equation :

D flip-flop with output A

State equation is equal to input equation

( ) yxAtA ⊕⊕=+1

No output, slash is not needed


Analysis with JK Flip-Flops

State equation is not the same as the input equation

Have to refer characteristic table or characteristic equation

Flip-flop Input equations

BAxAxAKxJ

xBKBJ

BB

AA

⊕=′+′=′=

′==


Analysis with JK Flip-Flops

State table and state diagram

( )( )( ) ( )( ) ( ) xBAABxxBBxABxtB

AxBABAAxBABtA

BKBJtB

AKAJtA

′′++′′=′⊕+′′=+

+′+′=′′+′=+

′+′=+

′+′=+

1

1

1

1


Analysis with T Flip-Flops

Input equations and output equation

TA=Bx, TB=x

y=AB

State equations are derived from characteristic equation

( ) ( ) ( )( ) BxtB

BxAxABAABxABxtA

⊕=+

′+′+′=′+′=+1

1


Analysis with T Flip-Flops

State/output Input


A sequential circuit with two D flip-flops, A and B; two inputs, x and y; and one output, z, is specified by the following next-state and output equations:

A(t+1) = x’y + xA(t)

B(t+1) = x’B(t) + xA(t)

Z = B(t)

(a) Draw the logic diagram of the circuit.

(b) List the state table for the sequential circuit.

(c) Draw the corresponding state diagram.

Example


Mealy model : output is a function of the present state and input

Inputs must be synchronized with the clock

Outputs must be sampled at the clock edge

Moore model : output is a function of the present state only

Outputs are synchronized with the clock

Mealy and Moore Models


Sequential circuit design: requires state table

⇔ Combinational circuit : truth table

The number of flip-flop is determined from the number of states in circuit

If 2ⁿ states exist, there are n flip-flops

Once the type and number of flip-flops are determined

Sequential circuit problem is transformed into a combinational circuit problem

Design Procedure


Design steps

1) Derive a state diagram or state table

2) Reduce the number of states if necessary

3) Assign binary values to the states

4) Obtain the binary-coded state table

5) Choose the type of flip-flops to be used

6) Derive the flip-flop input equations and output equations

7) Draw the logic diagram

Design Procedure


Sequential detectorThree or more consecutive 1’s in a string of bits coming through an input line

0

Derive a State Diagram


0

• State Assign as followings

• 4 States -> 2 bit assign

• S0 = 00

• S1 = 01

• S2 = 10

• S3 = 11

Assign Binary Values To The States


0

Obtain The Binary-coded State Table


∑∑∑

=

==+

==+

)7,6(),,(

)7,5,1(),,()1(

)7,5,3(),,()1(

xBAy

xBADtB

xBADtA

B

A

Input equations are obtained directly from the next states

Synthesis using D Flip-Flops


Draw the Logic Diagram


Excitation Table

Q(t) Q(t+1) J K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

Q(t) Q(t+1) T

0 0 00 1 11 0 11 1 0


Input equations evaluated from the present state to next state transition

Y = Ax

Synthesis with JK Flip-Flops


Synthesis using JK Flip-Flops


Example

Synthesis using T flip-flops

- Design with T flip-flops


Synthesis using T flip-flops

3-bit binary counter

3-bit counter has 3 flip-flops and can count from 0 to 2ⁿ-1(n=3)


TA2 A1 A0 TA1 A0 TA0 1

A2

A1

A0

1

1

1 1

1 1

1 1

1

1

1 1

1

1

Synthesis using T Flip-Flops


1. Synthesis the 3-bit binary counter using D flip-flop

2. Synthesis the 3-bit binary counter using J-K flip-flop

Example

chapter5 synchronous sequential logiciris.kaist.ac.kr/download/dd/chapter5_synchronous... ·...

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