chapter6-fpga module and interface designtylee/courses/chapter6... · chapter 6 fpga modules and...

Chapter 6Chapter 6

FPGA Modules and Hardware Interface DesignFPGA Modules and Hardware Interface Design

Professor Professor TzyyTzyy--KuenKuen TienTienEE--mail mail tktienmailstutedutwtktienmailstutedutw

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P-293教育部顧問室PAL聯盟系統雛型與軟硬體整合設計第六章FPGA模組與硬體介面設計

OutlineOutline61 The Implementation of IDCT on FPGA61 The Implementation of IDCT on FPGA62 AMBA IO Interface Design62 AMBA IO Interface Design63 IO Interface Design63 IO Interface Design


61 The Implementation of IDCT on FPGA61 The Implementation of IDCT on FPGA6161 The Implementation of IDCT on FPGAThe Implementation of IDCT on FPGA62 AMBA IO Interface Design62 AMBA IO Interface Design63 IO Interface Design63 IO Interface Design


61 CompressionDecompression System61 CompressionDecompression SystemA block diagram of a compressiondecompression system

DCTIDCT can be used in the system to reduce the bandwidth requirements


61 Introduction to IDCT61 Introduction to IDCTInverse Discrete Cosine Transform

IDCT is used to decompress DCT compressed data in the decoder

IDCT is one of the most computation-intensive parts of the MPEG decoding process

A fast hardware based IDCT implementation is crucial to speed the MPEG decoding process


61 2D IDCT Equations (12)61 2D IDCT Equations (12)The algorithm used for the calculation of the 2D IDCT coefficients is based on the following equation

First the 1D DCT of the rows are calculated and then the 1D IDCT of the columns are calculated

XCpq = sum sum XNmn middotM-1 N-1

m = 0 n = 0

c(p)c(q)

4middotcos

Π(2m+1)p

2Mmiddotcos

Π(2n+1)q

2N(EQ 1)


61 2D IDCT Equations (22)61 2D IDCT Equations (22)The 1D IDCT coefficients for the rows and columns can be calculated by separating equation 1 into the row part and the column part

C = K middot cos(2middotcol number + 1) middot row number middotΠ

2 middot M

K = radic1N

for row = 0radic2

K = N for row ne 0

Ct = K middot cos(2middotrow number + 1) middot col number middotΠ

2 middot N

K = radic1M

for col = 0 K = radic2

for col ne 0M

(EQ 2)

(EQ 3)

M = total number of columns N = total number of rows


61 Constant Values of C and C61 Constant Values of C and Ctt

The constant values for C and Ct calculated from equations 2 and 3 are as follows

23170 23170 23170 23170 23170 23170 23170 2317032138 27246 18205 6393 ndash6393 ndash18205 ndash27246 ndash3213830274 12540 ndash12540 ndash30274 ndash30274 ndash12540 12540 3027427246 ndash6393 ndash32138 ndash18205 18205 32138 6393 ndash2724623170 ndash23170 ndash23170 23170 23170 ndash23170 ndash23170 2317018205 ndash32138 6393 27246 ndash27246 ndash6393 32138 ndash1820512540 ndash30274 30274 ndash12540 ndash12540 30274 ndash30274 125406393 ndash18205 27246 ndash32138 32138 ndash27246 18205 ndash6393

C =

Ct =

23170 32138 30274 27246 23170 18205 12540 639323170 27246 12540 ndash6393 ndash23170 ndash32138 ndash30274 ndash1820523170 18205 ndash12540 ndash32138 ndash23170 6393 30274 2724623170 6393 ndash30274 ndash18205 23170 27246 ndash12540 ndash3213823170 ndash6393 ndash30274 18205 23170 ndash27246 ndash12540 3213823170 ndash18205 ndash12540 32138 ndash23170 ndash6393 30274 ndash2724623170 ndash27246 12540 6393 ndash23170 32138 ndash30274 1820523170 ndash32138 30274 ndash27246 23170 ndash18205 12540 ndash6393


61 2D IDCT using Vector Processing61 2D IDCT using Vector ProcessingA one-dimensional 8-point IDCT followed by an internal double buffer memory followed by another one-dimensional 8-point IDCT provides the 2D IDCT architecture

Vector processing using parallel multipliers is a method used for implementation of IDCTAdvantages of vector processing method

Regular structure simple control and interconnect good balancebetween performance and complexity of implementation

1D IDCT RAM DoubleBuffer 1D IDCT


61 Behavioral Model (12)61 Behavioral Model (12)The output Y of an 88 IDCT for input X is given by Y = CXCt where C is the cosine coefficients and Ct is the transpose coefficientsThe equation can also be written as Y = CtZ where Z = XC

X =

x00 x01 x02 x03 x04 x05 x06 x07x10 x11 x12 x13 x14 x15 x16 x17x20 x21 x22 x23 x24 x25 x26 x27x30 x31 x32 x33 x34 x35 x36 x37x40 x41 x42 x43 x44 x45 x46 x47x50 x51 x52 x53 x54 x55 x56 x57x60 x61 x62 x63 x64 x65 x66 x67x70 x71 x72 x73 x74 x75 x76 x77

C =



61 Behavioral Model (22)61 Behavioral Model (22)Z(00) = 23170x00 + 32138x01 + 30274x02 + 27246x03 + 23170x04 + 18205x05 + 12540x06 + 6393x07Z(01) = 23170x00 + 27246x01 + 12540x02 ndash 6393x03 ndash 23170x04 ndash 3213805 ndash 30274x06 ndash 18205x07Z(02) = 23170x00 + 18205x01 ndash 12540x02 ndash 32138x03 ndash 23170x04 + 6393x05 + 30274x06 + 27246x07Z(03) = 23170x00 + 6393x01 ndash 30274x02 ndash 18205x03 + 23170x04 + 27246x05 ndash 12540x06 ndash 3213807Z(04) = 23170x00 ndash 6393x01 ndash 30274x02 + 18205x03 + 23170x04 ndash 27246x05 ndash 12540x06 + 32138x07Z(05) = 23170x00 ndash 18205x01 ndash 12540x02 + 32138x03 ndash 23170x04 ndash 6393x05 + 30274x06 ndash 27246x07Z(06) = 23170x00 ndash 27246x01 + 12540x02 + 6393x03 ndash 23170x04 + 32138x05 ndash 30274x06 + 18205x07Z(07) = 23170x00 ndash 32138x01 + 30274x02 ndash 27246x03 + 23170x04 ndash 18205x05 + 12540x06 ndash 6393x07

OrZ(k0) = (23170xk0 + 30274xk2 + 23170xk4 + 12540xk6) + (32138xk1 + 27246xk3 + 18205xk5 + 6393xk7)

= P01 + P02Z(k1) = (23170xk0 + 12540xk2 ndash 23170xk4 ndash 30274xk6) + (27246xk1 ndash 6393xk3 ndash 32138xk5 ndash 18205xk7)

= P11 + P12Z(k2) = (23170xk0 ndash 12540xk2 ndash 23170xk4 + 30274xk6) + (18205xk1 ndash 32138xk3 + 6393xk5 + 27246xk7)

= P21 + P22Z(k3) = (23170xk0 ndash 30274xk2 + 23170xk4 ndash 12540xk6) + (6393xk1 ndash 18205xk3 + 27246xk5 ndash 32138xk7)

= P31 + P32Z(k4) = P31 ndash P32Z(k5) = P21 ndash P22Z(k6) = P11 ndash P12Z(k7) = P01 ndash P02where k = 0 2 hellip 7


61 1D IDCT61 1D IDCTThe block diagram for the implementation of the 1D IDCT is shown below


62 AMBA IO Interface Design62 AMBA IO Interface Design61 The Implementation of IDCT on FPGA61 The Implementation of IDCT on FPGA6262 AMBA IO Interface DesignAMBA IO Interface Design63 IO Interface Design63 IO Interface Design


62 AMBA IO Interface Design62 AMBA IO Interface DesignIntroduction to the AMBA busesIntroduction to the AMBA busesAMBA AHB busAMBA AHB busAMBA ASB busAMBA ASB busAMBA APB busAMBA APB bus


62 62 IntroductionIntroduction (15)(15)What is AMBA

The Advanced Microcontroller Bus Architecture specificationAn on-chip communication standard for designing high-performance embedded microcontroller

Three distinct busesAHB (the Advanced High-performance Bus)

High-performance system backbone busASB (the Advanced System Bus)

An alternative system busAPB (the Advanced Peripheral Bus)

Minimal power consumptionReduced interface complexity


62 62 Introduction Introduction (25)(25)Objectives of the AMBA specification

To facilitate the right-first-time development of embedded microcontroller productsTo be technology-independentTo ensure that highly reusable peripheral and system macrocellscan be migrated across a diverse range of IC processesTo encourage modular system designTo minimize the silicon infrastructure required for both operation and manufacturing test


62 62 IntroductionIntroduction (35)(35)Typical AMBA system

High-bandwidthExternal Memory

Interface

High-bandwidthOn-chip RAM

High-performanceARM-processor

DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge


62 62 IntroductionIntroduction (45)(45)

ASB decoderAHB decoderASB arbiterAHB arbiter

APB slaveASB slaveAHB slave

APB bridge (slave on AHB or ASB)ASB masterAHB masterComponents

Wider data bus configuration

Single-clock edge operation (rising edge)

Single-cycle bus master handover


Dual-clock edge operationSplit transactions

Suitable for many peripheralsBurst transfersBurst transfers

Simple interfaceMultiple bus mastersMultiple bus mastersLatched address and controlPipelined operationPipelined operationLow powerHigh performanceHigh performanceFeatureAMBA APBAMBA ASBAMBA AHB

Feature


62 62 IntroductionIntroduction (55)(55)When to use AMBA AHBASB or APB

A full AHB or ASBBus mastersOn-chip memory blocksExternal memory interfaceHigh-bandwidth peripherals with FIFO interfacesDMA slave peripherals

A simple APB interfaceSimple register-mapped slave devicesVery low power interfaces where clocks cannot be globally routedGrouping narrow-bus peripherals to avoid loading the system bus




62 A Typical 62 A Typical AAHB and APB SystemHB and APB System

High-bandwidthMemory Interface

High-bandwidthon-chip RAM


DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge

AMBA Advanced High-performance Bus (AHB)

High performance

Pipelined operation

Burst transfers

Multiple bus masters

Split transactions

AMBA Advanced Peripheral Bus (APB)

Low power

Latched address and control

Simple interface

Suitable for many peripherals


62 62 AMBA AHB AMBA AHB Signal List [13]Signal List [13]HCLK bus clockHRESETn resetHADDR[310] address busHTRANS[10] transfer type

NONSEQ SEQ IDLE and BUSYHWRITE transfer directionHSIZE[20] transfer size

Byte (8-bit) halfword (16-bit) word (32-bit) hellip 1024bits


62 62 AMBA AHB AMBA AHB Signal List [23]Signal List [23]HBURST[20] burst type

4 8 and 16 beats are supportedIncrementing or wrapping

HPROT[30] protection controlPrivileged mode access or user mode accessInstruction fetch or data access

HWDATA[310] write data busHRDATA[310] read data busHSEL slave selectHREADY transfer doneHRESP[10] transfer response

OKAY ERROR RETRY and SPLIT


62 62 AMBA AHB AMBA AHB Signal List [33]Signal List [33]HBUSREQx bus request

Up to a maximum of 16 bus mastersHLOCKx locked transfersHGRANTx bus grantHMASTER[30] master numberHMASTLOCK locked sequenceHSPLITx[150] split completion request


62 62 AMBA AHB AMBA AHB Bus InterconnectBus InterconnectMultiplexor interconnection

HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

Address andcontrol mux

Write data muxRead data mux


62 Timing Diagram Conventions62 Timing Diagram ConventionsKey to timing diagram conventions

Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus


62 62 AMBA AHB AMBA AHB Operation [13]Operation [13]Basic transfer

The address phase lasts only a single cycleThe data phase may require several cycles achieved by HREADY signal

A

Control

Data(A)

Data(A)

Address phase Data phase

HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master


62 62 AMBA AHB AMBA AHB Operation [23]Operation [23]Basic transfer with wait states

A

ControlControl

HCLK

HADDR [310]

HWDATA [310] Data(A)

HREADY

HRDATA [310]Data(A)


Slave inserts a wait state


62 62 AMBA AHB AMBA AHB Operation [33]Operation [33]Multiple transfers

Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]

Wait state for address B


62 62 AMBA AHB AMBA AHB Transfer TypeTransfer TypeTransfer type encoding

HTRANS[10]00 ndash IDLENo data transfer is required01 ndash BUSYBus masters insert IDLE cycles in the middle of bursts of

transfers10 ndash NONSEQThe first transfer of a burst or a single transfer is initiated11 ndash SEQThe remaining transfers are in a burstThe address is related to the previous transfer


62 Example of 62 Example of AMBA AHB AMBA AHB TransferTransferDifferent transfer types

HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR


62 62 AMBA AHB AMBA AHB Burst OperationBurst OperationBurst signal encoding

HBURST[20]000 ndash SINGLE001 ndash INCR (Incrementing burst of unspecified length)010 ndash WRAP4 (4-beat wrapping burst)011 ndash INCR4 (4-beat incrementing burst)100 ndash WRAP8101 ndash INCR8110 ndash WRAP16111 ndash INCR16

Bursts must not cross a 1kB address boundaryAll transfers within a burst must be aligned to the address boundary equal to the size of the transferEarly burst termination


62 62 AMBA AHB AMBA AHB Burst Operation [13]Burst Operation [13]Four-beat wrapping burst

NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4

Control for burstSIZE = Word

HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY

HPROT [30]HSIZE [20]

HWRITE

T1 T2 T3 T4 T5 T6 T 7


62 62 AMBA AHB AMBA AHB Burst Operation [23]Burst Operation [23]Four-beat incrementing burst

NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7


62 62 AMBA AHB AMBA AHB Burst Operation [33]Burst Operation [33]Undefined length burst

HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8

NONSEQ SEQ NONSEQ SEQ SEQ

0 x20 0x22 0x5C 0 x60 0x64

INCR INCR

Control for burstSIZE = Halfword


Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)


62 62 AMBA AHB AMBA AHB Transfer SizeTransfer SizeSize encoding

HSIZE[20]000 ndash byte (8 bits)001 ndash halfword (16 bits)010 ndash word (32 bits)011 ndash 64 bits100 ndash 128 bits101 ndash 256 bits110 ndash 512 bits111 ndash 1024 bits


62 62 AMBA AHB AMBA AHB Protection ControlProtection ControlProtection signal encodings

HPROT[30]HPROT[3] ndash cacheableHPROT[2] ndash bufferableHPROT[1] ndash privilegedHPROT[0] ndash dataopcode

MMU (memory management unit) uses these protection control signals


62 Slave Transfer Responses62 Slave Transfer ResponsesResponse encoding

HRESP[10]00 ndash OKAY01 ndash ERROR10 ndash RETRYThe signal shows the transfer has not yet completed so the

bus master should retry the transfer11 ndash SPLITThe slave will request access to the bus on behalf of the

master when the transfer can complete

If the response is the one among ERROR RETRY and SPLIT a two-cycle response is required


62 Example of RETRY Operation62 Example of RETRY OperationTransfer with retry response

HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]

NONSEQ SEQ IDLE NONSEQ

A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5


62 62 AMBA AHB AMBA AHB BBusus ArbitrationArbitrationBus master grant signals

The HGRANTx signal is only used by the master to determine when it owns the bus

DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter


62 AMBA AHB Bus Slave62 AMBA AHB Bus SlaveAHB bus slave interface

AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse


62 AMBA AHB Bus Master62 AMBA AHB Bus MasterAHB bus master interface

AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data


62 AMBA AHB Arbiter62 AMBA AHB ArbiterAHB arbiter interface

AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY




62 A Typical AMBA ASB62 A Typical AMBA ASB--based Microcontrollerbased MicrocontrollerA typical AMBA system




DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge

AMBA Advanced System Bus (ASB)

High performance

Pipelined operation

Burst transfers



Low power


Simple interface



62 AMBA ASB Description62 AMBA ASB DescriptionBasic flow of the bus operation

The arbiter determines which master is granted access to the busWhen granted a master initiates transfers on the busThe decoder uses the high order address lines to select a bus slaveThe slave provides a transfer response back lines to the bus master and data is transferred between the master and slave


62 ASB Transfers62 ASB TransfersThree types of transfer

NONSEQUENTIALUsed for signal transfers or the first transfer of a burst

SEQUENTIALUsed for transfers in a burst The address of a SEQUENTIAL transfer is always related to the previous transfer

ADDRESS-ONLYUsed when no data movement is required


62 62 NonsequentialNonsequential TransferTransferA typical NONSEQUENTIAL read transfer including wait states

BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read


62 Sequential Transfer62 Sequential TransferA SEQUENTIAL transfer with one wait state


62 Address62 Address--only Transferonly TransferThe ADDRESS-ONLY transfer can be used in three different ways

As a true IDLE cycleTo speculatively broadcast an address for the next transfer without committing to the transferTo provide a turnaround cycle during bus master handover


62 AMBA ASB Address Decode62 AMBA ASB Address DecodeIn an ASB-based AMBA system the address decoding is performed by a centralized decoder


62 Transfer Response62 Transfer ResponseThe transfer response is provided using the BWAIT BERROR and BLAST signals

BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]


62 AMBA ASB Bus Slave62 AMBA ASB Bus SlaveASB bus slave interface

ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data


62 AMBS ASB Bus Master62 AMBS ASB Bus MasterASB bus master interface

ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data


62 AMBA ASB Bus Decoder62 AMBA ASB Bus DecoderASB decoder interface

ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse


62 AMBA ASB Bus Arbiter62 AMBA ASB Bus ArbiterASB arbiter interface

ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants


6262 AMBA IO Interface DesignAMBA IO Interface DesignIntroduction to the AMBA busesIntroduction to the AMBA busesAMBA AHB busAMBA AHB busAMBA ASB busAMBA ASB busAMBA APB busAMBA APB bus


62 A Typical AMBA62 A Typical AMBA--based Microcontrollerbased MicrocontrollerAMBA Advanced Peripheral Bus (APB)




DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface



62 62 AMBA APB AMBA APB BBusus SignalsSignalsAMBA APB Signal list

PCLKPRESETnPADDR[310]PSELxPENABLEPWRITEPRDATAPWDATA


62 62 AvtivityAvtivity of the Peripheral Busof the Peripheral BusState diagram

IDLEThe default state for the peripheral bus

SETUPThe bus moves into this state when a transfer is requiredThe bus remains in the SETUP state for one clock and will always move to the ENABLE statePSELx is asserted

ENABLEPENABLE is assertedThe address write and select signals all remain stable during SETUP ENABLEGlitch is acceptable during ENABLE SETUP

No transfer

Transfer

TransferNo transfer


62 62 AMBA APB AMBA APB Interface DesignInterface DesignAPB bridge interface

APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data

System busslave interface

PRDATARead data

PRESETn

PCLKReset

Clock


62 62 AMBA APB AMBA APB SlaveSlaveAPB slave interface

APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data


62 62 Interfacing APB to AHBInterfacing APB to AHBA read transfer

T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers


63 IO Interface Design63 IO Interface Design61 The Implementation of IDCT on FPGA61 The Implementation of IDCT on FPGA62 AMBA IO Interface Design62 AMBA IO Interface Design63 IO Interface Design63 IO Interface Design


63 IO Interface63 IO InterfaceProvides a method for transferring information between CPU (or internal storage) and external IO devices

IO devices connected to a computer need special communication links for interfacing them with the CPU


63 Purposes of the Communication Link63 Purposes of the Communication LinkConversion of signal values

The manner of operation for an IO device may be different from the operation of the CPU

Providing a synchronization mechanismThe data transfer rate of IO devices is usually slower than the transfer rate of the CPU

Word format transformationData codes and formats in IO differ from the word format in the CPU

The control of IO devicesTo ensure the operation of an IO device is not disturbed by another IO devices


63 IO Bus and Interface Modules63 IO Bus and Interface ModulesThe IO bus consists of data lines address lines and control lines

ProcessorDataAddressControl

Processor Interface Interface Interface

Keyboardand

displayterminal

Printer Magneticdisk

Magnetictape


63 IO versus Memory Bus63 IO versus Memory BusThere are three ways that computer buses can be used to communicate with memory and IO

Use two separate buses one for memory and the other for IOUse one common bus for both memory and IO but have

separate control lines for eachUse one common bus for memory and IO with common control lines


63 Isolated versus Memory63 Isolated versus Memory--Mapped IOMapped IOIsolated IO

Isolate all IO interface addresses from the addresses assigned to memoryDistinct input and output instructions for IO transfer

Memory-mapped IOUse the same address space for both memory and IONo specific input or output instructionsThe CPU manipulates IO data with the same instructionsthat are used to manipulate memory words


63 Example of IO Interface63 Example of IO Interface

CS RS1 RS0 Register selected

0 X X None data bus in high-impedance1 0 0 Port A register1 0 1 Port B register1 1 0 Control register1 1 1 Status register


63 Asynchronous Data Transfer63 Asynchronous Data TransferAsynchronous data transfer between two independent units requires control signals to transmit dataTwo different types of control mechanism for data transferring between two independent units

Strobe controlHandshaking


63 Strobe Control (13)63 Strobe Control (13)The strobe control method employs a single control line to time each transfer

The strobe may be activated by either the source or the destination


Source-initiated strobe for data transfer

63 Strobe Control (23)63 Strobe Control (23)

Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram


Destination-initiated strobe for data transfer


Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram


63 Problem of Strobe Method63 Problem of Strobe MethodThe disadvantage of the strobe method is that the source (destination) unit that initiates the transfer has no way of knowing whether the destination (source) unit has actually received the data item that was placed in the bus


63 Handshaking63 HandshakingThe basic principle of the two-wire handshaking method of data transfer is as follows

One control line from the source unit is used to inform the destination whether there are valid data in the busThe other control line from the destination unit is used to inform the source whether it can accept data


63 Data Transfer by Handshaking (12)63 Data Transfer by Handshaking (12)Data transfer procedure initiated by the source

Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted

Place data on busEnable data valid

Disable data validInvalidate data on bus

Accept data from busEnable data accepted

Disable data acceptedReady to accept data

(initial state)

(c) Sequence of events

Source unit Destination unit


63 Data Transfer by Handshaking (22)63 Data Transfer by Handshaking (22)Data transfer procedure initiated by the destination

Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)

Ready to accept dataEnable ready for data

Accept data from busDisable ready for data


Source unit

Destination unit


63 Asynchronous Serial Transfer63 Asynchronous Serial TransferA serial asynchronous data transmission technique employs special bits that are inserted at both ends of the character codeWith this technique each character consists of three parts

A start bitThe character bitsStop bits

1 1 1 10 0 0 0Startbit

Character bits Stopbits


63 Asynchronous Communication Interface63 Asynchronous Communication Interface

CS RS

0 X

Operation Register selected

X Nonedata bus in high-impedance1 0 WR Transmitter register1 1 WR Control register1 0 RD Receiver register1 1 RD Status register


63 Modes of Transfer63 Modes of TransferData transfer to and from IO devices may be handled in one of three possible modes

Programmed IOInterrupt-initiated IODirect memory access (DMA)


63 Programmed IO63 Programmed IOProgrammed IO operations are the result of IO instructions written in the computer programEach data item transfer is initiated by an instruction in the programTransferring data under program control requires constant monitoring of the IO by the CPUThe IO device does not have direct access to memory


63 Example of Programmed IO63 Example of Programmed IOThe steps of data transfer

IO device places data to the IO bus and enables the data valid lineThe interface accepts the data into its register and enables thedata accepted lineThe interface sets a bit of flag ldquoFrdquoThe CPU reads the data from the interface according to flag ldquoFrdquo

CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted


63 Flowchart for CPU Reads Data From IO63 Flowchart for CPU Reads Data From IO

Read data register

Check flag bit

Flag

Read status register

Transfer data to memory

OperationComplete

Continuewith

program

= 0

= 1

yes

no


63 Interrupt63 Interrupt--Initiated IOInitiated IOInstead of constantly monitoring the flag the CPU is informed to receive data when an interrupt signal happens from the interface

The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required IO transfer


63 Priority Interrupt63 Priority InterruptThe system establishes a priority over the various sources to determine which condition is to be serviced first when two or more requests arrive simultaneously Two methods of priority interrupt

Software priority-interruptA polling procedure

Hardware priority-interruptDaisy-chaining priorityParallel priority-interrupt


63 Daisy63 Daisy--Chain Priority InterruptChain Priority Interrupt

Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request

Interrupt acknowledge

Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus


63 Parallel Priority63 Parallel Priority--InterruptInterrupt


63 DMA63 DMARemoving the CPU from the path and letting the IO devices manage the memory directlyDuring DMA transfer the CPU is idle and has no control of the memory busesTwo signals are used to facilitate the DMA transfer

Bus request a signal from DMA controllerBus grant the CPU informs the DMA that the buses are in high-impedance state

BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write

High-impedance(disable)when BG isenable


63 DMA Controller63 DMA ControllerBlock diagram of DMA controller

Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant

InterruptDMA request

DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device


63 Initialization of DMA63 Initialization of DMAThe CPU initializes the DMA by sending the following information through the data bus

Starting address of the memory blockWord countMode of transferA start signal to do DMA transfer


63 DMA Transfer63 DMA Transfer

CPU

WR Address DataRD

Random-accessmemory (RAM)

WR Address DataRD

Direct memoryaccess (DMA)

controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control

Write controlData bus

Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request


ReferencesReferenceshttpwwwxilinxcombvdocsappnotesxapp611pdfhttpwwwarmcomproductssolutionsAMBA_SpechtmlMano M Morris ldquoComputer system architecturerdquo Prentice Hall1993


OutlineOutline61 The Implementation of IDCT on FPGA61 The Implementation of IDCT on FPGA62 AMBA IO Interface Design62 AMBA IO Interface Design63 IO Interface Design63 IO Interface Design















m = 0 n = 0

c(p)c(q)

4middotcos

Π(2m+1)p

2Mmiddotcos

Π(2n+1)q

2N(EQ 1)




2 middot M

K = radic1N

for row = 0radic2

K = N for row ne 0


2 middot N

K = radic1M


for col ne 0M

(EQ 2)

(EQ 3)






C =

Ct =









X =


C =




























Interface



DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge













Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request

















m = 0 n = 0

c(p)c(q)

4middotcos

Π(2m+1)p

2Mmiddotcos

Π(2n+1)q

2N(EQ 1)




2 middot M

K = radic1N

for row = 0radic2

K = N for row ne 0


2 middot N

K = radic1M


for col ne 0M

(EQ 2)

(EQ 3)






C =

Ct =









X =


C =




























Interface



DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge













Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request






2 middot M

K = radic1N

for row = 0radic2

K = N for row ne 0


2 middot N

K = radic1M


for col ne 0M

(EQ 2)

(EQ 3)






C =

Ct =









X =


C =




























Interface



DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge













Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request







C =

Ct =









X =


C =




























Interface



DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge













Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request










X =


C =




























Interface



DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge













Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





























Interface



DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

AHB to APB Bridge

Or

ASB to APB Bridge













Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request















Feature












DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request














DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB

AHB to APB Bridge


High performance

Pipelined operation

Burst transfers


Split transactions


Low power


Simple interface

















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request


















HADDR

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA

HRDATA

HADDR

HADDR

HADDR

HWDATA

HWDATA

HWDATA

HRDATA

HRDATA

HRDATA





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





Clock

HIGH to LOW

Transient

HIGHLOW to HIGH

Bus stable


Bus change





A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request






A

Control

Data(A)

Data(A)


HCLK

HADDR [310]

Control

HWDATA [310]

HREADY

HRDATA [310]

master slave master



A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





A

ControlControl

HCLK

HADDR [310]


HREADY

HRDATA [310]Data(A)





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





Data(A)

Data(B)

Data(C)

A B

Control(A)

Control(B)

Control(A)

C

Control(C)

Data(B)

Data(C)

HADDR [310]

HWDATA [310]

Control

HCLK

HREADY

HRDATA [310]








HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request









HCLK

HADDR [310]

HWDATA [310]

HREADY

HRDATA [310]

HTRANS [10]

HBURST [20]

T1 T2 T3 T4 T5 T 6 T7 T 8

Data(0x24)

Data(0x28)

Data(0x 2C)

Data(0x2C)

Data(0x24)

Data(0x20)

Data(0x20)

0x20 0x24 0x280x24

NONSEQ BUSY SEQ SEQ

0x2C

SEQ

Data(0x28)

INCR







NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request









NONSEQ SEQ SEQ SEQ

0x30 0x340x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x34)

Data(0x30)

Data(0x3C)

Data(0x38)

WRAP4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





NONSEQ SEQ SEQ SEQ

0x40 0x440x3C0x38

Data(0x38)

Data(0x3C)

Data(0x40)

Data(0x44)

Data(0x44)

Data(0x40)

Data(0x3C)

Data(0x38)

INCR4


HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HRDATA [310]

HWDATA [31 0]

HREADY


HWRITE

T1 T2 T3 T4 T5 T6 T 7



HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





HCLK

HTRANS [10]

HADDR [31 0]

HBURST [20]

HWDATA [31 0]

HREADY

HRDATA [31 0]


HWRITE

T 1 T2 T3 T4 T5 T 6 T 7 T 8


0 x20 0x22 0x5C 0 x60 0x64

INCR INCR



Data(0x20)

Data(0x22)

Data(0x60)

Data(0x64)

Data(0x5C)

Data(0x20)

Data(0x 22)

Data(0x5 C)

Data(0x60)

Data(0x64)
















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request


















HCLK

HTRANS [10]

HADDR [310]

HWDATA [310]

HREADY

HRESP [10]


A A + 4 A

Data(A)

RETRY RETRY OKAY

Two -cycle response

T1 T2 T3 T4 T5




DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request






DecoderMaster

1

Master

2

Master

3

HGRANT_M1

HGRANT_M2

HGRANT_M3

HADDR_M1[310]

HADDR_M2[310]

HADDR_M3[310]

HADDR to all slaves

HMASTER[30]

Address and Control

multiplex

Arbiter



AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





AHBslave

Split-capableslave

HSELx

HADDR[310]

HWRITE

HTRANS[10]

HSIZE[20]

HBURST[20]

HWDATA[310]

HRESETnHCLK

HMASTER[30]

HMASTLOCK

Select

Addressand

control

Data

ResetClock

HRDATA[310]

HREADY

HRESP[10]

HSPLITx[150]

Data

Transferresponse



AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





AHBmaster

HGRANTx

HREADY

HRESP[10]

HRESETn

HCLK

HRDATA[310]

Arbitergrant

Transferresponse

Reset

Clock

Data

HBUSREQx

HLOCKx

HTRANS[10]

HADDR[310]

HWRITE

HSIZE[20]

HBURST[20]

HPROT[30]

HWDATA[310]

Arbiter

Transfer type

Addressandcontrol

Data



AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





AHBarbiter

HBUSREQx1HLOCKx1

HBUSREQx2

HLOCKx2

HBUSREQx3

HLOCKx3

HADDR[310]

HSPLITx[150]

HTRANS[10]

HBURST[20]

HRESP[10]

HRESETnHCLK

Arbiterrequests

and locks

Addressand control

ResetClock

HGRANTx1HGRANTx2

HGRANTx3

HMASTER[30]

HMASTLOCK

Arbitergrants

HREADY








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request










DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBASB

ASB to APB Bridge


High performance

Pipelined operation

Burst transfers



Low power


Simple interface












BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request













BCLK

BTRAN[10]

BA[310]BWRITE

BSIZE[10]

BPROT[10]

DSELxBWAIT

BERROR

BLAST

BD[310]Read










BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request












BCLK

BTRAN[10]

BA[310]

BWAIT

BERROR

BLAST

BD[310]



ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





ASBslave

DSELSelect

BA[310]

BWRITE

BSIZE[10]

BnRES

BCLK

Addressand

control

Reset

Clock

BWAIT

BERROR

BLAST

BD[310]

Transferresponse

Data



ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





ASBmaster

AGNT

BWAIT

BERROR

BLAST

BnRES

BCLK

Arbitergrant

Transferresponse

Reset

Clock

AREQ

BLOK

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BD[310]

Arbiter

Transfer type

Addressandcontrol

Data



ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





ASBdecoder

BTRAN[10]

BA[310]

BWRITE

BSIZE[10]

BPROT[10]

BnRES

BCLK

Transfer type

Addressand

control

Reset

Clock

DSEL1DSEL1

hellip

DSELn

BWAIT

BERROR

BLAST

Selects

Transferresponse



ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





ASBarbiter

AREQx1AREQx2

AREQx3

BWAIT

BLOK

BnRES

BCLK

Arbiterrequests

Wait

Lock

Reset

Clock

AGNTx1AGNTx2

AGNTx3Arbitergrants








DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request










DMA busmaster

BRIDGE

UART Timer

Keypad PIO

APBAHB or ASB

APB Bridge


Low power


Simple interface










No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request











No transfer

Transfer

TransferNo transfer



APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





APBslave

PRDATA

PSEL1PSEL2

PSELn

PENABLE

PADDR

PWRITE

Selects

Strobe

Addressandcontrol

Write data


PRDATARead data

PRESETn

PCLKReset

Clock



APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





APBslave

PRDATA Read data

PADDR

PWDATA

PSELx

PENABLE

PWRITE

PRESETn

PCLK

Select

Strobe

Addressand

control

Reset

Clock

Write data



T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





T1 T2 T3 T4 T5 T1 T2 T3 T4 T5 T6

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

HADDR

HREADY

HWRITE

HRDATA

PRDATA

PWRITE

PSEL

PADDR

PENABLE

Addr 1

Data 1

Data 1

Addr 1

Addr 1

Data 1

Addr 1

Data 1

Write transfers
















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request


















Keyboardand

displayterminal


Magnetictape






















Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request
























Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram




Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request






Sourceunit

Destinationunit

Data bus

Strobe

(a) Block diagram

Data

Strobe

Valid data

(b) Timing diagram








Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request










Sourceunit

Destinationunit

Data bus

Data accepted

(a) Block diagram

Data valid

Data bus Valid data

(b) Timing diagram

Data valid

Data accepted





(initial state)





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





Sourceunit

Destinationunit

Data bus

Ready for data

(a) Block diagram

Data valid

Ready for bus

Valid data

(b) Timing diagram

Data valid

Data bus



(initial state)




Source unit

Destination unit




1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request






1 1 1 10 0 0 0Startbit




CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





CS RS

0 X











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request











CPU

InterfaceData bus

Address bus

IO read

IO write

Data register

Statusregister

F

F = Flag bit

IOdevice

IO bus

Data valid

Data accepted



Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





Read data register

Check flag bit

Flag



OperationComplete

Continuewith

program

= 0

= 1

yes

no










Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request












Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

CPU

INTACK

INT

VAD1 VAD2 VAD3

To nextdevice

Interrupt request


Processor data bus






BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request








BR

BG

CPU

DBUS

ABUS

RD

WR

Bus request

Bus grant

Address bus

Data bus

Read

Write




Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request





Data busbuffer

Controllogic

DS

RS

RD

WR

BR

BG

Interrupt

DMA select

Register select

Data bus

Inte

rnal

bus

Address bus

Read

Write

Bus request

Bus grant


DMA Acknowledge

Address busbuffer

Address register

Word count register

Control register

to IO device






CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request








CPU

WR Address DataRD


WR Address DataRD


controller

WR Address DataRD

DS

RS

BR

BG

Interrupt

Addressselect

Read control


Address bus

Interrupt

BG

BR

IOPeripheral

device

DMA acknowledge

DMA request



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