characteristics and designs of sigec hbts...

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1 RTO RTCVD poly RTCVD nitride Clean Module Load lock ellipso- meter foup Department of Electrical Engineering, National Taiwan University Characteristics and Desig Characteristics and Desig ns of SiGeC HBTs ns of SiGeC HBTs 含含含含含含含含含含含含含含含 含含含含含含 含含含含含含含含含含含含含含含 含含含含含含 含含含含 : 含含含 含含 含含含 : 含含含 含含含含含含含含含含含含 含含含含含含含含 含含含含

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Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計      指導教授 : 劉致為 博士    研究生  : 劉寅昕 台灣大學電子工程學研究所 中華民國九十三年一月十七日. Outline. 1. Introduction. 1. Introduction 2. Carbon in SiGe alloy 3. Characteristics of SiGe(C) HBTs 4. Simulation of SiGe(C) HBT on SOI - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

1

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Characteristics and Designs of SiGeCharacteristics and Designs of SiGeC HBTsC HBTs

含碳摻雜矽鍺異質接面雙載子電晶含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計體的特性與設計

     指導教授 : 劉致為 博士    研究生  : 劉寅昕 台灣大學電子工程學研究所

中華民國九十三年一月十七日

Page 2: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

2

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

OutlineOutline

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

Page 3: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

3

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

1. Introduction1. Introduction

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

Page 4: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

4

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

MotivationMotivation

Market and Technology drive in wireless and optical communication !

9.616,88016,79013,23010,5509,10010,6907,235Optical Semiconductors

4.422,99921,50017,20714,89814,00018,56615,107Discrete

7.451,81346,06236,79631,63828,67736,30126,575Analog-Monolithic

11.019,03716,53312,32210,3028,94611,2797,074Total Other Logic

-9.51,9092,0412,1552,2252,2503,1452,608Standard Logic

-35.81372354026338781,2581,289Custom ICs

9.636,12731,41724,48720,85718,41122,82617,752ASICs

8.257,21150,22639,36634m01730,48538,50828,723Digital Logic

13.812,0009,9007,3005,6304,7206,2954,690Digital Signal Processors

8.923,40021,00014,60012,20011,40015,27112,570Microperipherals

10.325,00023,00018,00015,00013,60015,30411,747Microcontrollers

4.940,00037,00031,00027,00025,10031,50228,531Microprocessors

8.0100,40090,90070,90059,83054,82068,37257,538Microcomponents

0.09001,000951841800899723Other Memory

1.315,15117,36516,14711,82210,86414,1997,070Nonvolatile Memory

-1.17,0008,5007,5005,8005,3517,3944,558SRAM

-2.727,49746,57231,91018,63014,04931,54623,149DRAM

-1.350,54873,43756,50837,09331,06454,03835,500Memory

6.9272,353252,343202,097169,395154,097194,929147,529Total Semiconductors (Without DRAM)

166B(E)*142*B

5.8299,850298,915234,007188,025168,146226,475170,678Total Semiconductors

2000-20052005200420032002200120001999

CAGR(%)($M)

9.616,88016,79013,23010,5509,10010,6907,235Optical Semiconductors

4.422,99921,50017,20714,89814,00018,56615,107Discrete

7.451,81346,06236,79631,63828,67736,30126,575Analog-Monolithic

11.019,03716,53312,32210,3028,94611,2797,074Total Other Logic

-9.51,9092,0412,1552,2252,2503,1452,608Standard Logic

-35.81372354026338781,2581,289Custom ICs

9.636,12731,41724,48720,85718,41122,82617,752ASICs

8.257,21150,22639,36634m01730,48538,50828,723Digital Logic

13.812,0009,9007,3005,6304,7206,2954,690Digital Signal Processors

8.923,40021,00014,60012,20011,40015,27112,570Microperipherals

10.325,00023,00018,00015,00013,60015,30411,747Microcontrollers

4.940,00037,00031,00027,00025,10031,50228,531Microprocessors

8.0100,40090,90070,90059,83054,82068,37257,538Microcomponents

0.09001,000951841800899723Other Memory

1.315,15117,36516,14711,82210,86414,1997,070Nonvolatile Memory

-1.17,0008,5007,5005,8005,3517,3944,558SRAM

-2.727,49746,57231,91018,63014,04931,54623,149DRAM

-1.350,54873,43756,50837,09331,06454,03835,500Memory

6.9272,353252,343202,097169,395154,097194,929147,529Total Semiconductors (Without DRAM)

166B(E)*142*B

5.8299,850298,915234,007188,025168,146226,475170,678Total Semiconductors

2000-20052005200420032002200120001999

CAGR(%)($M)

Source: Gartner Dataquest September 2001

Optlcal Flber

Copper

Flxed Wlreless

Moblle Wlreless

OC-768

OC-192

OC-48

PON

IEEE 1394

IEEE 802.3

DSLCable modem

IEEE 802.16

IEEE 802.11a,b,g

IEEE 802.15

W1394Bluetooth

3G Mobile

2.5G Mobile

WAN

MAN

LAN

Mobile

40G

10G

1G

100M

10M 1MPAN

Optlcal Flber

Copper

Flxed Wlreless

Moblle Wlreless

OC-768

OC-192

OC-48

PON

IEEE 1394

IEEE 802.3

DSLCable modem

IEEE 802.16

IEEE 802.11a,b,g

IEEE 802.15

W1394Bluetooth

3G Mobile

2.5G Mobile

WAN

MAN

LAN

Mobile

40G

10G

1G

100M

10M 1MPAN

Page 5: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

5

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

SiGe advantagesSiGe advantages

High speed--- HBT structure replace III-V compound group and work as high-speed based devices

High linearity--- SiGe HBT has better linearity output than RF-CMOS

High breakdown--- SiGe HBT provides higher breakdown voltage than RF-CMOS, but lower than GaAs

Low cost--- high compatibility with Si VLSI technology, low cost with commercial productions

V: good O : fair X : poor

Ref: Jiann Yuan, SiGe, GaAs and InP HBTs, Wiley, 1999, P3.

VVXXXRF-CMOS

XXVVVGaAs HBT

OVOVVSiGe HBT

CostIntegrationBreakdownLinearityfT/fmax

VVXXXRF-CMOS

XXVVVGaAs HBT

OVOVSiGe HBT

CostIntegrationBreakdownLinearityfT/fmax

Page 6: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

6

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Technology roadmapTechnology roadmap

Source: Conexant 2000 Ref: N. Nakamura, ISSCC, 1998

Page 7: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

7

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RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

2. Carbon in SiGe alloy

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

Page 8: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

8

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RTCVDpoly

RTCVDnitride

CleanModule

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ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Pseudomorphic Growth and Film RelaxationPseudomorphic Growth and Film Relaxation

strained and relaxed SiGe on a Si substrate

misfit dislocation formed at the Si/ SiGe growth interface

unwanted !

Page 9: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

9

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RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

B diffusion in SiB diffusion in Si

B

I

Si Interstitial (I)

B

I

Boron interstitial (Si and B share site)

is highly mobile

I reacts with substitutionalBoron

B

I

Si Interstitial (I)

B

I

Boron interstitial (Si and B share site)

is highly mobile

B

I

Boron interstitial (Si and B share site)

is highly mobile

I reacts with substitutionalBoron

B diffusion is a major concern in electronic devices like: B out-diffusion in bipolar ; B penetration in MOSFET B diffusion enhanced in TED or OED, especially increased in thermal anneal

B out diffusion is mediated with Si interstitial: Bsubstitutional + I ==> Binterstitial

Boron substitutional (immobile)

Ref: A. Ural, et al., J. Appl. Phys., vol. 85, p. 6440, 1999.

Page 10: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

10

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RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Parasitic barrier induced by B out-diffusion Parasitic barrier induced by B out-diffusion

n- p+ n-

As-grown

Boron inside SiGe layer

Depth

Concentration

(a)

n- p+ n-

Annealed

Boron outside SiGe layerC

oncentration

Depth

SiGe

Activation anneal

(b)

SiGe

n- p+ n-

As-grown

Boron inside SiGe layer

Depth

Concentration

(a)

n- p+ n-

Annealed

Boron outside SiGe layerC

oncentration

Depth

SiGe

Activation anneal

(b)

SiGe

Ref: E. J. Prinz et al., IEEE Elec.Dev.Lett., vol. 12, p. 661, 1991.

0 500 1000 1500 2000 2500

1E18

1E19

1E20

as-grown

after anneal at 1000 0C for 10 seconds in N2

B c

once

ntra

tion

(cm

-3)

Depth (nm)

Observed by the degradations in collector saturation current and Early Voltage !

Source: process was executed in ERSO

Page 11: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

11

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

C diffusion in Si/SiGeC diffusion in Si/SiGe

Cs+ I CI

Cs: immobile substitutional carbon I : self-interstitial Si CI: mobile interstitial carbon

SiGeC epitaxial grown on Si by UHVCVD

Ge=25%, B=6E19 cm-3, C=~0.1%

SiGeC layer thickness=20 nm

Carbon precursor from C2H4

SIMS: Cs+ ion beam / 500 ev / incident angle 600

Source: process was executed in ERSO

0 500 1000 1500

1018

1019

1020

as-grown

after anneal at 1000 0C for 10 seconds in N2

C co

ncen

tratio

n (c

m-3

)

Depth (nm)

after anneal

as-grown

Substitutional-Interstitial exchange

Ref: H. Rucker et al., IEDM, P. 345, 1999.

Page 12: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

12

RTO

RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Effects of Carbon incorporation into SiGe alloy Effects of Carbon incorporation into SiGe alloy

Pros:

Substitutional C suppresses B out-diffusion Substitutional C improves thermal stability of SiGe alloy

Cons:

low solid solubility in Si (3-41017 cm-3 near the melting point) and Ge (1108~11010 cm-3)

SiC is the only thermally stable phase in Si No stable Ge-C phases are known above this solid solubility limit of Ge

=> a large of various meta-stable C states formation including X-Ci, Bs-Ci, and Cs-Ci to make negative electrical defects.

Page 13: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

13

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RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Substitutional C suppress B out-diffusionSubstitutional C suppress B out-diffusion

Substitutional C can suppress B out-diffusion through reducing Si interstitial concentrationby C out-diffusion from base

Ref: H. Rucker et al., IEDM, P. 345, 1999.

C concentration = 1E20 cm-3

Thermal budget=900 0C 2 hour

B concentrations in SIMS

Interstitials eliminated in C-rich regionVacancies enhance 8X in C-rich region

Si interstitial and vacancy simulations

Si substrateEpi

Si substrate

SiC epi

Cs+ I <=> Ci Cs <=> Ci + V CCDC >CIeqDI CCDC>CVeqDV

I: interstitial V: vacancy

Page 14: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

14

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RTCVDpoly

RTCVDnitride

CleanModule

Loadlock

ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

C precursors: C2H4 (ethylene), Planar structure and stable with its -bond

UHVCVD(ultra high vacuum chemical vapor deposition)

SiGe epitaxial growth conditions: Growth pressure: 1 mtorr Growth temperature: 550 C GeH4: 36 sccm (5% in He) B2H6: 50 sccm (5% in He) SiH4: 70 sccm (in He) C2H4: various (2% in He)

Advantages: Low cost Low risk in ESH Easy preparations

ExperimentsExperiments

Source: process was executed in ERSO

Page 15: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

15

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RTCVDpoly

RTCVDnitride

CleanModule

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ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

Si/SiGe(C)/Si MQWsSi/SiGe(C)/Si MQWs

MQW epitaxial grown

Source: process was executed in ERSO

404040404040Si1-xGexCy layer thickness (nm)

100756550250Si1-xGexCy, C2H4flow rate (sccm)

FEDCBALayer no

404040404040Si1-xGexCy layer thickness (nm)

100756550250Si1-xGexCy, C2H4flow rate (sccm)

FEDCBALayer no

Sample growth for SIMS and XRD measure Epitaxial grown by UHVCVD CR and 10:1 HF-last clean before growth Low growth temperature 550 0C Low growth pressure 1 mtorr Boron concentration (nominal): 1E19 cm-3

Germanium concentration (nominal): 20 % C=0, 25, 50, 60, 75, 100 sccm, respectively Carbon precursor from C2H4

Region (A) works as a control No apparent misfit / dislocation observed

Si seed layer 40 nm

Region (A) SiGe 40nm, B doped

Si 40 nm

Region (B) SiGeC 40nm C flow 25 sccm, B doped

Si 40 nm

Cap Si 10 nm

Si substrate

Mutli-quantum well Si / SiGeC / Si layer (3 X periods)

Region (F) SiGeC 40nm C flow 100 sccm, B doped

Si 40 nm

Page 16: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

16

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RTCVDnitride

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ellipso-meter

foup Department of Electrical Engineering, National Taiwan University

B in SiGeC B in SiGeC

0 10 20 30 40 50 60 70 80 90 1001.00E+019

2.00E+019

3.00E+019

4.00E+019

5.00E+019

6.00E+019

7.00E+019

B p

eak

conc

entra

tion

(cm

-3)

as-grown after anneal

100

200

300

400

500

FWH

M

C2H

4 flow (sccm)

as-grown after anneal

Source: process was executed in ERSO

SIMS: Cs+ ion beam / 500 ev / incident angle 600

Each peak corresponds the above SiGeC layer Apparent broaden profiles can been observed at low C concentration (<50 sccm) Ge fraction degrades due to high concentration C incorporation (>75 sccm)

100 200 300 400 500

2.0x1019

4.0x1019

6.0x1019

8.0x1019

1.0x1020

Depth from surface (nm)

Bor

on c

once

ntra

tion

(cm

-3)

B (as-grown)

B (after anneal at 1000 0C 10 seconds in N2)

0.00

0.05

0.10

0.15

0.20

0.25

Ge fraction

Ge

(F) (E) (D) (C) (B) (A)

Source: process was executed in ERSO

small amount of Cs can effective reduce diffusivity of B Optimal C2H4 flow rate ~ 75 sccm

Page 17: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

17

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foup Department of Electrical Engineering, National Taiwan University

C in SiGeC in SiGe

100 200 300 400 500

1x1020

2x1020

3x1020

C (as-grown)

C (after anneal at 1000 0C for 10 seconds in N2)

C c

once

ntra

tion

(cm

-3)

Depth from surface (nm)20 40 60 80 100

1x1020

2x1020

3x1020

4x1020

as grown after anneal

C2H

4 flow (sccm)

C p

eak

conc

entr

atio

n (c

m-3)

as grown after anneal

200

400

600

800

1000

FW

HM

Source: process was executed in ERSO

SIMS: Cs+ ion beam / 500 ev / incident angle 600 Each peak corresponds the above SiGeC layer Apparent broaden profiles can been observed C incorporation form complex cluster at high flow rate (>75 sccm) of C2H4

Cs + Ci => Cs-Ci cluster (immobile)Or silicon-carbide formation

(F)

(E)

(A)(B)

(C)

(D)

Ref: J. W. Strane, et al., J. Appl. Phys., vol.76, p. 3656, 1994.

Page 18: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

18

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Substitutional C from XRDSubstitutional C from XRD

-3000 -2500 -2000 -1500 -1000 -500 0 50010

0

101

102

103

104

105

106

(400) Si

(F) C2H

4 100 sccm

(E) C2H

4 75 sccm

(C) C2H

4 50 sccm

(B) C2H

4 25 sccm

(A) no C2H

4

X-r

ay in

tens

ity

(cps

)

arc-second Small amount of C2H4 progressively added in SiGe, a shift of 100 arcsec in the (400) x-ray diffraction peak at 75 sccm Decrease of lattice constant by Cs incorporation Lattice constant: aC=3.54 A , aSi=5.43 A, aGe=5.65 A Broadened and weak diffraction intensity at C2H4=100 sccm ref: C. W. Liu Ph.D. thesis, Princeton, 1994

C. W. Liu, et al., J. Appl. Phys. 80, 3043 (1996 )

20 40 60 80 1000.0

0.1

0.2

0.3

0.4

0.5

0.6

C f

ract

ion

(y%

)C2H4 flow rate (sccm)

subst. C from XRD

total C from SIMS

At C2H4 flow rate=75 sccm, Ctotal=0.2%, Cs=~0.08%. The ratio of substitutional/total~0.4 Higher C2H4 flow rate, substitutional C saturate

XRD of Si/SiGe(C)/Si SQW Substitutional/total C ratio

Source: process was executed in ERSO

Page 19: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

19

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Substitutional C improve thermal stabilitySubstitutional C improve thermal stability

Ref: process was executed in ERSO

Test structure using SiGeC

Epitaxial grown by UHVCVD Low growth temperature 550 C Low growth pressure 1 mtorr Boron concentration (SIMS): 6E19 cm-3

Germanium concentration (SIMS): 25 % C=0, 0.1% or 0.5% Carbon precursor from C2H4

Strain relaxation in SiGe layer with thermalannealImprove thermal stability of SiGe layer with small amount C incorporation

Si seed layer 40 nm

Si0.75-yGe0.25Cy 20 nm, [B = 6E19 cm-3; y = 0, 0.1% or 0.5 %]

Si 40 nm

Cap Si 10 nm

Si substrate

-3000 -2000 -1000 0 1000100

101

102

103

104

105

106

107

108

109

(ii)

(i)C =0% with 10000 C 10 sec annealingC =0% as grown

C =0.5% with 10000 C 10 sec annealingC =0.5% as grown

Theta (arc-second)

Inte

nsit

y (a

rb.u

nits

)

-3000 -2000 -1000 0 1000100

101

102

103

104

105

106

107

108

109

-3000 -2000 -1000 0 1000100

101

102

103

104

105

106

107

108

109

(ii)

(i)C =0% with 10000 C 10 sec annealingC =0% as grown

C =0.5% with 10000 C 10 sec annealingC =0.5% as grown

Theta (arc-second)

Inte

nsit

y (a

rb.u

nits

)

Source: process was executed in ERSO

Page 20: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Morphology roughnessMorphology roughness

AFM measurement of Sample ( with C doped 0.5%), RMS=1.66nm

0.0 0.1 0.2 0.3 0.4 0.5 0.60.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Si0.8Ge0.2Cx (before annealed)

Rrm

s(nm

)

Y(%)

AFM measurement of Sample ( with C doped 0.1%), RMS=0.27nm

Add Carbon into SiGe alloy => make morphology roughness Carbon concentration => roughness

Source: process was executed in ERSO

Page 21: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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PhotoluminescencePhotoluminescence

Source: Measurement was executed by T.-C. Chen, NTE EE

0.9 1.0 1.10.000

0.001

Energy (ev)

PL

Inte

nsity

(a.

u.)

SiGeC 15K PL

C(y=0.05%)

B(y=0.02%)A(no C)

NPTO

PL was measured by 488 nm Ar+ laser at 15K Power density=0.2 Wcm-2

Diameter of circular spot size~0.5 um No SiC precipitates Ge concentration=20 %

Significant attenuations of PL intensity observed at NP and TO peaks Decreasing PL intensity shows defect formations from extra interstitial C atoms

Si seed layer 40 nm

Si0.8-yGe0.2Cy 40 nm, [y = 0, 0.02 %, 0.05 %]

Si 40 nm

Cap Si 10 nm

Si substrate

Si/SiGe(C)/Si single quantum well

Page 22: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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3. Characteristics of SiGeC HBTs3. Characteristics of SiGeC HBTs

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

Page 23: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Why SiGe HBT ? Why SiGe HBT ?

Source: Nortel, R. Hadaway, Ethernet Standards, March 1999

SiGe used in bipolar devices, high speed: SiGe epitaxy > Si implant

Source: D.L. Harame, IBM, 2002

Narrow bandgap and quasi-drift e-fieldby graded profile SiGe base

Page 24: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Integration challenge of HBT with CMOS

--- Need low thermal cycle of HBT module

--- Without degradation of core CMOS performance Higher thermal stability cycle in HBT module

--- SiGeC HBT module provide a higher thermal cycle

--- Suppression of boron out-diffusion effect Improvement of HBT devices

--- Higher early voltage

--- Better low-frequency noise

Why SiGeC HBT ?Why SiGeC HBT ?

Source: D.L. Harame, IBM, 2002

SiGeC HBT offer higher speed Integrity with Si/SiGe BiCMOS

Ref: J. D. Cressler and G. Niu, SiGe HBTs, Artech House, 2002

TED / OEDoutdiffusion

base

Boron porfile

wilder base

limit fT

smaller Nb

RB increase

degradation !

TED / OEDoutdiffusion

base

Boron porfile

wilder base

limit fT

smaller Nb

RB increase

degradation !

2002 IBM 350 GHz

Page 25: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Integration process for SiGe/SiGeC HBTsIntegration process for SiGe/SiGeC HBTs

Schematic of Single-Poly Non-Self-Aligned structure

P-type substrate N+ buried layer N / P well formation

LOCOS

Si epitaxy

Ultra Base engineering

Emitter engineeringIsolation engineering

Contact & metallization

UHVCVDSi/SiGe/SiGeC

RTCVD

AE = 0.6 * 10.8 um2

Thermal budget: ~ 1000 0C several tens secondsfor dielectric dense and emitter driving

SIC implantation

Page 26: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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SIMSSIMS

0.3 0.4 0.5 0.6

1E17

1E18

1E19

1E20

1E21

AsBGePOSb

0.00

0.05

0.10

0.15

0.20

Ge

mole fraction

Depth (um)

Dop

ant

conc

SiGe HBT SIMS profile

Ge

As

B

CO

P

Sb

Ge

0.3 0.4 0.5 0.6

1E17

1E18

1E19

1E20

1E21

AsBGePOSb

0.00

0.05

0.10

0.15

0.20

Ge

mole fraction

Depth (um)

Dop

ant

conc

SiGe HBT SIMS profile

Ge

0.3 0.4 0.5 0.6

1E17

1E18

1E19

1E20

1E21

AsBGePOSb

0.00

0.05

0.10

0.15

0.20

Ge

mole fraction

Depth (um)

Dop

ant

conc

SiGe HBT SIMS profile

Ge

As

B

CO

P

Sb

Ge

0.3 0.4 0.5 0.6

1E17

1E18

1E19

1E20

1E21

Depth

Dop

ant

conc

.

AsBPSbCO

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

SiGeC HBT SIMS profile

Ge

mole fraction

Ge

As Ge

C

P

O

Sb

0.3 0.4 0.5 0.6

1E17

1E18

1E19

1E20

1E21

Depth

Dop

ant

conc

.

AsBPSbCO

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

SiGeC HBT SIMS profile

Ge

mole fraction

Ge

0.3 0.4 0.5 0.6

1E17

1E18

1E19

1E20

1E21

Depth

Dop

ant

conc

.

AsBPSbCO

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

SiGeC HBT SIMS profile

Ge

mole fraction

Ge

As Ge

C

P

O

Sb

Cs+ ion beam / energy=500 ev / incident angle=600

Intended-doped Carbon concentration~0.2 % Other dopant distributions are also exhibited

Source: process was executed in ERSO

(um)

Page 27: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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C suppress B and enhance AsC suppress B and enhance As

0.30 0.35 0.40 0.45 0.50

1E17

1E18

1E19

1E20

1E21

As &

B c

on

ce

ntr

atio

n (

cm

-3)

As no C B no C As with C B with C

Depth (um)

Source: process was executed in ERSO

Carbon suppress B out diffusion, but enhance As diffusion As diffusion is mediated by Si vacancy As and B distributions extracted from total SIMS profile

As

B

Ref: H. Rucker et al., IEDM, P. 345, 1999.

Page 28: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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XRDXRD

-3000 -2500 -2000 -1500 -1000 -500 0 5001

10

100

1000

10000

X-r

ay in

tens

ity

arc-second

SiGe HBT SiGeC HBT

Control wafers used to observe strain compensation as carbon incorporated into SiGe layer Substitutional carbon is estimated to: 0.08 % Interstitial carbon is estimated to: 0.12 %

Source: process was executed in ERSO

Page 29: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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DC characteristicsDC characteristics

0.2 0.4 0.6 0.8 1.0

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Ib of SiGe HBT Ic of SiGe HBT Ib of SiGeC HBT Ic of SiGeC HBT

Ib,Ic

(A)

VBE

(V)0.0 0.5 1.0 1.5 2.0

0

100n

200n

300n

400n

500n

600n

700n

800nV

BE=0.65V ; I

B=50 nA

SiGe HBT SiGeC HBT

I C(A

)

VCE

(V)

When VBE=0.65V, IC(SiGeC)/IC(SiGe)=1.6 => improve Ic ~60% Collector current doesn’t degrade => substitutional C effective suppress boron out-diffusion in base Non-ideal current in SiGeC HBT indicates carrier recombination caused by interstitial-related defects

Output curveGummel plot

Ref: process was executed in ERSO

2

2 )](/[

)/exp(i

in

BEC n

xnDpdx

kTqVqJ

IC

IB

Page 30: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Flicker noiseFlicker noise

10 100 1k

1E-20

1E-19

1E-18

1E-17I

B=100 uA

Si0.8

Ge0.2

base

Si0.798

Ge0.2

C0.002

base

SIB(A

2 /Hz)

Frequency(Hz) SIB: spectral density of base current noise SIB: SiGeC larger ~8X than SiGe at IB=100 uA SIB = K × IB

2 / f (K: the factor related to the defect density; f: the operation frequency) interstitial carbon affect carrier transport making larger 1/f noise

Ref: process was executed in ERSO

Page 31: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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RF characteristicsRF characteristics

0 5m 10m 15m 20m 25m 30m 35m 40m 45m

5

10

15

20

25

30

35

40

45

50

55

60

65

70

75

800 5x10-3 1x10-2 2x10-2 2x10-2 3x10-2 3x10-2 4x10-2 4x10-2 5x10-2

Jc(A/cm2)

f T,f m

ax(

GH

z)

Ic(A)

fT SiGe HBT

fmax

fT SiGeC HBT

fmax

cbbccbebebcmT

rrCCCgf

1

2

1

bbc

T

RC

ff

8max

fT peak (SiGeC HBT)=75GHz > fT peak(SiGe HBT)=72 GHz C suppress B out-diffusion providing shorter base,b decrease

fmax peak (SiGeC HBT)=26GHz > fmax peak (SiGe HBT)=19GHz Slightly higher fT and low Cbc make largerfmax in SiGeC HBT

Source: process was executed in ERSO

B=WB2/2DB C=Xdbc/2Vsat

fT

fmax

Page 32: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Early VoltageEarly Voltage

BW

ieBnB

B

dBC

BiezBBnBA xSiGenxD

xN

C

WSiGenWqDSiGeV

0 2

2

),()(

)(,)(

Early Voltage (SiGeC HBT)>Early Voltage (SiGe HBT) improve >2X Low Cbc is contributed to high Early Voltage, nieb almost same

Source: process was executed in ERSO

0.0 0.5 1.0 1.5 2.0

0.0

2.0x10-4

4.0x10-4

6.0x10-4

8.0x10-4

1.0x10-3

1.2x10-3

1.4x10-3 Forced IB

I C(A

)

VCE

(V)

SiGeC HBT

SiGe HBT

Page 33: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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4. Simulation of SiGe(C) HBTs on SOI4. Simulation of SiGe(C) HBTs on SOI

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

Page 34: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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MotivationMotivation

Page 35: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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TargetTarget

The SiThe Si11--xxGeGexx HBT fabricated on SOI:HBT fabricated on SOI:

Advantages :higher breakdownhigher fmaxcompeting fT

low noise

Disadvantage :costself-heating (thermal resistance)

Ref: IBM, VLSI 2002

The SiThe Si11--xxGeGexx HBT fabricated on SOI:HBT fabricated on SOI:

Advantages :higher breakdownhigher fmaxcompeting fT

low noise

Disadvantage :costself-heating (thermal resistance)

Ref: IBM, VLSI 2002Ref: IBM, VLSI 2002

The key parameters of SOI design for SiSi11--xxGeGexx HBT

Si collector thickness

Buried oxide thickness

Lateral distance

Tsi=0.15 um is the optimal choice with WE =0.1um (ref : BCTM 2002 / IBM)

The key parameters of SOI design for SiSi11--xxGeGexx HBT

Si collector thickness

Buried oxide thickness

Lateral distance

Tsi=0.15 um is the optimal choice with WE =0.1um (ref : BCTM 2002 / IBM)

Page 36: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Simulation structuresSimulation structures

Source: EE times, IBM, 2002

Bulk: Tsi=0.3 um N+ buried layer Lcol=0.15 um

BOX=0.06~0.20 um

Lcol=0.1~0.2 um

SOI: Tsi=0.15um no N+ buried layer Lcol=0.1~0.2 um

Fixed conditionsFixed conditionsEmitter: AEmitter: AEE=0.14*10 um, N=0.14*10 um, NEE=1E20 cm=1E20 cm-3-3

Base: TBase: TBB=0.07 um, N=0.07 um, NBB=2E18 cm=2E18 cm-3-3, SiGe(C) epi, SiGe(C) epi

Collector: Nc=1E17 cmCollector: Nc=1E17 cm-3-3

VBE=0.4~1.0VVCB=2V

Simulation by commercial simulator: ISE

FD collector

Page 37: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Depletion region of bulk HBT with VCE=2Vno obvious depletion region

Depletion region of SOI HBT with VCE=2Valmost all collector depleted

E-field and depletion regionE-field and depletion region

-0.4 1.2 1.4 1.6 1.8

0.0

8.0x104

1.6x105

2.4x105

Bulk SOI (BOX0.15)

E-f

ield

(V/c

m)

positon

lateralvertical

E-field (vertical ) comparison of SOI HBT devices with different BOX

E-field (vertical and lateral ) comparison of bulk HBT and SOI HBT

collector reach-through

collectorreach-throughE B C BOX

E B Creach-through

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.20.0

2.0x104

4.0x104

6.0x104

8.0x104

1.0x105

1.2x105

1.4x105

1.6x105

1.8x105

2.0x105

BOX0.08 BOX0.13 BOX0.15

E-f

ield

(V

/cm

)

position

Page 38: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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0.0 0.2 0.4 0.6 0.8 1.0

0

10

20

30

40

BulkIc1 BulkIc2 SOIIc1 SOIIc2

I c(u

A/u

m)

VCE

(V)

IB=0.1 uA/um

IB=0.01 uA/um

Buried oxide thickness effectsBuried oxide thickness effects

Output characteristics of SOI and bulk HBTs

VA(SOI, BOX=0.15 um): 155 V ; VA(Bulk): 98 V at IB=0.1 uA/um Lateral-extended depletion region in SOI HBT, effective depletion region increase, so CdBC decrease Lcol=0.15 um

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Bulk BOX0.08 BOX0.1 BOX0.15 BOX0.20.0

10.0f

20.0f

30.0f

C

dB

C (f

F/u

m)

CdBC0

100

200

300

400

500

600E

arly

Vo

ltag

e (V

) Va

Early Voltage v.s CEarly Voltage v.s CdBCdBC

Early Voltage of SOI and bulk HBTs v.s CdBC

As BOX thickness decreases, CdBC slightly decreases. All smaller than bulk As BOX thickness decreases, Early Voltage increases due to smaller CdBC

All larger than bulk

BW

ieBnB

B

dBC

BiezBBnBA xSiGenxD

xN

C

WSiGenWqDSiGeV

0 2

2

),()(

)(,)(

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fmax v.s Cfmax v.s CCSCS

0 0.08 0.1 0.15 0.2

240

245

250

255

260

265

270

Oxide thickness (m)

f max(

GH

z)

900.0a

1.0f

1.1f

1.2f

1.3f

1.4f

Ccs (f

F/m

)

As BOX thickness decreases, CCS increases, smaller than bulk As BOX thickness decreases, fmax inversely increases, larger than bulk Lcol=0.15 um

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Bulk BOX0.08 BOX0.10 BOX0.15 BOX0.20

240

245

250

255

260

265

270

f max(

GH

z) fmax

34

35

36

37

38

39

40

41

fT (GH

z)

fT

RF characteristicsRF characteristics

SOI HBT has lower fT than bulk HBT SOI HBT has higher fmax than bulk HBT at BOX thickness > 0.1 um As BOX thickness increases, fT decrease due to long BC depletion region As BOX thickness increases, fmax increases due to low CCS

Lcol=0.15 um

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BVBVCEOCEO v.s E-field v.s E-field

0.10 0.15 0.20

3.90

3.95

4.00

4.05

4.10

Oxide thickness Tox

(m)

BV C

EO (

V)

0.10

0.11

0.12

0.13

0.14

0.15

Ele

ctr

ic F

ield

(M

V/c

m)

As BOX thickness decreases, peak e-field in B-C interface increases, due to extra voltage drop across thick BOX As BOX thickness decreases, BVCEO inversely increases, due to smaller e-field Lcol=0.15 um

Page 43: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Lateral designLateral design

E-field distributions between different Lcol (lateral-cut direction) in SOI HBT

n+ reach-throughn- collector

BOX thickness is fixed at 0.15 um, different Lcol from 0.1 ~ 0.2 um,Collector doping is 1E17 cm-3

As Lcol distance increases, depletion region extends, e-field distributes and lower peak value

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RF characteristicsRF characteristics

0.10 0.15 0.200

50

100

150

200

250

300

Lcol

(m)

f T/f m

ax(G

Hz) f

T

fmax

RF characteristics of SOI HBT devices with different Lcol distances

As Lcol distance increases, fT decreases due to carrier transferring across longer depletion region As Lcol distance increases, fmax decreases due to smaller fT

Page 45: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Trade-off of fTrade-off of fTT and BV and BVCEOCEO

Lcol0.10um Lcol0.15um Lcol0.20um

3.75

4.00

4.25

BV

CE

O (

V)

BVCEO

15

20

25

30

35

40

45fT (G

Hz)

fT

Trade-off of fT and BVCEO in SOI HBT devices with different Lcol distances

As fT*BVCEO as a figure of merit, as Lcol distance increases, fT decreases, but BVCEO increases, a trade-off exists Optimal Lcol design depends the circuit application and user need

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5. Summary and further works5. Summary and further works

1. Introduction

2. Carbon in SiGe alloy

3. Characteristics of SiGe(C) HBTs

4. Simulation of SiGe(C) HBT on SOI

5. Summary and Future Works

Page 47: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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SummarySummary

smallerlarger(>2X)Early Voltage(V)

smallerlarger(35%)fmaxpeak(GHz)

smallerlarger(5%)fTpeak(GHz)

smallerlarger(10X)Flicker noise(A2/Hz)@Ib=100 uA,frequency=100Hz

smallerlargerNoise Figure minimum(dB)@frequency=1.2GHz,Vc = 1.5 V

quitequiteCurrent gain@Vbe=0.65V

smallerlargerBase current(A)

smallerlargerCollector current(A)

SiGeHBT

SiGeCHBT

Performance characteristics

smallerlarger(>2X)Early Voltage(V)

smallerlarger(35%)fmaxpeak(GHz)

smallerlarger(5%)fTpeak(GHz)

smallerlarger(10X)Flicker noise(A2/Hz)@Ib=100 uA,frequency=100Hz

smallerlargerNoise Figure minimum(dB)@frequency=1.2GHz,Vc = 1.5 V

quitequiteCurrent gain@Vbe=0.65V

smallerlargerBase current(A)

smallerlargerCollector current(A)

SiGeHBT

SiGeCHBT

Performance characteristicsPropertiesEffect of C incorporation

in SiGe alloy

defects Interstitial-induced as shown by PL

roughness increase

Ge concentration

high C flow will inhibit Ge incorporation

dopant diffusion

C enhance As, suppress B diffusion

thermal stability

improve

strainadd 1% C will compensate 8~10%Ge strain

critical thickness

increase critical thickness of SiGe

Page 48: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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ConclusionConclusion

1. The substitutional/total C ratio provided by our system is < 0.42. Narrow process window for using C2H4 to satisfy the demand of reducing CI and suppressing B out-diffusion is restricted at total C concentration < 0.2 % in our system3. If the precise control of epitaxy process is executed , C2H4 is able to utilize as C precursor

4. SOI devices can have better Early voltage than bulk due to low CdBC

5. As the BOX thickness increases => fT => mainly caused by e-field re-distribution => fmax=> because of low Ccs => BVCEO => due to smaller BC E-field A trade-off design exists between the different BOX thickness6. As the distance of C-sinker increases => fT => mainly caused by depletion region extending => BVCEO => due to lower lateral E-field A trade-off design exists between the different Lcol

Page 49: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Further worksFurther works

1. Use other C-doped sources in SiGe HBT, like methyl-silane (SiH3CH3)

2. Simulation using 3D structure of HBT on SOI with thermal resistance

3. Plan to wafer-start of HBT fabricated on SOI

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ERSO group in ITRI:P. S. Chen, Z. Pei, L. S. Lai (now tsmc), C. S. Liang, Y. T. Tseng, M. H. Lee, Y. M. Shiu, S. C. Lu, and M.-J. Tsai, for epitaxy growth, measurements and advisements.

NTU group:T. C. Chen (PL and CV measurements)S. T. Chang (simulation)W. C. Hua (noise)

AcknowledgmentsAcknowledgments

Page 51: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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Capacitance-VoltageCapacitance-Voltage

-5 -4 -3 -2 -1 0 1 2 3 40.0

200.0p

400.0p

600.0p

800.0p

1.0n

Si0.8

Ge0.2

HBT Si

0.798Ge

0.2C

0.002 HBT

Si0.8

Ge0.2

HBT Si

0.798Ge

0.2C

0.002 HBT

Capa

ctian

ce (F

)Voltage (V) Bias exerted=-4V~3V

Operation frequency=50Hz~0.2MHz Al metal gate is used

Si seed layer 10 nm

Si0.8-yGe0.2Cy 90 nm, [B = 1E19 cm-3; y = 0 or 0.2 %]

Cap Si 9 nm

P-Si substrate

Source: Measurement was executed by T.-C. Chen, NTE EE

SiGeC has higher normalization ratio Cinversion/Coxid

e at both frequencies extra-induced minority carriers response with exerted bias

Oxide 8.8 nm

Al metal 300 nm

Al metal 300 nm

MOS capacitor using SiGeC layer

10 KHz

100 KHz

Page 52: Characteristics and Designs of SiGeC HBTs 含碳摻雜矽鍺異質接面雙載子電晶體的特性與設計         指導教授  :  劉致為 博士

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substitutional C improve critical thickness constraint

1

10

100

1000

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

SiGe

1%carbon

2%carbon

3%carbon

Ge concentration

criti

cal t

hick

ness

(nm

)

Ge = 20 %, SiGe layer critical thickness ~ 13 nm SiGeC (sub C = 0.1 %) layer critical thickness ~ 20 nm

Formula: …….people

C can suppress B out-diffusion Because the lattice constant of carbon crystallized in the diamond structure is considerably smaller than that of silicon (aC is 0.354 nm),carbon incorporation in SiGe to form SiGeC is also of great interest for its potential to compensate the compressive stain in Sie layers grown commensurate to Si

8.1010440 y

Substitutional C calculations:by an assumation of 1 % C compensating 10.8 % GeVegard’s law:

y = fraction of Carbon = separation of (400) peaks between SiGe and Si in the unit of arc secondIn (E), the Ge content of SiGe:C is the same as the SiGe control sample, substitutional C = 0.09 0.01 %

Vengard law

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P-SUB.

SOI Buried Oxide

oxide oxide collector

F.O.deep n+

F.O. F.O.

reach-through

emitter

base

P-SUB.

P+B/L P+B/LN+B/L

P-Well P-WellN-Well

F.O.

DEEP N+

F.O. F.O.

1. No use buried oxide => 0.1um thin BOX2. 0.5um collector thickness => 0.1~0.14 um collector thickness3. No use high doping buried layer4. Later reach through

Bulk HBT

SOI HBT

Emitter

Base

Collector

Traditional NPN BJTTraditional NPN BJT

Structure ComparisonStructure Comparison

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N+ polyN+ poly

P baseP base

N-collectorN-collector

BoxBox

P- substrateP- substrate

reach-throughreach-through---- electron flow direction---- electric field direction

Bulk HBT owns 1D electric field (vertical)

N+ polyN+ poly

P baseP base

N-collectorN-collector

N+ SC reach-through N+ SC reach-through

sinkersinker

P- substrateP- substrate

SOI HBT owns 2D electric field (vertical+lateral)

Operation ConceptOperation Concept