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    Synthetic presentation of the major clusters in nanoelectronics

    Charles Collet, GAEL,October 07

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    Introduction

    Nanoelectronics can be considered as anexception in nanosciences :its indeed a nanotechnology (producing

    devices at the nanoscale), but its top downapproach, as a continuation of themicroelectronics roadmap, doesnt constitue

    -yet- a breakthrough as it doesnt bringchanges in physical properties.Its a nanotechnology but not a

    nanoscience, yet.

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    Comparing & positioning nanoelectronics clustersis a hard task due to heterogeneity of their activities.

    Indeed the current split of their business models(continuation of miniaturization, diversification onnew functionalities) makes it for example

    irrelevant to compare nb of employees (front vsback end) or investment.

    The only criterion that is however common togrowing clusters seems to be the excellence of their applied researchWe can thus present the repartition of the

    industry, major clusters in their position on thevalue chain.

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    g o a wor : a nee or nnova on versus a push for production relocation.

    2 axis in Business Model Change:Digital versus Physical Value Added(design vs production)Modular versus Integral

    architecture: miniaturized &standardized chips (More Moore) vsminiaturized & specific chips (More

    than Moore)

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    Physical valuecreation

    Modularproduction

    architecture

    Integralproduction

    architecture

    1

    2

    3

    4

    Digital value creation

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    1) digital & modular: value added is ondesign, & the architecture design is modular

    IP providers designing the processcores

    or ASICs(like ARM, MIPS)IP providers conceive generic chips coresaround which other firms (fabless or IDMs)

    will design some extended architectures for specific applications.coordination costs are low (IP providers justhave to send the digital architecture to other fabless or IDMs), & the IP can beunderstood by any manufacturer

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    2) physical & modular : mass production of generic chips (high volume/low unit value)

    the pure play foundries Business Model for

    chips & memories (TSMC, UMC, Qimonda, etc)VA is indeed physical (chip production that involves a high capital intensity), & the production

    model is modular, as these firms produce chips that will be sold to different customers & integrate a large range of products.R&D costs are heavily supported bymanufacturers as their competitive advantagerelies on the ability to keep on with miniaturization(More Moore)

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    3) digital & integral : Value on design, specificarchitectures & new functionalities. the Fabless Business Model (Broadcom,Qualcomm, IBM, Freescale, etc)

    value added is even more digital & knowledge-intensive, as these design companies conceivespecific chips for specific clients, which will beproduced by foundries.chips are specific & cant be applied to different

    products, thus taking place in an integralproduction strategy.

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    4) physical & specific : complex systems producedby IDMs & integrative clusters: the Integrated Business Model (TI, Samsung,STM, Grenoble, Dresde, Albany clusters, )etc

    VA is on design & also on production of thesespecific chips like NEMS (Nano ElectronicsMechanical Systems), as the complexity of the chipmakes production as knowledge intensive as thedesign.

    labs-on-chip, Embedded System on Chip, SecuredSolutions, NEMS, etc.

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    Valeur plutt physique

    Production de

    pucesstandards / modulaires(VA faible, production de

    masse)

    Production

    de pucesspcialisesou intgres(VA forte, prod deligneslimites)

    1-IP providers quiconoivent un cur de

    process: ARM, MIPS, etc

    2- producteurs de masse

    More Moore :Dresde(Qimonda,),&Taiwan(fonderies),fabricants de mmoires :Epida, Powerchip, etc.

    3- designers fabless :Qualcomm, Broadcom, etc, &

    orientation prise par NXP, FSLpour les gnrations < 45nm

    4- entreprises intgratrices :ST, TI, Atmel, etc& clusters produisant dessolutions intgres, labos surpuce, etc: Grenoble,Eindhoven Alban .

    Valeur plutt digitale

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    Physique,architectur

    esmodulaires

    Digitale,architectur

    esmodulaire

    s &spcialis

    Digitale &architectur

    esspcialis

    es

    Physique,architectu

    resmodulaire

    s &spcialis

    Digitale &architecturesspcialises

    Type of Value

    Added

    Production demasse

    Rechercheinternationale &intgration

    multidisciplinaire

    Rechercheinternation

    ale &design

    diversifi

    Recherchelocale &

    production de

    masse(processe

    urs,mmoires

    )

    Recherche localeforte &intgrationmultidisciplin

    aire(Minatec)

    Business Model&

    Positionnin

    g

    76 00050 00025 00020 00020 000Nombre

    demploys

    ITRICNSEIMECCNTCEA LtiResearch Lab

    TSMC, UMC

    IBM, Samsung,AMD,

    Micron,Infineon,

    Chartered.

    NXPInfineon, AMDSTMAnchor tenant

    firm

    TaiwanAlbanyLouvain/EindhovenDresdeGrenoble

    Structure of the clusters around a double anchor

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    epar on o pro uc oncapacities ownership,nanoelectronics.

    distribution de la proprit des capacits deproduction de semiconducteurs en 2005 (%)

    0

    10

    20

    30

    40

    50

    USA japon europe taiwan Core duSud

    Chine

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    epar on o pro uc oncapabilities locations,nanoelectronics.

    Distribution gographique des fabs mondiales en2005.

    0%

    5%

    10%

    15%

    20%

    25%

    30%

    USA japon europe taiwan Core duSud

    Chine

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    Evolution of the nationalproduction produced inshore

    Evolution de la part de production nationaleeffectue sur son sol, 1998 - 2003.

    0%

    20%

    40%

    60%

    80%

    100%

    USA Europe Japon AsiePacifique

    MoyenneMonde

    1998

    2003

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    Number of dedicated researchers &

    operational workers in nanoelectronicsclusters, ex of Grenoble.

    0 50000 100000 150000

    HsinchuTsukuba

    Seoul

    Silicon ValleyOregonArizona

    New-YorkM assachusset t s

    TexasPek inShanghai

    GrenobleCataniaDresde

    0 5000 10000 15000

    Production

    Chercheurs

    Taille comptitive

    Le ple Grenoblois a une taillecomptitive en matire derecherche

    il lui faut encore acqurirla dimension de productionindustrielle adquate

    0 50000 100000 150000

    HsinchuTsukuba

    Seoul

    Silicon ValleyOregonArizona

    New-YorkM assachusset t s

    TexasPek inShanghai

    GrenobleCataniaDresde

    0 5000 10000 15000

    Production

    Chercheurs

    Taille comptitive

    Le ple Grenoblois a une taillecomptitive en matire derecherche

    il lui faut encore acqurirla dimension de productionindustrielle adquate

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    Tsukuba

    Hsinchu

    Japan

    Taiwan

    USA

    OregonCalifornia

    Texas

    New-York

    Seoul

    Korea

    Fab 300 mm Fabs

    Labo Public

    Chinea

    Shanghai

    Beijing

    Portland

    AustinDallas

    AlbanyEast Fishkill

    Competitiors of

    European clusters

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    From Academia to Market, ex of Grenoble

    Academic Research Advanced Research Manufacturing

    Process IntegrationModule Development

    Advanced Modules

    Dan Noble CenterDan Noble Center

    IMECIMEC

    LETILETI

    45nm Device Architecture

    45nm Device Architecture

    StressorTechnologies

    StressorTechnologies

    Gate Stack (high-k, M-

    Gate)

    Gate Stack (high-k, M-

    Gate)

    BEOL Materials& Integration

    BEOL Materials& Integration

    ImmersionLithography

    ImmersionLithography

    Materialsand Advanced

    Modules

    Materialsand

    AdvancedModules

    Crolles Narrowed Options

    45nm DesignRules Inputs

    45nm DesignRules Inputs

    E-beam DirectWrite Litho

    E-beam DirectWrite Litho

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    Conclusion: Successful clusters in high cost regions rely ondifferentiating themselves from their competition

    Europe may be loosing the cost war for low value-adding industries,but not the same for high tech & capital-intensive sectors such as

    nanoelectronics, as in this high tech industry the cost of equipment(clean rooms, lithography tools) & workforce (engineers) becamesimilar globally.however the differences between territories mainly rely on statesubsidies & tax regimes. Taiwan or China wouldnt have been able tobuild their competitive foundries without a public support being higher than the one granted in Europe & US together for the same timeperiod (about 4 billion $ between 2002-2007). That shows that with asame amount of subsidies & a same tax rate Europeannanoelectronics clusters like Dresden or Grenoble would surely be ascompetitive as Taiwan, all things remaining equal.This statement goes against the common acceptation saying that if their ability to make a good becomes ubiquitous, the competitiveadvantage of European clusters should shift from the production lineto management strategies, innovation, R&D, or marketing (Andersen,2005).But what we do agree with, is that without the same national or environmental conditions the challenge for western clusters is toreinvent themselves in ways that keep a level of local employment, asit will be hard for them to compete on production with places that have

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    Most strategies have looked to the universities as

    the source of new and distinguishing innovations, &most cluster analyses include rates of patents andpublications as evidence of innovation.But for these indicators Taiwanese cluster again doas good as European ones. The difference betweenAsian & western clusters is the fact that they havebeen built on a longer tradition & already developedsecondary competencies, like biotechnology inGrenoble, Dresden or Albany-Boston, which now

    can really become a source of advantage in theconvergence enabled at the nanoscale.Creative Centers, Richard Florida writes, tend tobe the economic winners of our age. These creativecenters have the attributesphysical, diversity, andexperiencesto attract what he defines as thecreative class. & its up to this creative class now todesign complex & integrated systems so as to swiftthe value from low cost to high performance, &

    diversify on new functionalities so as to create newvalue.

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    Bridgingdisciplines &competencies to

    develop new & highvalue addingsolutions

    Designing betterchips

    Integrative firms &clusters

    Miniaturizedarchitecture, lowconsumption &/or

    high performance

    Designing chipsbetter

    Fabless / Designfirms

    low cost thanks tomass production,investment inminiaturization

    Making chipssmaller & cheaper

    Foundries

    AdvantageGoalActor

    Table: competitive advantage of the micro/nanoelectronics actors, CharlesCollet, 2007.

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    Those Golden Days of Scaling:Pricetrend Baseline CMOS

    0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.10

    123

    45

    67

    89

    101112

    13

    1415

    Min = 2/3 * Average

    Source : Gartner/Dataquest 2004

    Q298Q299Q200Q201Q202Q203Q403Q204

    a v e r a g e

    S i w a f e r

    P r i c e

    ( $ / c m

    2 )

    Node (um)LTPS : 1-1.5 $ /cm2

    Price Trend (time) at fixed Node

    @ 0.12 um 200 mm > 300mm +7%

    @ 0.5 um : 150 mm > 200mm 20%

    Golden Decades of Scaling 2 Functionality + Clockspeed @ equal $/cm2

    2ML, 13 masks

    7LM, 36 masks

    Source: [2005] Carel van der Poel, Philips Research