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DC Motor Driver ASSP MCU

HT45F4630

Revision: V1.00 Date: i 1 01i 1 01

Rev. 1.00 i 1 01 Rev. 1.00 3 i 1 01

HT45F4630DC Motor Driver ASSP MCU


Table of Contents

Features ............................................................................................................ 6CPU Featues ......................................................................................................................... Peihea Featues ................................................................................................................. 7

General Description ......................................................................................... 8Block Diagram .................................................................................................. 8Pin Assignment ................................................................................................ 9Pin Description ................................................................................................ 9Absolute Maximum Ratings ...........................................................................11D.C. Characteristics ....................................................................................... 12A.C. Characteristics ....................................................................................... 13LXT Characteristics ....................................................................................... 14LVD & LVR Electrical Characteristics .......................................................... 14Bandgap Reference Voltage Characteristics – VBG .................................... 15A/D Converter Electrical Characteristics ..................................................... 15Operational Amplifier Electrical Characteristics ........................................ 16Level Shifter Electrical Characteristics ....................................................... 17Voltage Detector Electrical Characteristics ................................................ 18Power-on Reset Characteristics ................................................................... 18System Architecture ...................................................................................... 19

Cocking and Pieining ......................................................................................................... 19Pogam Counte ................................................................................................................... 0Stack ..................................................................................................................................... 0ithmetic and Logic Unit – LU ........................................................................................... 1

Flash Program Memory ................................................................................. 22Stuctue ................................................................................................................................ Secia Vectos ..................................................................................................................... Look-u Tabe ........................................................................................................................ Tabe Pogam Exame ........................................................................................................ 3In Cicuit Pogamming – ICP ............................................................................................... 4On Chi Debug Suot – OCDS ......................................................................................... 5

Data Memory .................................................................................................. 26Stuctue ................................................................................................................................ Genea Puose Data Memoy ............................................................................................ Secia Puose Data Memoy .............................................................................................

Special Function Register Description ........................................................ 28Indiect ddessing Registe – IR0 IR1 ........................................................................... 8Memoy Pointes – MP0 MP1 ............................................................................................. 8Bank Pointe – BP ................................................................................................................ 9

Rev. 1.00 i 1 01 Rev. 1.00 3 i 1 01



ccumuato – CC ............................................................................................................... 9Pogam Counte Low Registe – PCL ................................................................................. 9Look-u Tabe Registes – TBLP TBHP TBLH .................................................................... 9Status Registe – STTUS .................................................................................................... 30

EEPROM Data memory ................................................................................. 32EEPROM Data Memoy Stuctue ........................................................................................ 3EEPROM Registes .............................................................................................................. 3Reading Data fom the EEPROM ......................................................................................... 34Witing Data to the EEPROM ................................................................................................ 34Wite Potection ..................................................................................................................... 34EEPROM Inteut ................................................................................................................ 34Pogamming Consideations ................................................................................................ 35

Oscillators ...................................................................................................... 36Osciato Oveview ............................................................................................................... 3System Clock Configurations ................................................................................................ 3Extena Cysta/Ceamic Osciato – HXT .......................................................................... 37Intena RC Osciato – HIRC ............................................................................................... 38Extena 3.78kHz Cysta Osciato – LXT ........................................................................ 39Intena 3kHz Osciato – LIRC ........................................................................................... 40

Operating Modes and System Clocks ......................................................... 40System Cocks ...................................................................................................................... 40System Oeation Modes ...................................................................................................... 41Conto Registe .................................................................................................................... 43Fast Wake-u ........................................................................................................................ 44Oeating Mode Switching .................................................................................................... 45Standby Cuent Consideations .......................................................................................... 49Wake-u ................................................................................................................................ 49Pogamming Consideations ................................................................................................ 50

Watchdog Timer ............................................................................................. 51Watchdog Time Cock Souce .............................................................................................. 51Watchdog Time Conto Registe ......................................................................................... 51Watchdog Time Oeation ................................................................................................... 5

Reset and Initialisation .................................................................................. 54Reset Functions .................................................................................................................... 54Reset Initia Conditions ......................................................................................................... 5

Input/Output Ports ......................................................................................... 60Pu-high Resistos ................................................................................................................ 0Pot Wake-u ..................................................................................................................... 1I/O Pot Conto Registes ..................................................................................................... 1Pin-shaed Functions ............................................................................................................ I/O Pin Stuctues .................................................................................................................. 5Pogamming Consideations ............................................................................................... 5

Rev. 1.00 4 i 1 01 Rev. 1.00 5 i 1 01



Timer Modules – TM ...................................................................................... 66Intoduction ........................................................................................................................... TM Oeation ........................................................................................................................ TM Cock Souce ................................................................................................................... TM Inteuts ......................................................................................................................... TM Extena Pins ................................................................................................................... 7TM Inut/Outut Pin Seection .............................................................................................. 7Pogamming Consideations ................................................................................................ 8

Periodic Type TM – PTM ................................................................................ 69Peiodic TM Oeation .......................................................................................................... 9Peiodic Tye TM Registe Descition ................................................................................ 70Peiodic Tye TM Oeating Modes ..................................................................................... 75

Analog to Digital Converter ......................................................................... 84/D Convete Oveview ....................................................................................................... 84/D Convete Registe Descition ...................................................................................... 85/D Convete Oeation ....................................................................................................... 87/D Convete Refeence Votage ......................................................................................... 88/D Convete Inut Signas .................................................................................................. 88Convesion Rate and Timing Diagam .................................................................................. 88Summay of /D Convesion Stes ....................................................................................... 89Pogamming Consideations ................................................................................................ 90/D Convesion Function ...................................................................................................... 90/D Convesion Pogamming Exames .............................................................................. 91

Operational Amplifier – OPA ......................................................................... 93Operational Amplifier Operation ............................................................................................ 93Operational Amplifier Registers ............................................................................................. 93Operational Amplifier Input Offset Calibration ....................................................................... 94

Over Current Protection – OCP .................................................................... 95Ove Cuent Potection Oeation ....................................................................................... 95Ove Cuent Potection Registes ........................................................................................ 95Inut Votage Range .............................................................................................................. 98Offset Caibation .................................................................................................................. 98

High Voltage Driver ...................................................................................... 100High Votage Dive Conto ................................................................................................. 101High Votage Dive Combination ........................................................................................ 107High Votage Powe Suy Detection .................................................................................110

I2C Interface ...................................................................................................111IC Inteface Oeation .........................................................................................................111IC Registes ........................................................................................................................11IC Bus Communication ......................................................................................................11IC Bus Stat Signa .............................................................................................................117Save ddess ......................................................................................................................117IC Bus Read/Wite Signa ..................................................................................................117IC Bus Save ddess cknowedge Signa .......................................................................117

Rev. 1.00 4 i 1 01 Rev. 1.00 5 i 1 01



IC Bus Data and cknowedge Signa ...............................................................................118IC Time-out Conto .............................................................................................................119

Interrupts ...................................................................................................... 121Inteut Registes ............................................................................................................... 11Inteut Oeation .............................................................................................................. 17Extena Inteut ................................................................................................................. 19Ove Cuent Potection Inteut ........................................................................................ 19Operational Amplifier Inteut ............................................................................................ 19/D Convete Inteut ....................................................................................................... 130Thema Potection Inteut ............................................................................................... 130Muti-function Inteut ........................................................................................................ 130LVD Inteut ....................................................................................................................... 130IC Inteut ......................................................................................................................... 131EEPROM Inteut .............................................................................................................. 131Time Base Inteuts ........................................................................................................... 131PTM Inteuts .................................................................................................................... 13Inteut Wake-u Function ................................................................................................. 133Pogamming Consideations .............................................................................................. 133

Low Voltage Detector – LVD ....................................................................... 134LVD Registe ....................................................................................................................... 134LVD Oeation ..................................................................................................................... 135

Configuration Options ................................................................................. 136Application Circuits ..................................................................................... 137Instruction Set .............................................................................................. 138

Intoduction ......................................................................................................................... 138Instuction Timing ................................................................................................................ 138Moving and Tansfeing Data ............................................................................................. 138ithmetic Oeations .......................................................................................................... 138Logica and Rotate Oeation ............................................................................................. 139Banches and Conto Tansfe ........................................................................................... 139Bit Oeations ..................................................................................................................... 139Tabe Read Oeations ....................................................................................................... 139Othe Oeations ................................................................................................................. 139

Instruction Set Summary ............................................................................ 140Tabe Conventions ............................................................................................................... 140

Instruction Definition ................................................................................... 142Package Information ................................................................................... 151

4-in SSOP (150mi) Outine Dimensions ......................................................................... 15

Rev. 1.00 i 1 01 Rev. 1.00 7 i 1 01



Features

CPU Features• Operatingvoltage

♦ VDD=2.2V~5.5V♦ VCC1=3V~12V

• Upto0.25μsinstructioncyclewith16MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillatortypes:♦ ExternalHighSpeedCrystal–HXT♦ InternalHighSpeedRC–HIRC♦ External32.768kHzCrystal–LXT♦ Internal32kHzRC–LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Fullyintegratedinternal8MHz/12MHz/16MHzoscillatorrequiresnoexternalcomponents

• Allinstructionsexecutedinoneortwoinstructioncycles

• Tablereadinstructions

• 63powerfulinstructions

• 6-levelsubroutinenesting

• Bitmanipulationinstruction

Rev. 1.00 i 1 01 Rev. 1.00 7 i 1 01



Peripheral Features• FlashProgramMemory:2K×16

• RAMDataMemory:128×8

• EEPROMMemory:512×8

• WatchdogTimerfunction

• 18bidirectionalI/Olines

• Dualpin-sharedexternalinterrupts

• MultipleTimerModulesfortimemeasurement,inputcapture,comparematchoutputorPWMoutputorsinglepulseoutputfunction

• I2CInterfaceModule

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• 7-channel12-bitresolutionA/Dconverter

• OperationalAmplifier

• Highvoltagedrivercontrolandhighvoltagedrivercombination

• Lowvoltageresetfunction

• Lowvoltagedetectfunction

• OverCurrentProtectionfunction

• Highvoltagepowersupplydetection

• PWMoutputwithHXTfrequency

• Flashprogrammemorycanbere-programmedupto100,000times

• Flashprogrammemorydataretention>10years

• EEPROMdatamemorycanbere-programmedupto1,000,000times

• EEPROMdatamemorydataretention>10years

• Packagetype:24-pinSSOP

Rev. 1.00 8 i 1 01 Rev. 1.00 9 i 1 01



General DescriptionThedeviceisaFlashMemorytype8-bithighperformanceRISCarchitecturemicrocontrollerwithintegratedfunctionsforDCmotordrivingapplications.Offeringusers theconvenienceofFlashMemorymulti-programmingfeatures, thisdevicealso includesawide rangeof functionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaofEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analogfeatures includeamulti-channel12-bitA/Dconverterandanoperationalamplifier.Withregard to internal timers, thedevice includesmultipleandextremely flexibleTimerModulesprovidingfunctionsfortiming,pulsegenerationandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Afullchoiceofvariousexternalandinternallowandhighspeedoscillatorfunctionsisprovidedincludinga fully integrated systemoscillatorwhich requiresnoexternal components for itsimplementation.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesusers theability tooptimisemicrocontrolleroperationandminimisepowerconsumption.CommunicationwiththeoutsideworldiscateredforbyincludingafullyintegratedI2Cinterface,thispopularinterfacewhichprovidesdesignerswithameansofeasycommunicationwithexternalperipheralhardware.AlsotheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsandexternalinterruptsalongwithmanyotherfeaturesfurtherenhancedevicefunctionalityandflexibilityforwiderangeofapplicationpossibilities.

Thisdevicecontainsahighvoltagedrivercontrolcircuitandahighvoltagedrivercombinationcircuitaswellashighvoltagepowersupplydetectionandovercurrentprotectionfunctionswhichcanbeusedindifferentmotordriverapplications.

Block Diagram

8-bitRISCMCUCoe

FashPogam Memoy

Fash/EEPROMPogamming Cicuity

RMData

Memoy

LowVotageReset

IntenaHIRC/LIRCOsciatos

InteutContoe

ResetCicuit

Extena HXT/LXT

Osciatos

1-bit /DConvete

OP

OCP

I/O

EEPROM

IC

LowVotageDetect

ContoCicuit

LeveShift

High Votage Dive

Watchdog Time

TimeBase

10-bit PTM×

1-bit PTM×

HXT PWM

Rev. 1.00 8 i 1 01 Rev. 1.00 9 i 1 01



Pin Assignment

43101918171151413

134578910111

OCPI0/PD7OCPI0/PD

N7/P7DCREF/OCP0REF/N/P

HPO0/PTP1/OP0OUT/P5PTP0/INT0/N4/P4

PTCK3/HPO0/PTP1/N3/P3PTP1I/HPO0/PTP1/N1/P1

OP0INN/PBOP0INP/PB5PDH0/OUT0

VSS1

PB7/OCPO0VDD/VDDPB1/PTCK1/XTPB/XT1VSS/VSSPB0/PTCK0/PTPI/PTP/INT1P/PTCK/OCDSCK/ICPCK/SCLP0/PTP0I/OCDSD/ICPD/SDPB3/OSC1/PTP3/PTP3IPB4/OSCPDH1/OUT1VCC1

HT45F4630/HT45V463024SSOP-A

Note:1.Ifthesamepin-sharedpinhasmultipleoutputsormultipleinputs,thedesiredpin-sharedfunctionisdeterminedusingsoftwarecontrolbits.

2.TheOCDSDAandOCDSCKpinsaresuppliedfor theOCDSdedicatedpinsandassuchonlyavailablefortheHT45V4630devicewhichistheOCDSEVchipfortheHT45F4630device.

Pin DescriptionPin Name Function OPT I/T O/T Descriptions

P0/PTP0I/OCDSD/ICPD/SD

P0PPUPWUPPS0

ST CMOS Genea uose I/O. Registe enabed u-u and wake-u.

PTP0I PPS0SSCTL ST — PTM0 catue inut

OCDSD — ST CMOS OCDS addess/data fo EV chi ony.ICPD — ST CMOS ICP addess/dataSD PPS0 ST NMOS IC data ine

P1/PTP1I/HPO0/PTP1/N1

P1PPUPWUPPS0


PTP1I PPS0 ST — PTM1 catue inut

HPO0 PPS0SSCTL — CMOS HXT PWM outut

PTP1 PPS0 — CMOS PTM1 oututN1 PPS0 N — /D Convete inut channe 1

P/PTCK/OCDSCK/ICPCK/SCL

PPPUPWUPPS0


PTCK PPS0 ST — PTM cock inutOCDSCK — ST — OCDS cock fo EV chi ony.

ICPCK — ST CMOS ICP cockSCL PPS0 ST NMOS IC cock ine

Rev. 1.00 10 i 1 01 Rev. 1.00 11 i 1 01



Pin Name Function OPT I/T O/T Descriptions

P3/PTCK3/HPO0/PTP1/N3

P3PPUPWUPPS0


PTCK3 PPS0 ST — PTM3 cock inut


PTP1 PPS0 — CMOS PTM1 oututN3 PPS0 N — /D Convete inut channe 3

P4/PTP0/INT0/N4

P4PPUPWUPPS1


PTP0 PPS1 — CMOS PTM0 outut

INT0 PPS1INTEG ST — Extena Inteut 0 inut

N4 PPS1 N — /D Convete inut channe 4

P5/HPO0/PTP1/OP0OUT

P5PPUPWUPPS1



PTP1 PPS1 — CMOS PTM1 oututOP0OUT PPS1 — N Operational amplifier output

P/DCREF/OCP0REF/N

PPPUPWUPPS1


DCREF PPS1 N — /D Convete efeence votage inutOCP0REF PPS1 N — OCP0 efeence votage inut

N PPS1 N — /D Convete inut channe

P7/N7P7

PPUPWUPPS1


N7 PPS1 N — /D Convete inut channe 7

PB0/PTCK0/PTPI/PTP/INT1

PB0 PBPUPBDPS ST CMOS Genea uose I/O. Registe enabed u-u.

PTCK0 PBDPS ST — PTM0 cock inutPTPI PBDPS ST — PTM catue inutPTP PBDPS — CMOS PTM outut

INT1 PBDPSINTEG ST — Extena Inteut 1 inut

PB1/PTCK1/XT

PB1 PBPU ST CMOS Genea uose I/O. Registe enabed u-u.

PTCK1 PTM1C0PTM1C1 ST — PTM1 cock inut

XT CO — LXT LXT in

PB/XT1PB PBPU ST CMOS Genea uose I/O. Registe enabed u-u.XT1 CO LXT — LXT in

PB3/OSC1/PTP3/PTP3I

PB3 PBPUPBDPS ST CMOS Genea uose I/O. Registe enabed u-u.

OSC1 CO HXT — HXT inPTP3 PBDPS — CMOS PTM3 oututPTP3I PBDPS ST — PTM3 catue inut

PB4/OSCPB4 PBPU ST CMOS Genea uose I/O. Registe enabed u-u.

OSC CO — HXT HXT in

Rev. 1.00 10 i 1 01 Rev. 1.00 11 i 1 01



Pin Name Function OPT I/T O/T Descriptions

PB5/OP0INPPB5 PBPU ST CMOS Genea uose I/O. Registe enabed u-u.

OP0INP PBDPS N — Operational amplifier positive input

PB/OP0INNPB PBPU ST CMOS Genea uose I/O. Registe enabed u-u.

OP0INN PBDPS N — Operational amplifier negative input

PB7/OCPO0PB7 PBPU

PBDPS ST CMOS Genea uose I/O. Registe enabed u-u.

OCPO0 PBDPS — N OCP operational amplifier output

PD/OCPI0PD PDPU


OCPI0 PBDPSSSCTL N — OCP extena inut

PD7/OCPI0PD7 PDPU


OCPI0 PBDPSSSCTL N — OCP extena inut

PDH0/OUT0PDH0 — ST CMOS High Votage Dive I/OOUT0 — — N High Votage Dive Combination 0 outut

PDH1/OUT1PDH1 — ST CMOS High Votage Dive I/OOUT1 — — N High Votage Dive Combination 1 outut

VCC1 VCC1 — PWR — High Votage owe suy

VDD/VDDVDD — PWR — MCU ositive owe suy

VDD — PWR — naog ositive owe suyVSS1 VSS1 — PWR — High Votage gound

VSS/VSSVSS — PWR — Gound

VSS — PWR — naog gound

Legend:I/T:Inputtype; O/T:Outputtype; OPT:Optionalbyconfigurationoption(CO)orregisteroption; PWR:Power; ST:SchmittTriggerinput; CMOS:CMOSoutput; NMOS:NMOSoutput; AN:Analogsignal; CO:Configurationoption; HXT:Highfrequencycrystaloscillator; LXT:Lowfrequencycrystaloscillator.

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW

Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder "AbsoluteMaximumRatings"maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

Rev. 1.00 1 i 1 01 Rev. 1.00 13 i 1 01



D.C. CharacteristicsTa= -40°C~85°C, unless otherwise specified

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD

Oeating Votage(HXT HIRC) —

fSYS=8MHz . — 5.5

VfSYS=1MHz .7 — 5.5fSYS=1MHz 4.5 — 5.5

Oeating Votage (LXT) fSYS=fLXT=3.78kHz . — 5.5

IDD Oeating Cuent

3V No oad DC off WDT enabefSYS=fH=8MHz fS=fSUB=fLIRC

— 1. .0

m

5V — .8 4.53V No oad DC off WDT enabe

fSYS=fH=1MHz fS=fSUB=fLIRC

— 1.8 3.05V — 4.0 .0

5V No oad DC off WDT enabefSYS=fH=1MHz fS=fSUB=fLIRC

— 4.5 7.0

ISTB

Standby Cuent(IDLE0 Mode)

3V No oad MCU Powe Down DC off WDT enabe fSYS=1MHz off fS=fSUB=fLIRC

— 1.3 3.0μA

5V — . 5.0

Standby Cuent(IDLE1 Mode)

3V No oad MCU Powe Down DC off WDT enabe fSYS=fH=1MHz on fS=fSUB=fLIRC

— 0. 1.0m

5V — 1. .0

VILInut Low Votage fo I/O Pots — — 0 — 0.3VDD V

VIHInut High Votage fo I/O Pots — — 0.7VDD — VDD V

IOL Sink Cuent fo I/O Pots3V

VOL=0.1VDD1 45 —

m5V 3 5 —

IOH Souce Cuent fo I/O Pots3V

VOH=0.9VDD-5 -10 —

m5V -7 -15 —

RPHPu-high Resistance fo I/O Pots 5V — 10 30 50 kΩ

TPRTThema Potection temeatue

3VPDHn (n=0~1) no oad

135 155 175°C

5V 50 70 90

Rev. 1.00 1 i 1 01 Rev. 1.00 13 i 1 01



A.C. CharacteristicsTa= -40°C~85°C, unless otherwise specified



fSYS System Cock 4.5V~5.5V — 3 — 1000 kHz

fHIRCHigh Seed Intena RC Osciato (HIRC) —

Ta= -40°C~85°C -1% 8 +4%

MHz

Ta= -0°C~85°C -9% 8 +4%Ta=5°C -% 8 +%Ta= -40°C~85°C -1% 1 +4%Ta= -0°C~85°C -9% 1 +4%Ta=5°C -% 1 +%Ta= -40°C~85°C -1% 1 +4%Ta= -0°C~85°C -9% 1 +4%Ta=5°C -% 1 +%

fHXTHigh Seed Extena Cysta Osciato (HXT)

3V~5.5V — 0.4 — 4

MHz4.5V~5.5V — 0.4 — 84.5V~5.5V — 0.4 — 14.5V~5.5V — 0.4 — 1

tRSTD

System Reset Deay Time(Powe On Reset) — — 5 50 100 ms

System Reset Deay Time(ny Reset excet Powe On Reset)

.V~5.5V — 8.3 1.7 33.3 ms

tSST

System Stat-u Time Peiod(Wake-u fom Powe Down Mode and fSYS Off)

— fSYS=fLXT 104 — — tLXT

— fSYS=fHXT ~ fHXT / 4 18 — — tHXT

— fSYS=fHIRC ~ fHIRC / 4 1 — — tHIRC

— fSYS=fLIRC — — tLIRC

System Stat-u Time Peiod(Slow Mode ↔ Normal Mode, o fH=fHIRC ↔ fHXT o fSUB=fLIRC ↔ fLXT)

— fHXT off → on (HTO=1) 104 — — tHXT

— fHIRC off → on (HTO=1) 1 — — tHIRC

— fLXT off → on (LTO=1) 104 — — tLXT

System Stat-u Time Peiod(Wake-u fom Powe Down Mode and fSYS On)

— fSYS=fH~fH/4 fH=fHXT o fHIRC

— — tH

— fSYS=fLXT o fLIRC — — tSUB

System Stat-u Time Peiod(WDT Time-out Hadwae Cod Reset)

— — 0 — — tH

tEERD EEPROM Read Time — — — 45 90 μstEEWR EEPROM Wite Time — — — 4 ms

Rev. 1.00 14 i 1 01 Rev. 1.00 15 i 1 01



LXT CharacteristicsTa= -40°C~85°C, unless otherwise specified



VDD LXT Oeating Votage — fSYS=fLXT=3.78kHz . — 5.5 V

fLXTLow Seed Extena Cysta Osciato (LXT) .V~5.5V fSYS=fLXT=3.78kHz — 378 — Hz

ILXTdditiona Cuent fo LXT Enabe

3VLXTSP=0 — —

μLXTSP=1 — — 3

5VLXTSP=0 — — LXTSP=1 — — 3

tSTRT LXT Stat U Time3V — — — 1000

ms5V — — — 1000

Duty Cyce Duty Cyce — — 40 — 0 %RNEG Negative Resistance (Note) .V — 3×ESR — — Ω

Note:C1,C2andRPareexternalcomponents.C1=C2=10pF.RP=10MΩ.CL=7pF,ESR=30kΩ.

LVD & LVR Electrical CharacteristicsTa= -40°C~85°C, unless otherwise specified



VLVR Low Votage Reset Votage —

LVR enabe votage seect .1V

-5%

.1

+5% VLVR enabe votage seect .55V .55

LVR enabe votage seect 3.15V 3.15

LVR enabe votage seect 3.8V 3.8

VLVDLow Votage Detection Votage —

LVD enabe votage seect .0V

-5%

.0

+5% V

LVD enabe votage seect .V .

LVD enabe votage seect .4V .4

LVD enabe votage seect .7V .7

LVD enabe votage seect 3.0V 3.0


LVD enabe votage seect 3.V 3.


ILVR Low Votage Reset Cuent — LVR enabe ENLVD=0 — 0 90 μA

ILVDLow Votage Detection Cuent —

LVR disabe ENLVD=1 — 75 10μA

LVR enabe ENLVD=1 — 90 150

tLVDS LVDO Stabe Time— LVR enabe VBGEN=0

LVD off → on — — 15μs

— LVR disabe VBGEN=0 LVD off → on — — 150

Rev. 1.00 14 i 1 01 Rev. 1.00 15 i 1 01



Bandgap Reference Voltage Characteristics – VBG Ta= -40°C~85°C, unless otherwise specified



VBG Bandga Refeence Votage — tDCK=fSYS/8 -5% 1.04 +5% V

IBGdditiona Cuent fo Bandga Refeence Enabe — LVR disabe LVD disabe — 00 300 μA

tBGS VBG Tun On Stabe Time — No oad — — 150 μs

Note:TheBandgapreferencevoltageisusedastheA/Dconverterinternalsignalinput.

A/D Converter Electrical CharacteristicsTa= -40°C~85°C, typical is 25°C unless otherwise specified



VDD /D Convete Oeating Votage — VREF=VDD .7 — 5.5 V

VD /D Convete Inut Votage — — 0 — VDD/VREF

V

VREF /D Convete Refeence Votage3V — .0 — VDD

V5V — .0 — VDD

DNL Diffeentia Non-ineaity

3V VREF=VDD=VDD tDCK=0.5μs, 10-bit

-3 — +

LSB

5V3V VREF=VDD=VDD tDCK=10μs

10-bit5V3V VREF=VDD=VDD

tDCK=0.5μs, 12-bit-4 — +3

5V3V VREF=VDD=VDD tDCK=10μs

1-bit5V

INL Intega Non-ineaity

3V VREF=VDD=VDD tDCK=0.5μs, 10-bit -4 — +4

LSB

5V3V VREF=VDD=VDD

tDCK=0.5μs, 12-bit -4 — +75V3V

VREF=VDD=VDD tDCK=10μs -4 — +45V

IDCdditiona Cuent fo /D Convete Enabe

3VNo oad tDCK =0.5μs

— 1.0 .0m

5V — 1.5 3.0

tDCK /D Cock Peiod .7V~5.5V10-bit 0.5 — 10

μs1-bit 0.5 — 10

tONST /D Convete On-to-Stat Time .7V~5.5V — 4 — — μstDS /D Saming Time .7V~5.5V 1-bit /D Convete 4 tDCK

tDC/D Convesion Time (Incude /D Same and Hod Time) .7V~5.5V 1-bit /D Convete 1 — 0 tDCK

Rev. 1.00 1 i 1 01 Rev. 1.00 17 i 1 01



Operational Amplifier Electrical CharacteristicsTa= -40°C~85°C, unless otherwise specified



VDDOOperational Amplifier Operating Votage — — . — 5.5 V

IOPOperational Amplifier Operating Cuent —

OP0BW=00B no oad — 1. 3.5

μAOP0BW=01B no oad — 10 1OP0BW=10B no oad — 80 18OP0BW=11B no oad — 00 30

VOSOperational Amplifier Inut Offset Votage

5V Without caibation(O0OF[5:0] =100000B) -15 — +15

mV5V With caibation -1 — +1

VCMOperational Amplifier Common Mode Votage Range — — VSS — VDD-

1.4V V

IOSOperational Amplifier Input Offset Cuent 5V VCM=1/VDD — 1 — n

PSRR Powe Suy Rejection Ratio 5V — 58 70 — dBCMRR Common Mode Rejection Ratio 5V — 58 80 — dBOL Oen Loo Gain — — 0 80 — dB

SR Sew Rate + Sew Rate - 5V

RL=1MΩ CL=0FOP0BW[1:0]=00B 1.0 1.5 —

V/ms

RL=1MΩ CL=0FOP0BW[1:0]=01B 10 15 —

RL=1MΩ CL=0FOP0BW[1:0]=10B 300 500 —

RL=1MΩ CL=0FOP0BW[1:0] =11B 100 1800 —

GBW Operational Amplifier Gain Band Bandwidth 5V

RL=1MΩ CL=100FOP0BW[1:0]=00B .5 5 —

kHz

RL=1MΩ CL=100FOP0BW[1:0]=01B 0 40 —

RL=1MΩ CL=100FOP0BW[1:0]=10B 400 00 —

RL=1MΩ CL=100FOP0BW[1:0] =11B 1300 000 —

Rev. 1.00 1 i 1 01 Rev. 1.00 17 i 1 01



Level Shifter Electrical CharacteristicsTa=-40°C~85°C VCC1=V



ISOURCE OUT0~OUT1 Outut Souce Cuent 5V VOH=0.9VCC1 — -450 — mISINK OUT0~OUT1 Outut Sink Cuent 5V VOL=0.1VCC1 — 450 — mVHIH PDH0~PDH1 Inut High Votage 5V — 0.7VCC1 — VCC1 VVHIL PDH0~PDH1 Inut Low Votage 5V — 0 — 0.3VCC1 V

VDD = 5V, VOL = 0.1VCC

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

2 3 4 5 6 7 8 9

Vcc

Isin

k

VDD = 5V, VOH = 0.9VCC

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

2 3 4 5 6 7 8 9

Vcc

Isou

re

Rev. 1.00 18 i 1 01 Rev. 1.00 19 i 1 01



Voltage Detector Electrical CharacteristicsTa= -40°C~85°C, unless otherwise specified



VDET VCC1 Detect Leve — VCC1=3V~1VtDCK=fSYS/8 - 0.5% 0.VCC1 + 0.5% V

Power-on Reset CharacteristicsTa=5°C



VPOR VDD Stat Votage to Ensue Powe-on Reset — — — — 100 mVRRPOR VDD Rising Rate to Ensue Powe-on Reset — — 0.035 — — V/ms

tPORMinimum Time fo VDD Stays at VPOR to Ensue Powe-on Reset — — 1 — — ms

VDD

tPOR RRPOR

VPOR

Time

Rev. 1.00 18 i 1 01 Rev. 1.00 19 i 1 01



System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.TherangeofthedevicetakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.Thepipeliningscheme is implemented insuchaway that instruction fetchingand instructionexecutionareoverlapped,hence instructionsareeffectivelyexecuted inonecycle,with theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitectural featuresensure thataminimumofexternalcomponents is required toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakes thedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedat thebeginningof theT1clockduringwhichtimeanewinstruction isfetched.TheremainingT2~T4clockscarryout thedecodingandexecution functions. In thisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles, thepipeliningstructureof themicrocontrollerensures thatinstructionsareeffectivelyexecutedinoneinstructioncycle.TheexceptiontothisareinstructionswherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.

Fetch Inst. (PC)Execute Inst. (PC-1) Fetch Inst. (PC+1)

Execute Inst. (PC) Fetch Inst. (PC+)Execute Inst. (PC+1)

Osciato Cock(System Cock)

Phase Cock T1

Phase Cock T

Phase Cock T3

Phase Cock T4

Pogam Counte

Pieining

PC PC+1 PC+

System Clocking and Pipelining

For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

Rev. 1.00 0 i 1 01 Rev. 1.00 1 i 1 01



Execute Inst. 1Fetch Inst.

1 MOV [1H] CLL DELY3 CPL [1H]4 :5 : DELY: NOP

Fetch Inst. 1Execute Inst. Fetch Inst. 3 Fush Pieine

Fetch Inst. Execute Inst. Fetch Inst. 7

Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas"JMP"or"CALL" thatdemandsa jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program Counter

High Byte Low Byte (PCL)

PC10~PC8 PCL7~PCL0

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly;however,asonlythis lowbyteisavailable formanipulation, the jumpsare limited to thepresentpageofmemory that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisorganizedinto6levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

Rev. 1.00 0 i 1 01 Rev. 1.00 1 i 1 01



StackPointe

Stack Leve

Stack Leve 1

Stack Leve 3

:::

Stack Leve

Pogam Memoy

Pogam Counte

Bottom of Stack

To of Stack

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

Rev. 1.00 i 1 01 Rev. 1.00 3 i 1 01



Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthedevicetheProgramMemory isFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdeviceoffersuserstheflexibilitytoconvenientlydebuganddevelop their applicationswhilealsoofferingameansof fieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof2K×16bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

000HInitiaisation Vecto

004H

7FFH 1 bits

Inteut Vectos

03CH

Program Memory Structure

Special VectorsWithin theProgramMemory,certain locationsarereservedfor theresetand interrupts.Thelocation000Hisreservedforusebythedeviceresetforprograminitialisation.Afteradeviceresetisinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRD[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas0.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

Rev. 1.00 i 1 01 Rev. 1.00 3 i 1 01



Last Page o TBHP Registe

TBLP Registe

Pogam Memoy

Registe TBLH Use Seected Registe

ddess

Data1 bits

High Byte Low Byte

Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"0700H"whichreferstothestartaddressofthelastpagewithinthe2KProgramMemoryofthemicrocontroller.Thetablepointerlowbyteregisterissetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"0706H"or6locationsafterthestartofthelastpage.NotethatthevalueforthetablepointerisreferencedtothefirstaddressofthepagethatTBHPpointedifthe"TABRD[m]"instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRDL[m]"instructionisexecuted.

Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2 : :mov a,06h ; initialize table pointer - note that this address is referencedmov tblp,a ; to the last page or the page that tbhp pointed : :tabrdl tempreg1 ; transfers data at program memory address "0706H" ; to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "0705H" to tempreg2 and TBLH ; in this example the data "1AH" is transferred to ; tempreg1 and data "0FH" to register tempreg2 ; the value "00H" will be transferred to the high byte register TBLH : :org 0700h ; sets initial address of last pagedc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :

Rev. 1.00 4 i 1 01 Rev. 1.00 5 i 1 01



In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

Holtek Writer Pins MCU Programming Pins Pin DescriptionICPD P0 Pogamming Seia Data/ddessICPCK P Pogamming CockVDD VDD Powe SuyVSS VSS Gound

TheProgramMemoryandEEPROMdataMemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Duringtheprogrammingprocess,theusermusttakecontroloftheICPDAandICPCKpinsfordataandclockprogrammingpurposestoensurethatnootheroutputsareconnectedtothesetwopins.

* *

Wite_VDD

ICPD

ICPCK

Wite_VSS

To othe Cicuit

VDD

P0

P

VSS

Wite Connecto Signas

MCU PogammingPins

Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitanceof*mustbelessthan1nF.

Rev. 1.00 4 i 1 01 Rev. 1.00 5 i 1 01



On Chip Debug Support – OCDSThereisanEVchipnamedHT45V4630whichisusedtoemulatetheHT45F4630device.TheEVchipdevicealsoprovidesan"On-ChipDebug"functiontodebugtherealMCUdeviceduringthedevelopmentprocess.TheEVchipandtherealMCUdevicearealmostfunctionallycompatibleexceptfor"On-ChipDebug"function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApin is theOCDSData/Address input/outputpinwhile theOCDSCKpin istheOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwith theOCDSDAandOCDSCKpins in thedevicewillhavenoeffect in theEVchip.However, thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.FormoredetailedOCDSinformation,refertothecorrespondingdocumentnamed"Holteke-Linkfor8-bitMCUOCDSUser’sGuide".

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSD OCDSD On-Chi Debug Suot Data/ddess inut/oututOCDSCK OCDSCK On-Chi Debug Suot Cock inut

VDD VDD Powe SuyVSS VSS Gound

Rev. 1.00 i 1 01 Rev. 1.00 7 i 1 01



Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.

StructureDividedintotwoareas, thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersareaccessibleinallbanks,withtheexceptionof theEECregisterataddress40H,whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforthedeviceistheaddress00H.

00H

7FH80H

FFH

Secia Puose Data Memoy

Genea Puose Data Memoy

Bank 1

Bank 0

40HEEC in Bank 1

Data Memory Structure

General Purpose Data MemoryThereare128bytesofgeneralpurposedatamemorywhicharearrangedin80H~FFHofBank0.Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.ByusingthebitoperationinstructionsindividualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue"00H".

Rev. 1.00 i 1 01 Rev. 1.00 7 i 1 01



00H IR0

01H MP0

0H IR1

03H MP1

04H

05H CC

0H PCL

07H TBLP

08H TBLH

09H TBHP

0H STTUS

0BH

0CH

0DH

0EH

0FH

10H

11H

1H

19H

PMSL

18H

PSS

1BH

1H

1DH

1CH

1FH

PDHCL

1EH

SMOD

13H

14H

15H

1H

17H

DTS0

DTS1

POSL

PRTL

40H

41H

4H

49H

48H

4BH

4H

4DH

4CH

4FH

4EH

43H

44H

45H

4H

47H

50H

51H

5H

59H

58H

5BH

5H

5DH

5CH

5FH

5EH

53H

54H

55H

5H

57H

TBC

LVDC

CTRL

WDTC

: Unused ead as 00H

OPCL

BP

Bank0 Bank1

0HHVC

OCPC00

OCPC10

OCPOCL0

OCPCCL0

MFI0

INTC3

MFI1

MFI

MFI4

LVRC

PTMC1

PTMDL

PTMDH

PTMH

PTMRPL

INTEG

INTC0

INTC1

INTC

MFI3

PTML

PTMC0

PTMRPH

OCPD0

0H

1H

H

9H

8H

BH

H

DH

CH

FH

EH

3H

4H

5H

H

7H

30H

31H

3H

39H

38H

3BH

3H

3DH

3CH

3FH

3EH

33H

34H

35H

3H

37H

H

1H

4H

3H

5H

9H

8H

BH

H

DH

CH

FH

EH

7H

70H

71H

7H

73H

74H

75H

7H

77H

H

EEC

EED

EE0

PTM0C0

PTM0C1

PTM0RPH

PTM0DL

SDC0

SDC1

SDOL

OP0C

OP0VOS

PTM0DH

PTM0L

PTM0H

PTM0RPL

SDOH

IICC0

EE1

IICC1

IICD

IIC

ICTOC

PPS1

PBDPS

PWU

PPU

P

PC

PDC

PBPU

RPDH

SSCTL

PB

PBC

PDPU

PD

PPS0

Bank0 Bank1

79H

78H

7BH

7H

7DH

7CH

7FH

7EH

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Unused

PTM1C0

PTM1C1

PTM1RPH

PTM1DL

PTM1DH

PTM1L

PTM1H

PTM1RPL

PTM3C0

PTM3C1

PTM3RPH

PTM3DL

PTM3DH

PTM3L

PTM3H

PTM3RPL

Unused

Unused

Unused

Special Purpose Data Memory

Rev. 1.00 8 i 1 01 Rev. 1.00 9 i 1 01



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsections;howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Register – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.ThemethodofindirectaddressingforRAMdatamanipulationuses theseIndirectAddressingRegistersandMemoryPointers, incontrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof"00H"andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1 TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedto,istheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 code´org 00hstart: mov a,04h ; setup size of block mov block,a mova,offsetadres1 ;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbymp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

Rev. 1.00 8 i 1 01 Rev. 1.00 9 i 1 01



Bank Pointer – BP For thisdevice, theDataMemory isdivided into twobanks,Bank0andBank1.Selecting therequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.

TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePowerDownMode,inwhichcase,theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.

BP RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:SelectDataMemoryBanks

0:Bank01:Bank1

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCL Toprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLH Thesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe"INC"or"DEC"instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Rev. 1.00 30 i 1 01 Rev. 1.00 31 i 1 01



Status Register – STATUSThis8-bitregistercontainstheSCflag,CZflag,zeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheSZ,CZ,PDFandTOflags,bits inthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheSZ,CZ,PDForTOflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.

TheZ,OV,AC,C,SCandCZflagsgenerallyreflectthestatusofthelatestoperations.

• SCistheresultofthe"XOR"operationwhichisperformedbytheOVflagandtheMSBofthecurrentinstructionoperationresult.

• CZistheoperationalresultofdifferentflagsfordifferentinstructions.Refertoregisterdefinitionsformoredetails.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDFisclearedbyasystempower-uporexecutingthe"CLRWDT"instruction.PDFissetbyexecutingthe"HALT"instruction.

• TOisclearedbyasystempower-uporexecutingthe"CLRWDT"or"HALT"instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

Rev. 1.00 30 i 1 01 Rev. 1.00 31 i 1 01



STATUS RegisterBit 7 6 5 4 3 2 1 0

Name SC CZ TO PDF OV Z C CR/W R R R R R/W R/W R/W R/WPOR x x 0 0 x x x x

"x": unknownBit7 SC:Theresultofthe"XOR"operationwhichisperformedbytheOVflagandthe

MSBoftheinstructionoperationresult.Bit6 CZ:Theoperationalresultofdifferentflagsfordifferentinstructions.

ForSUB/SUBM/LSUB/LSUBMinstructions,theCZflagisequaltotheZflag.ForSBC/SBCM/LSBC/LSBCMinstructions, theCZflag is the"AND"operationresultwhichisperformedbythepreviousoperationCZflagandcurrentoperationzeroflag.Forotherinstructions,theCZflagwillnotbeaffected.

Bit5 TO:WatchdogTime-Outflag0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.00 3 i 1 01 Rev. 1.00 33 i 1 01



EEPROM Data memoryThisdevicecontainsanareaof internalEEPROMDataMemory.EEPROM,whichstands forElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply is removed.Byincorporating thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis512×8bitsforthedevice.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusingtwoaddressregistersandadataregisterinBank0andasinglecontrolregisterinBank1.

EEPROM RegistersFourregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregisters,EEA0andEEA1,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEA0,EEA1andEEDregistersarelocatedinBank0, theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

Register Name

Bit7 6 5 4 3 2 1 0

EE0 D7 D D5 D4 D3 D D1 D0EE1 — — — — — — — D8EED D7 D D5 D4 D3 D D1 D0EEC — — — — WREN WR RDEN RD

EEPROM Registers List

EEA0 Register

Bit 7 6 5 4 3 2 1 0

Name D7 D D5 D4 D3 D D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:DataEEPROMaddressDataEEPROMaddressbit7~bit0

Rev. 1.00 3 i 1 01 Rev. 1.00 33 i 1 01



EEA1 RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — — D8R/W — — — — — — — R/WPOR — — — — — — — 0

Bit7~1 Unimplemented,readas"0"Bit0 D8:DataEEPROMaddress

DataEEPROMaddressbit8

EED RegisterBit 7 6 5 4 3 2 1 0

Name D7 D D5 D4 D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:DataEEPROMdataDataEEPROMdatabit7~bit0

EEC RegisterBit 7 6 5 4 3 2 1 0

Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto"1"atthesametimeinoneinstruction.TheWRandRDcannotbesetto"1"atthesametime.

Rev. 1.00 34 i 1 01 Rev. 1.00 35 i 1 01



Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEA1/EEA0register.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationiftheRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.TheapplicationprogramcanpolltheRDbittodeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTowritedatatotheEEPROM,theEEPROMaddressofthedatatobewrittenmustfirstbeplacedin theEEA1/EEA0registerand thedataplaced in theEEDregister.Then thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbeimmediatelysethightoinitiateawritecycle.Thesetwoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbeforeimplementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.Notethatsetting theWRbithighwillnot initiateawritecycle if theWRENbithasnotbeenset.As theEEPROMwritecycle iscontrolledusingan internal timerwhoseoperation isasynchronous tomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.Theapplicationprogramcanthereforepoll theWRbit todeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheEPWEbitintherelevantinterruptregister.WhenanEEPROMwritecycleends,theEPWFrequestflagwillbeset.IftheEEPROMinterruptisenabledandthestackisnotfull,ajumptotheassociatedEEPROMInterruptvectorwilltakeplace.Whentheinterruptisserviced,theEEPROMinterruptrequestflag,EPWF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.MoredetailscanbeobtainedintheInterruptsection.

Rev. 1.00 34 i 1 01 Rev. 1.00 35 i 1 01



Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.

WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.Notethatthedeviceshouldnotenter theIDLEorSLEEPmodeuntil theEEPROMreadorwriteoperationis totallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples• Reading data from the EEPROM – polling methodMOV A,EEPROM_ADRES_L ;userdefinedaddresslowbyteMOV EEA0,AMOV A,EEPROM_ADRES_H ;userdefinedaddresshighbyteMOV EEA1,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ASET IAR1.1 ;setRDENbit,enablereadoperationsSET IAR1.0 ;startReadCycle-setRDbitBACK:SZ IAR1.0 ;checkforreadcycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BPMOV A,EED ;movereaddatatoregisterMOV READ_DATA,A

• Writing Data to the EEPROM – polling methodMOV A,EEPROM_ADRES_L ;userdefinedaddresslowbyteMOV EEA0,AMOV A,EEPROM_ADRES_H ;userdefinedaddresshighbyteMOV EEA1,AMOV A,EEPROM_DATA ;userdefineddataMOV EED,AMOV A,040H ;setupmemorypointerMP1MOV MP1,A ;MP1pointstoEECregisterMOV A,01H ;setupBankPointerMOV BP,ACLR EMISET IAR1.3 ;setWRENbit,enablewriteoperationsSET IAR1.2 ;startWriteCycle-setWRbitSET EMIBACK:SZ IAR1.2 ;checkforwritecycleendJMP BACKCLR IAR1 ;disableEEPROMread/writeCLR BP

Rev. 1.00 3 i 1 01 Rev. 1.00 37 i 1 01



OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandregisters.

Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellasfullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovided to formawiderangeofboth fastandslowsystemoscillators.Thehigher frequencyoscillators providehigherperformancebut carrywith it thedisadvantageof higherpowerrequirements,while theopposite isofcourse truefor the lowerfrequencyoscillators.With thecapabilityofdynamically switchingbetween fast andslowsystemclock, thedevicehas theflexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Frequency PinsExtena High Seed Cysta HXT 400kHz~1MHz OSC1/OSCExtena Low Seed Cysta LXT 3.78kHz XT1/XTIntena High Seed RC HIRC 8/1/1MHz —Intena Low Seed RC LIRC 3kHz —

Oscillator Types

System Clock ConfigurationsTherearefourmethodsofgenerating thesystemclock, twohighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatorsaretheexternalcrystal/ceramicoscillator-HXTandtheinternal8MHz,12MHzand16MHzRCoscillator-HIRC.Thetwolowspeedoscillatorsaretheinternal32kHzRCoscillator-LIRCandtheexternal32.768kHzcrystaloscillator-LXT.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactual sourceclockused foreachof thehighspeedand lowspeedoscillators ischosenviaconfigurationoptions.Thefrequencyof theslowspeedorhighspeedsystemclock isalsodeterminedusing theHLCLKbitandCKS2~CKS0bits in theSMODregister.Note that twooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.TheOSC1andOSC2pinsareusedtoconnecttheexternalcomponentsfortheexternalcrystal.

Rev. 1.00 3 i 1 01 Rev. 1.00 37 i 1 01



HIRC

HLCLK CKS~CKS0 bits

fSYS

High Seed Osciatos

Pescae

fH/

fH/1

fH/4

fH/8

fH/4

fH/3

HXT

fH

High Seed OsciatoConfiguation Otion

LIRC

Low Seed Osciatos

LXT

fSUB

Low Seed OsciatoConfiguation Otion

Fast Wake-u fom SLEEP Mode o IDLE Mode Conto(fo HXT ony)

fSUB

System Clock Configurations

External Crystal/Ceramic Oscillator – HXT TheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer’sspecification.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

Note: 1. RP is nomay not equied. C1 and C ae equied.. though not shown OSC1/OSC ins have a aasitic

caacitance of aound 7F.

To intena cicuits

Internal Oscillator Circuit

C1

C

OSC1

OSC

RFRP

Crystal/Resonator Oscillator – HXT

Rev. 1.00 38 i 1 01 Rev. 1.00 39 i 1 01



HXT Oscillator C1 and C2 ValuesCrystal Frequency C1 C2

1MHz 0F 0F1MHz 0F 0F8MHz 0F 0F4MHz 0F 0F1MHz 100F 100F

Note: C1 and C vaues ae fo guidance ony.

Crystal Recommended Capacitor Values

HXT PWM OutputInordertoenhancethecurrentoutputcapability, thedevicecangenerateaPWMsignalwiththesamefrequencyof theexternalHXToscillator,andthissignal isoutput throughmultipleHPO0pins.ThisfunctioniscontrolledbytheHXT_EXbitintheSSCTLregistertoswitchonoroff.

13.5MHz

HXT

OSC

OSC1

HXT_EX

PWMHPO0

HPO0HXT_EX0: Disabe PWM outut1: Enabe PWM outut

HPO0

fHXT

fHIRCfH

fHXT

HPO0

0V

VDD

Peiod

HXT_EX Bit HXT PWM Output

0 Disabe

1 Enabe

AstheHXTPWMsignalcanbeoutputviamultipleHPO0pinsandtheHPO0pinsarepin-sharedwithI/Opinsorotherfunctions,theHPO0outputfunctionmustfirstbeproperlysetupusingthecorrespondingbitsinthePAPS0andPAPS1pin-sharedfunctionselectionregistersbeforetheHXTPWMfunctionisenabled,toensurethesignalcanbenormallyoutput.

Internal RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.The internalRCoscillatorhas three fixed frequenciesof8MHz,12MHzand16MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Notethatifthisinternalsystemclockoptionisselected,asitrequiresnoexternalpinsforitsoperation.

Rev. 1.00 38 i 1 01 Rev. 1.00 39 i 1 01



External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequired toprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoadd twosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturerspecification.Theexternalparallelfeedbackresistor,RP,isrequired.

Someconfigurationoptionsdetermineif theXT1/XT2pinsareusedfortheLXToscillatororasnormalI/Oorotherpin-sharedfunctionalpins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Oorotherpin-sharedfunctionalpins.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

Note: 1. RP C1 and C ae equied.. though not shown ins have a aasitic caacitance of aound 7F.

To intena cicuits

Internal Oscillator Circuit

C1

C

XT1

XT

RP3.78kHz

Intena RC Osciato

External LXT Oscillator

LXT Oscillator C1 and C2 ValuesCrystal Frequency C1 C2

3.78kHz 10F 10FNote: 1. C1 and C vaues ae fo guidance ony. . RP=5M~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

Rev. 1.00 40 i 1 01 Rev. 1.00 41 i 1 01



LXT Oscillator Low Power FunctionTheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTSPbitintheTBCregister.

LXTSP Bit LXT Operating Mode0 Low-owe1 Quick Stat

WhentheLXTSPbitissettohigh,theLXTQuickStartModewillbeenabled.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhasfullypoweredupitcanbeplacedintotheLow-powermodebyclearingtheLXTSPbittozero.Theoscillatorwillcontinue torunbutwithreducedcurrentconsumption,as thehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.

Itshouldbenotedthat,nomatterwhatconditiontheLXTSPbit isset to, theLXToscillatorwillalwaysfunctionnormally.TheonlydifferenceisthatitwilltakemoretimetostartupifintheLow-powermode.

Internal 32kHz Oscillator – LIRCTheInternal32kHzSystemOscillator isoneof the lowfrequencyoscillatorchoices,which isselectedviaconfigurationoption.It isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.

Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthedevicewithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically, theusercanoptimisetheoperationof theirmicrocontrollertoachievethebestperformance/powerratio.

System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequencyfHorlowfrequencyfSUBsource,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromeitheranHXTorHIRCoscillator,selectedviaaconfigurationoption.ThelowspeedsystemclocksourcecanbesourcedfrominternalclockfSUB.IffSUBisselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillator,selectedviaaconfigurationoption.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.ThefSUBclockisusedasasourcefortheWatchdogtimer,theTimeBaseinterruptfunctionsandfortheTMs.

Rev. 1.00 40 i 1 01 Rev. 1.00 41 i 1 01



HIRC

HLCLK CKS~CKS0 bits

fSYS

High Seed Osciatos

Pescae

fH/

fH/1

fH/4

fH/8

fH/4

fH/3

HXT

fH

High Seed OsciatoConfiguation Otion

LIRC

Low Seed Osciatos

LXT

fSUB

Low Seed OsciatoConfiguation Otion

Fast Wake-u fom SLEEP Mode o IDLE Mode Conto(fo HXT ony)

fSUB

fSYS/4

fSUB fTB Time Base

TBCK

fSUB

fSYS/4

Configuation Otion

fS WDT

Device Clock ConfigurationNote:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillatorwill

stoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

Operating ModeDescription

CPU fSYS fSUB fS

NORML Mode On fH~fH/4 On OnSLOW Mode On fSUB On OnIDLE0 Mode Off Off On On/Off (Note)

IDLE1 Mode Off On On OnSLEEP0 Mode Off Off Off OffSLEEP1 Mode Off Off On On

Note:TheWDTclock,fS,willbeoffandtheWDTwillstoprunningif theWDTclocksourceisselectedfromthesystemclockbyconfigurationoptionregardlessoftheWDTisenabledordisabled.TheWDTclock,fS,willbeonif theWDTclocksourceisselectedfromthefSUBclockandtheWDTisenabled.

Rev. 1.00 4 i 1 01 Rev. 1.00 43 i 1 01



NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromoneofthehighspeedoscillators,eithertheHXTorHIRCoscillators.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbits in theSMODregister.Althoughahighspeedoscillator isused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromoneofthelowspeedoscillators,eithertheLXTortheLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregister is low.IntheSLEEP0modetheCPUwillbestopped,andthefSUBandfSclockswillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.WhenthedeviceisintheSLEEPmode,theLVDfunctionwillbedisabledautomaticallyeveniftheENLVDbitishigh.

SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstruction isexecutedandwhentheIDLENbit intheSMODregister is low.IntheSLEEP1modetheCPUwillbestopped.HoweverthefSUBandfSclockswillcontinuetooperateiftheWatchdogTimerfunctionisenabledwithitsclocksourcecomingfromthefSUB.WhenthedeviceisintheSLEEPmode,theLVDfunctionwillbedisabledautomaticallyeveniftheENLVDbitishigh.

IDLE0 ModeTheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimerandTMs.IntheIDLE0Mode,thesystemoscillatorwillbestopped.IntheIDLE0ModetheWatchdogTimerclock,fS,willeitherbeonoroffdependinguponthefSclocksource.IfthesourceisfSYS/4thenthefSclockwillbeoff,andifthesourcecomesfromfSUBthenfSwillbeon.

IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimerandTMs.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.IntheIDLE1ModetheWatchdogTimerclock,fS,willbeon.

Rev. 1.00 4 i 1 01 Rev. 1.00 43 i 1 01



Control RegisterTheregisters,SMODandCTRL,areusedforoverallcontrolof the internalclockswithin thedevice.

SMOD Register

Bit 7 6 5 4 3 2 1 0

Name CKS CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK

R/W R/W R/W R/W R/W R R R/W R/W

POR 1 1 1 0 0 0 1 0

Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis"0"000:fSUB(fLXTorfLIRC)001:fSUB(fLXTorfLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeeithertheLXTorLIRC,adividedversionof thehighspeedsystemoscillatorcanalsobechosenas thesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto"0"byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.Thereforethisflagwillalwaysbereadas"1"bytheapplicationprogramafterdevicepower-on.

Bit1 IDLEN:IDLEModecontrol0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Rev. 1.00 44 i 1 01 Rev. 1.00 45 i 1 01



Bit0 HLCLK:systemclockselection0:fH/2~fH/64orfSUB1:fH

Thisbit isused toselect if the fHclockor the fH/2~fH/64or fSUBclock isusedasthesystemclock.Whenthebit ishigh thefHclockwillbeselectedandif lowthefH/2~fH/64or fSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

CTRL RegisterBit 7 6 5 4 3 2 1 0

Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

"x" unknownBit7 FSYSON:fSYSControlinIDLEMode

0:Off1:On

Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

Describedelsewhere.Bit1 LRF:LVRControlregistersoftwareresetflag

Describedelsewhere.Bit0 WRF:WDTControlregistersoftwareresetflag

Describedelsewhere.

Fast Wake-upTominimisepowerconsumptionthedevicecanentertheSLEEPorIDLE0Mode,wherethesystemclocksourcetothedevicewillbestopped.Howeverwhenthedeviceiswokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelyeithertheLXTorLIRCoscillator,toactasatemporaryclocktofirstdrivethesystemuntil theoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunctionisfSUB,theFastWake-upfunctionisonlyavailableintheSLEEP1andIDLE0modes.WhenthedeviceiswokenupfromtheSLEEP0mode,theFastWake-upfunctionhasnoeffectbecausethefSUBclockisstopped.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHXToscillator isselectedas theNORMALModesystemclock,andif theFastWake-upfunctionisenabled,thenitwilltakeonetotwotSUBclockcyclesoftheLIRCorLXToscillatorforthesystemtowake-up.ThesystemwilltheninitiallyrununderthefSUBclocksourceuntil128HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

If theHIRCoscillatororLIRCoscillator isusedasthesystemoscillator thenitwill take15~16clockcyclesof theHIRCor1~2cyclesof theLIRCtowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

Rev. 1.00 44 i 1 01 Rev. 1.00 45 i 1 01



System Oscillator

FSTEN Bit

Wake-up Time(SLEEP0 Mode)

Wake-up Time(SLEEP1 Mode)

Wake-up Time(IDLE0 Mode)

Wake-up Time(IDLE1 Mode)

HXT

0 18 HXT cyces 18 HXT cyces 1~ HXT cyces

1 18 HXT cyces

1~ fSUB cyces(System uns with fSUB first for 128 HXT cyces and then switches ove

to un with the HXT cock)

1~ HXT cyces

HIRC x 15~1 HIRC cyces 15~1 HIRC cyces 1~ HIRC cycesLIRC x 1~ LIRC cyces 1~ LIRC cyces 1~ LIRC cycesLXT x 104 LXT cyces 104 LXT cyces 1~ LXT cyces

"x": don’t caeWake-Up Times

Operating Mode SwitchingThedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.Insimpleterms,ModeSwitchingbetweentheNORMALModeandSLOWModeisexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModes to theSLEEP/IDLEModes isexecutedvia theHALT instruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheCTRLregister.WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofother internal functions.Theaccompanyingflowchartshowswhathappenswhen thedevicemovesbetweenthevariousoperatingmodes.

NORMALfSYS=fH~fH/4

fH onCPU unfSYS onfSUB on

IDLE1HLT instuction executed

CPU stoIDLEN=1

FSYSON=1fSYS onfSUB on

IDLE0HLT instuction executed

CPU stoIDLEN=1

FSYSON=0fSYS offfSUB on

SLOWfSYS=fSUBCPU unfSYS onfSUB onfH off

SLEEP1HLT instuction executed

fSYS offCPU stoIDLEN=0fSUB on

WDT on

SLEEP0HLT instuction executed

fSYS offCPU stoIDLEN=0fSUB off

WDT off

Rev. 1.00 4 i 1 01 Rev. 1.00 47 i 1 01



NORMAL Mode to SLOW Mode SwitchingWhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto"0"andsettheCKS2~CKS0bitsto"000"or"001"intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLXTor theLIRCoscillatorsandthereforerequires theseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

NORMAL Mode

SLOW Mode

CKS~CKS0 = 00xB &HLCLK = 0

SLEEP0 Mode

IDLEN=0HLT instuction is executed

SLEEP1 Mode

IDLE0 Mode

IDLE1 Mode

WDT is off

IDLEN=0HLT instuction is executed

WDT is on

IDLEN=1 FSYSON=0HLT instuction is executed

IDLEN=1 FSYSON=1HLT instuction is executed

Rev. 1.00 4 i 1 01 Rev. 1.00 47 i 1 01



SLOW Mode to NORMAL Mode SwitchingInSLOWModethesystemuseseither theLXTorLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbesetto"1"orHLCLKbitis"0",butCKS2~CKS0issetto"010","011","100","101","110"or"111".Asacertainamountof timewillberequiredfor thehighfrequencyclocktostabilise, thestatusof theHTObit ischecked.Theamountof timerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

NORMAL Mode

SLOW Mode

CKS2~CKS0 ≠ 000B or 001B as HLCLK = 0 or HLCLK = 1

SLEEP0 Mode

IDLEN=0HALT instruction is executed

SLEEP1 Mode

IDLE0 Mode

IDLE1 Mode

WDT is off

IDLEN=0HALT instruction is executed

WDT is on

IDLEN=1, FSYSON=0HALT instruction is executed

IDLEN=1, FSYSON=1HALT instruction is executed

Entering the SLEEP0 ModeThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andtheWDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandthefSUBclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstoppednomatteriftheWDTclocksourceoriginatesfromthefSUBclockorfromthesystemclock.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Rev. 1.00 48 i 1 01 Rev. 1.00 49 i 1 01



Entering the SLEEP1 ModeThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"0"andtheWDTorLVDon.When this instruction isexecutedunder theconditionsdescribedabove, thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,buttheWDTorLVDwillremainwiththeclocksourcecomingfromthefSUBclock.


• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefromthefSUBclockastheWDTisenabled.



Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"1"andtheFSYSONbitinCTRLregisterequalto"0".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,buttheTimeBaseclockandfSUBclockwillbeon.


• TheWDTwillbeclearedandresumecountingiftheWDTclocksourceisselectedtocomefromthefSUBclockandtheWDTisenabled.TheWDTwillstopifitsclocksourceoriginatesfromthesystemclock.



Entering the IDLE1 Mode ThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto"1"andtheFSYSONbitinCTRLregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe"HALT"instruction.


• TheWDTwillbeclearedandresumecountingiftheWDTisenabledregardlessoftheWDTclocksourcewhichoriginatesfromthefSUBclockorfromthesystemclock.



Rev. 1.00 48 i 1 01 Rev. 1.00 49 i 1 01



Standby Current Considerations AsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestothedevicewhichhasdifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredif theconfigurationoptionshaveenabledtheLXTorLIRCoscillator.

IntheIDLE1Modethesystemoscillatorison,ifthesystemoscillatorisfromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-upAfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

IfthedeviceiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiated.ThePDFflagisclearedbyasystempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe"HALT"instruction.TheTOflagissetifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer, theotherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Rev. 1.00 50 i 1 01 Rev. 1.00 51 i 1 01



Programming ConsiderationsTheHXTandLXToscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEP0ModeandboththeHXTandLXToscillatorsneedtostart-upfromanoffstate.TheLXToscillatorusestheSSTcounterafterHXToscillatorhasfinisheditsSSTperiod.

• IfthedeviceiswokenupfromtheSLEEP0ModetotheNORMALMode,thehighspeedsystemoscillatorneedsanSSTperiod.ThedevicewillexecutefirstinstructionafterHTOis"1".Atthistime,theLXToscillatormaynotbestabilityiffSUBisfromLXToscillator.Thesamesituationoccursinthepower-onstate.TheLXToscillatorisnotreadyyetwhenthefirstinstructionisexecuted.

• IfthedeviceiswokenupfromtheSLEEP1ModetoNORMALMode,andthesystemclocksourceisfromHXToscillatorandFSTENis"1",thesystemclockcanbeswitchedtothelowspeedoscillatorafterwakeup.

• Thereareperipheralfunctions,suchasWDTandTMs,forwhichthefSYSisused.IfthesystemclocksourceisswitchedfromfHtofSUB,theclocksourcetotheperipheralfunctionsmentionedabovewillchangeaccordingly.

• Theon/offconditionoffSUBandfSdependsuponwhethertheWDTisenabledordisabledastheWDTclocksourceisselectedfromfSUB.

Rev. 1.00 50 i 1 01 Rev. 1.00 51 i 1 01



Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fS,whichisinturnsuppliedbyoneoftwosourcesselectedbyconfigurationoption:fSUBorfSYS/4.ThefSUBclockcanbesourcedfromeithertheLXTorLIRCoscillators,againchosenviaaconfigurationoption.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However, itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheLXToscillatorissuppliedbyanexternal32.768kHzcrystal.TheotherWatchdogTimerclocksourceoptionis thefSYS/4clock.TheWatchdogTimersourceclockis thensubdividedbyaratioof28to215togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.TheWDTCissetto01010011BatdeviceresetexceptWDTtime-outHardwareWarmreset.

WDTC RegisterBit 7 6 5 4 3 2 1 0

Name WE4 WE3 WE WE1 WE0 WS WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrolIftheWDTconfigurationoptionis"alwaysenable":10101or01010:EnableOthers:MCUreset

IftheWDTconfigurationoptionis"controlledbytheWDTcontrolregister":10101:Disable01010:EnableOthers:MCUreset

Whenthesebitsarechangedbytheenvironmentalnoiseorsoftwaresettingtoresetthemicrocontroller, theresetoperationwillbeactivatedafter2~3fSUBclockcyclesandtheWRFbitintheCTRLregisterwillbesethigh.

Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fS001:29/fS010:210/fS011:211/fS100:212/fS101:213/fS110:214/fS111:215/fS

These threebitsdetermine thedivisionratioof theWatchdogTimersourceclock,whichinturndeterminesthetimeoutperiod.

Rev. 1.00 5 i 1 01 Rev. 1.00 53 i 1 01






Describedelsewhere.Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

Describedelsewhere.Bit1 LRF:LVRControlregistersoftwareresetflag

Describedelsewhere.Bit0 WRF:WDTControlregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit issethighbytheWDTControlregistersoftwareresetandclearedbytheapplicationprogram.Notethatthisbitcanonlybeclearedtozerobytheapplicationprogram.

Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.

SomeoftheWatchdogTimeroptions,suchasalwaysonselectandclocksourceareselectedusingconfigurationoptions.WithregardtotheWatchdogTimerenable/disablefunction,therearealsofivebits,WE4~WE0,intheWDTCregister toofferadditionalenable/disableandresetcontrolof theWatchdogTimer.IftheWDTconfigurationoptionisdeterminedthattheWDTfunctionisalwaysenabled, theWE4~WE0bitsstillhaveeffectson theWDTfunction.WhentheWE4~WE0bitsvalueisequalto01010Bor10101B,theWDTfunctionisenabled.However,iftheWE4~WE0bitsarechangedtoanyothervaluesexcept01010Band10101B,whichiscausedbytheenvironmentalnoiseorsoftwaresetting,itwillresetthemicrocontrollerafter2~3LIRCclockcycles.IftheWDTconfigurationoptionisdeterminedthattheWDTfunctioniscontrolledbytheWDTcontrolregister,theWE4~WE0valuescandeterminewhichmodetheWDToperatesin.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof10101B.TheWDTfunctionwillbeenablediftheWE4~WE0bitsvalueisequalto01010B.IftheWE4~WE0bitsaresettoanyothervaluesbytheenvironmentalnoiseorsoftwaresetting,except01010Band10101B,itwillresetthedeviceafter2~3LIRCclockcycles.Afterpoweronthesebitswillhavethevalueof01010B.

WDT Configuration Option WE4~WE0 Bits WDT Function

ways Enabe01010B o 10101B Enabeny othe vaues Reset MCU

Contoed by WDT Conto Registe

10101B Disabe01010B Enabe

ny othe vaues Reset MCU

Watchdog Timer Enable/Disable Control

Rev. 1.00 5 i 1 01 Rev. 1.00 53 i 1 01



Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled, thesecondisusingtheWatchdogTimersoftwareclear instructionsandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle"CLRWDT"instructiontocleartheWDT.

Themaximumtimeoutperiod iswhenthe215divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround1secondforthe215divisionratio,andaminimumtimeoutof8msforthe28divisionration.

“CLR WDT”Instuction

8-stage Divide WDT Pescae

WE4~WE0 bits

WDTC Registe

Reset MCU

fSYS/4fS

fS/8

8-to-1 MUX

CLR

WS~WS0 WDT Time-out

LIRC

MUX

ConfiguationOtion

“HLT”Instuction

fSUB

LXT MUX

Configuation Otion

Watchdog Timer

Rev. 1.00 54 i 1 01 Rev. 1.00 55 i 1 01



Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawell-definedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.AnothertypeofresetiswhentheWatchdogTimeroverflowsandresets.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset, is implementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset FunctionsTherearefourwaysinwhicharesetcanoccur.

Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/OportandportcontrolregisterswillpowerupinahighconditionensuringthatallI/Oportswillbefirstsettoinputs.

VDD

Powe-on Reset

SST Time-out

tRSTD

Power-On Reset Timing Chart

Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltageVLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRLregisterwillalsobesethigh.ForavalidLVRsignal,alowsupplyvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistfora timegreater thanthatspecifiedbytLVRintheLVD&LVRElectricalCharacteristics.Ifthelowsupplyvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRvaluecanbeselectedbytheLVS7~LVS0bitsintheLVRCregister.IftheLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoiseorsoftwaresetting,theLVRwillresetthedeviceafter2~3fLIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesethigh.Afterpowerontheregisterwillhavethevalueof01010101B.Notethat theLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.

LVR

Intena Reset

tRSTD + tSST

Low Voltage Reset Timing Chart

Rev. 1.00 54 i 1 01 Rev. 1.00 55 i 1 01



• LVRC Register

Bit 7 6 5 4 3 2 1 0Name LVS7 LVS LVS5 LVS4 LVS3 LVS LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7~LVS0:LVRvoltageselect01010101:2.1V00110011:2.55V10011001:3.15V10101010:3.8VOthervalues:MCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated.The resetoperationwillbeactivatedafterthelowvoltageconditionkeepsmorethanatLVRtime.Inthissituationtheregistercontentswillremainthesameaftersucharesetoccurs.Anyregistervalue,otherthanthefourdefinedLVRvaluesabove,willalsoresultinthegenerationofanMCUreset.Theresetoperationwillbeactivatedafter2~3fLIRCclockcycles.HoweverinthissituationtheregistercontentswillberesettothePORvalue.




Describedelsewhere.Bit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:notoccur1:occurred

ThisbitissethighwhenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:notoccur1:occurred

ThisbitissethighiftheLVRCregistercontainsanynon-definedLVRvoltageregistervalues.Thisineffectactslikeasoftware-resetfunction.Thisbitcanonlybeclearedtozerobytheapplicationprogram.

Bit0 WRF:WDTControlregistersoftwareresetflagDescribedelsewhere.

Watchdog Time-out Reset during Normal Operation TheWatchdogtime-outResetduringnormaloperationis thesameasLVRresetexcept that theWatchdogtime-outflagTOwillbesethigh.

WDT Time-out

Intena ResettRSTD + tSST

WDT Time-out Reset during Normal Operation Timing Chart

Rev. 1.00 5 i 1 01 Rev. 1.00 57 i 1 01



Watchdog Time-out Reset during SLEEP or IDLE Mode TheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedtozeroandtheTOflagwillbesethigh.RefertotheA.C.CharacteristicsfortSSTdetails.

WDT Time-out

Intena ResettSST

WDT Time-out Reset during Sleep or IDLE Timing Chart

Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF Reset Conditions0 0 Powe-on esetu u LVR eset duing Noma o SLOW Mode oeation1 u WDT time-out eset duing Noma o SLOW Mode oeation1 1 WDT time-out eset duing IDLE o SLEEP Mode oeation

"u" stands fo unchangedThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition after ResetPogam Counte Reset to zeoInteuts inteuts wi be disabedWDT Cea afte eset WDT begins countingTime Modues Time Modues wi be tuned offInut/Outut Pots I/O ots wi be setu as inutsStack Pointe Stack Pointe wi oint to the to of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.

Rev. 1.00 5 i 1 01 Rev. 1.00 57 i 1 01



Register Name Power On Reset WDT Time-out(Normal Operation)

WDT Time-out(IDLE/SLEEP)

MP0 x x x x x x x x u u u u u u u u u u u u u u u u

MP1 x x x x x x x x u u u u u u u u u u u u u u u u

BP - - - - - - 0 - - - - - - 0 - - - - - - - u

CC x x x x x x x x u u u u u u u u u u u u u u u u

TBLP x x x x x x x x u u u u u u u u u u u u u u u u

TBLH x x x x x x x x u u u u u u u u u u u u u u u u

TBHP - - - - - x x x - - - - - u u u - - - - - u u u

STTUS x x 0 0 x x x x u u 1 u u u u u u u 11 u u u u

SMOD 111 0 0 0 1 0 111 0 0 0 1 0 u u u u u u u u

TBC 0 0 11 0 111 0 0 11 0 111 u u u u u u u u

LVDC - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

CTRL 0 - - - - x 0 0 0 - - - - 0 0 0 u - - - - u u u

LVRC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u u u u u u u u

EE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

EE1 - - - - - - - 0 - - - - - - - 0 - - - - - - - u

EEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

EED x x x x x x x x x x x x x x x x u u u u u u u u

WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u u

PSS - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PMSL - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

PDHCL - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

DTS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

DTS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

POSL - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

PRTL - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - u u u u

OPCL - - - - 0 - 0 - - - - - 0 - 0 - - - - - u - u -

HVC 0 0 0 - - - - - 0 0 0 - - - - - u u u - - - - -

OCPC00 0 0 0 0 - - - 0 0 0 0 0 - - - 0 u u u u - - - u

OCPC10 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

OCPD0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

OCPOCL0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 u u u u u u u u

OCPCCL0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 u u u u u u u u

INTEG - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - u u u u u u

INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u

INTC1 0 0 0 - 0 0 0 - 0 0 0 - 0 0 0 - u u u - u u u -

INTC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

INTC3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

MFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI1 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI3 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

MFI4 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - u u - - u u

Rev. 1.00 58 i 1 01 Rev. 1.00 59 i 1 01





PTMC0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

PTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTMDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PTML 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTMH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PTMRPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTMRPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PTM3C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

PTM3C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM3DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM3DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PTM3L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM3H - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PTM3RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM3RPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u

PTM0C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

PTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM0DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM0L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM0H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM0RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM0RPH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u - - -

PTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1RPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PTM1RPH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

SDC0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 u u u u u u u u

SDC1 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - u u u u u

SDOL x x x x - - - - x x x x - - - -

u u u u - - - -(DRFS=0)

u u u u u u u u(DRFS=1)

SDOH x x x x x x x x x x x x x x x x

u u u u u u u u(DRFS=0)

- - - - u u u u(DRFS=1)

OP0C - 0 - - - - 0 0 - 0 - - - - 0 0 - u - - - - u u

OP0VOS 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 u u u u u u u u

Rev. 1.00 58 i 1 01 Rev. 1.00 59 i 1 01





IICC0 - - - - 0 0 0 - - - - - 0 0 0 - - - - - u u u -

IICC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u u

IICD x x x x x x x x x x x x x x x x u u u u u u u u

IIC 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - u u u u u u u -

ICTOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PPS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PPS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PBDPS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u

PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PDPU 0 0 - - - - - - 0 0 - - - - - - u u - - - - - -

PD 1 1 - - - - - - 1 1 - - - - - - u u - - - - - -

PDC 1 1 - - - - - - 1 1 - - - - - - u u - - - - - -

RPDH - - - - - - 0 0 - - - - - - u u - - - - - - u u

SSCTL - - 0 0 - - 0 0 - - u u - - u u - - u u - - u u

Note:"u"standsforunchanged"x"standsforunknown"-"standsforunimplemented

Rev. 1.00 0 i 1 01 Rev. 1.00 1 i 1 01



Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectionalinput/outputlineslabeledwithportnamesPA,PBandPD.TheseI/OportsaremappedtotheRAMDataMemorywithspecificaddressesasshownintheSpecialPurposeDataMemorytable.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction"MOVA,[m]",wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Register Name

Bit7 6 5 4 3 2 1 0

P P7 P P5 P4 P3 P P1 P0PC PC7 PC PC5 PC4 PC3 PC PC1 PC0

PPU PPU7 PPU PPU5 PPU4 PPU3 PPU PPU1 PPU0PWU PWU7 PWU PWU5 PWU4 PWU3 PWU PWU1 PWU0

PB PB7 PB PB5 PB4 PB3 PB PB1 PB0PBC PBC7 PBC PBC5 PBC4 PBC3 PBC PBC1 PBC0

PBPU PBPU7 PBPU PBPU5 PBPU4 PBPU3 PBPU PBPU1 PBPU0PD PD7 PD — — — — — —

PDC PDC7 PDC — — — — — —PDPU PDPU7 PDPU — — — — — —

"–": Unimemented ead as "0"I/O Logic Function Registers List

Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPxPU("x"standsforA,BorD),andareimplementedusingweakPMOStransistors.

Note that thepull-highresistorcanbecontrolledbytherelevantpull-highcontrolregisteronlywhenthepin-sharedfunctionalpinisselectedasaninputorNMOSoutput.Otherwise,thepull-highresistorscannotbeenabled.

PxPU RegisterBit 7 6 5 4 3 2 1 0

Name PxPU7 PxPU PxPU5 PxPU4 PxPU3 PxPU PxPU1 PxPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

PxPUn:I/OPortxPinpull-highfunctioncontrol0:Disable1:EnableThePxPUnbitisusedtocontrolthepinpull-highfunction.Herethe"x"canbeA,BorD.However,theactualavailablebitsforeachI/OPortmaybedifferent.

Rev. 1.00 0 i 1 01 Rev. 1.00 1 i 1 01



Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

Notethat thewake-upfunctioncanbecontrolledbythewake-upcontrolregistersonlywhenthepin-sharedfunctionalpinisselectedasgeneralpurposeinput/outputandtheMCUentersthePowerdownmode.

PAWU RegisterBit 7 6 5 4 3 2 1 0

Name PWU7 PWU PWU5 PWU4 PWU3 PWU PWU1 PWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 PAWU7~PAWU0:PA7~PA0wake-upfunctioncontrol0:Disable1:Enable

I/O Port Control RegistersEachI/Oporthas itsowncontrol registerknownasPAC,PBCandPDC, tocontrol the input/outputconfiguration.Withthiscontrolregister,eachCMOSoutputor inputcanbereconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa"1".Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

PxC RegisterBit 7 6 5 4 3 2 1 0

Name PxC7 PxC5 PxC5 PxC4 PxC3 PxC PxC1 PxC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

PxCn:I/OPortxPintypeselection0:Output1:InputThePxCnbitisusedtocontrolthepintypeselection.Herethe"x"canbeA,BorD.However,theactualavailablebitsforeachI/OPortmaybedifferent.

Rev. 1.00 i 1 01 Rev. 1.00 3 i 1 01



Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.

Pin-shared Function Selection RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.

Themostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Toselect thedesiredpin-sharedfunction, thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.Afterthatthecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.Tocorrectlydeselectthepin-sharedfunction,theperipheralfunctionshouldfirstbedisabledandthenthecorrespondingpin-sharedfunctioncontrolregistercanbemodifiedtoselectotherpin-sharedfunctions.

Register Name

Bit7 6 5 4 3 2 1 0

PPS0 P3S1 P3S0 PS1 PS0 P1S1 P1S0 P0S1 P0S0PPS1 P7S1 P7S0 PS1 PS0 P5S1 P5S0 P4S1 P4S0PBDPS PD7S PDS PB7S PBS PB5S PB3S PB0S1 PB0S0SSCTL — — PT0IS OCPIS — — HXT_EX EN_VDET

Pin-shared Function Selection Registers List

• PAPS0 Register

Bit 7 6 5 4 3 2 1 0Name P3S1 P3S0 PS1 PS0 P1S1 P1S0 P0S1 P0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PA3S1~PA3S0:PA3pin-sharedfunctionselection00:PA3/PTCK301:AN310:PTP111:HPO0

Bit5~4 PA2S1~PA2S0:PA2pin-sharedfunctionselection00:PA2/PTCK201:SCL10:PA2/PTCK211:PA2/PTCK2

Bit3~2 PA1S1~PA1S0:PA1pin-sharedfunctionselection00:PA1/PTPI101:AN110:PTP111:HPO0

Rev. 1.00 i 1 01 Rev. 1.00 3 i 1 01



Bit1~0 PA0S1~PA0S0:PA0pin-sharedfunctionselection00:PA0/PTPI001:SDA10:PA0/PTPI011:PA0/PTPI0

• PAPS1 Register

Bit 7 6 5 4 3 2 1 0Name P7S1 P7S0 PS1 PS0 P5S1 P5S0 P4S1 P4S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PA7S1~PA7S0:PA7pin-sharedfunctionselection00:PA701:AN710:PA711:PA7

Bit5~4 PA6S1~PA6S0:PA6pin-sharedfunctionselection00:PA601:AN610:OCP0REF/ADCREF11:PA6

Bit3~2 PA5S1~PA5S0:PA5pin-sharedfunctionselection00:PA501:OP0OUT10:PTP111:HPO0

Bit1~0 PA4S1~PA4S0:PA4pin-sharedfunctionselection00:PA4/INT001:AN410:PTP011:PA4/INT0

• PBDPS Register

Bit 7 6 5 4 3 2 1 0Name PD7S PDS PB7S PBS PB5S PB3S PB0S1 PB0S0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 PD7S:PD7pin-sharedfunctionselection0:PD71:OCPI0

Bit6 PD6S:PD6pin-sharedfunctionselection0:PD61:OCPI0

Bit5 PB7S:PB7pin-sharedfunctionselection0:PB71:OCPAO0

Bit4 PB6S:PB6pin-sharedfunctionselection0:PB61:OP0INN

Bit3 PB5S:PB5pin-sharedfunctionselection0:PB51:OP0INP

Rev. 1.00 4 i 1 01 Rev. 1.00 5 i 1 01



Bit2 PB3S:PB3pin-sharedfunctionselection0:PB3/PTP3I1:PTP3

Bit1~0 PB0S1~PB0S0:PB0pin-sharedfunctionselection00:PB0/PTP2I/PTCK0/INT101:PTP210:PB0/PTP2I/PTCK0/INT111:PB0/PTP2I/PTCK0/INT1

• SSCTL Register

Bit 7 6 5 4 3 2 1 0Name — — PT0IS OCPIS — — HXT_EX EN_VDETR/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 PT0IS:PTP0Iinputsourcepinselection

0:FromPA01:FrominternalOCP0Osignal

Bit5 OCPIS:OCPI0inputsourcepinselection0:FromPD61:FromPD7

Bit3~2 Unimplemented,readas"0"Bit1 HXT_EX:HXTPWMoutputcontrol

0:Disable1:Enable

ThisbitisusedtocontrolthePWMsignaloutputwithHXTfrequency.RefertotheOscillatorssectionformoredetails.

Bit0 EN_VDET:Highvoltagepowersupplydetectionfunctioncontrol0:Disable1:Enable

Thisbitisusedtocontrolthehighvoltagepowersupplydetectionfunctionenabledordisabled,thedetailsofwhicharedescribedintheHighVoltageDriversection.

Rev. 1.00 4 i 1 01 Rev. 1.00 5 i 1 01



I/O Pin StructuresTheaccompanyingdiagramillustratestheinternalstructuresoftheI/Ologicfunction.Astheexactlogicalconstructionof theI/Opinwilldifferfromthisdrawing, it issuppliedasaguideonlytoassistwiththefunctionalunderstandingofthelogicfunctionI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

MUX

VDD

Conto Bit

Data Bit

Data Bus

Wite Conto Registe

Chi Reset

Read Conto Registe

Read Data Registe

Wite Data Registe

System Wake-u Wake-u Seect

I/O in

WeakPu-u

Pu-highRegisteSeect

Q

D

CK

Q

D

CK

Q

QS

S

P ony

Logic Function Input/Output Structure

Programming Considerations Withintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PxC,arethenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,Px,arefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbitsintheportcontrolregisterusingthe"SET[m].i"and"CLR[m].i"instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Rev. 1.00 i 1 01 Rev. 1.00 7 i 1 01



Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

Thegeneralfeaturesof thePeriodic typeTMaredescribedherewithmoredetailedinformationprovidedinthePeriodicTMsection.

IntroductionThedevicecontainsfourPeriodictypeTMs.ThemainfeaturesofthePTMaresummarisedintheaccompanyingtable.

Function PTMTime/Counte √I/P Catue √Comae Match Outut √PWM Channes 1Singe Puse Outut 1PWM ignment EdgePWM djustment Peiod & Duty Duty o Peiod

PTM Function Summary

TM OperationThePeriodic typeTMs offer adiverse rangeof functions, fromsimple timingoperations toPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is tosee it in termsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

TM Clock SourceTheclocksourcewhichdrivesthemaincounterintheTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingthePTnCK2~PTnCK0bitsinthePTMncontrolregisters.TheclocksourcecanbearatioofthesystemclockfSYSortheinternalhighclockfH,thefSUBclocksourceortheexternalPTCKnpin.ThePTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsThePeriodicTypeTMshavetwointernalinterrupts,oneforeachoftheinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerateditcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

Rev. 1.00 i 1 01 Rev. 1.00 7 i 1 01



TM External PinsEachofthePTMshastwoTMinputpins,withthelabelPTCKnandPTPnI.ThePTMninputpin,PTCKn,isessentiallyaclocksourceforthePTMnandisselectedusingthePTnCK2~PTnCK0bitsinthePTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThePTCKninputpincanbechosentohaveeitherarisingorfallingactiveedge.ThePTCKnpinisalsousedastheexternaltriggerinputpininsinglepulseoutputmodeortheexternaltriggerinputsourceincaptureinputmodeforthePTMn.

TheotherPTMn inputpin,PTPnI, is thecaptureinputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingthePTnIO1~PTnIO0bitsinthePTMnC1register.

ThePTMseachhasoneoutputpin,PTPn.WhentheTMisintheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalPTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.

TM Input/Output Pin SelectionSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingtherelevantpin-sharedfunctionselectionregisters,withthecorrespondingselectionbits ineachpin-sharedfunctionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.

PTMn

PTCKn

PTPnCCR outut/PWM signa

Catue inut

TCK inut/catue inut

PTPnI

Singe use

PTM Function Pin Control Block Diagram

Rev. 1.00 8 i 1 01 Rev. 1.00 9 i 1 01



Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRPregisters,allhavea lowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

AstheCCRAandCCRPregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheregister iscarriedout inaspecificwaydescribedabove, it isrecommendedtousethe"MOV"instructiontoaccess theCCRAandCCRPlowbyteregisters,namedPTMnALandPTMnRPL,usingthefollowingaccessprocedures.AccessingtheCCRAorCCRPlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data Bus

8-bit Buffe

PTMnDHPTMnDL

PTMnHPTMnL

PTMn Counte Registe (Read ony)

PTMn CCR Registe (Read/Wite)

PTMnRPHPTMnRPL

PTMn CCRP Registe (Read/Wite)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRAorCCRP♦ Step1.WritedatatoLowBytePTMnALorPTMnRPL

– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighBytePTMnAHorPTMnRPH

– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydatais latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRAorCCRP♦ Step1.ReaddatafromtheHighBytePTMnDH,PTMnAHorPTMnRPH

– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowBytePTMnDL,PTMnALorPTMnRPL– Thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.00 8 i 1 01 Rev. 1.00 9 i 1 01



Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.

fSYS

fSYS/4

fH/4fH/1

fSUB

PTCKn

000

001

010

011

100

101

110

111

PTnCK~PTnCK0

10-bit /1-bitCount-u Counte

10-bit /1-bit Comaato P

CCRP

b0~b9/b0~b15

10-bit /1-bitComaato

PTnONPTnPU

Comaato Match

Comaato P Match

Counte Cea 01

Outut Conto

Poaity Conto PTPn

PTnOC

PTnM1 PTnM0PTnIO1 PTnIO0

PTMnF Inteut

PTMPnF Inteut

PTnPOL

CCR

PTnCCLR

EdgeDetecto

PTnIO1 PTnIO0

fSUB

10

PTnDPX

PTPnI

b0~b9/b0~b15

Note:1.AsthePTCKn,PTPnandPTPnIpinsarepin-sharedwithI/Opins,thecorrespondingpin-sharedselectionbitsshouldfirstbeproperlyconfigured.

2.ForthePTM0,PTP0IinputsourcecanbeselectedfromtheexternalPA0pinortheinternalOCPcircuitOCPO0signalbythePTP0ISbitintheSSCTLregister.

3.ThesizeofPTM0andPTM1is16-bitwide,whilethesizeofPTM2andPTM3is10-bitwide.Periodic Type TM Block Diagram (n=0~3)

Periodic TM OperationTherearetwosizesofPeriodicTMs,oneis10-bitwideandtheotheris16-bitwide.Itscoreisa10-bitor16-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPandCCRAcomparatoreachis10-bitor16-bitwide.

Theonlywayofchangingthevalueofthe10-bitor16-bitcounterusingtheapplicationprogram,istoclearthecounterbychangingthePTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aPTMninterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolmorethanoneoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

Rev. 1.00 70 i 1 01 Rev. 1.00 71 i 1 01



Periodic Type TM Register Description Overalloperationof thePeriodicTypeTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitor16-bitvalue,whiletworead/writeregisterpairsexist tostoretheinternal10-bitor16-bitCCRAvalueandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

RegisterName

Bit7 6 5 4 3 2 1 0

PTMnC0 PTnPU PTnCK PTnCK1 PTnCK0 PTnON — — —PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnDPX PTnCCLRPTMnDL D7 D D5 D4 D3 D D1 D0PTMnDH D15 D14 D13 D1 D11 D10 D9 D8PTMnL D7 D D5 D4 D3 D D1 D0PTMnH D15 D14 D13 D1 D11 D10 D9 D8PTMnRPL D7 D D5 D4 D3 D D1 D0PTMnRPH D15 D14 D13 D1 D11 D10 D9 D8

16-bit Periodic TM Registers List (n=0~1)

RegisterName

Bit7 6 5 4 3 2 1 0

PTMnC0 PTnPU PTnCK PTnCK1 PTnCK0 PTnON — — —PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnDPX PTnCCLRPTMnDL D7 D D5 D4 D3 D D1 D0PTMnDH — — — — — — D9 D8PTMnL D7 D D5 D4 D3 D D1 D0PTMnH — — — — — — D9 D8PTMnRPL D7 D D5 D4 D3 D D1 D0PTMnRPH — — — — — — D9 D8

10-bit Periodic TM Registers List (n=2~3)

PTMnC0 Register – n=0~3Bit 7 6 5 4 3 2 1 0

Name PTnPU PTnCK PTnCK1 PTnCK0 PTnON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 PTnPAU:PTMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditionthePTMnwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Rev. 1.00 70 i 1 01 Rev. 1.00 71 i 1 01



Bit6~4 PTnCK2~PTnCK0:SelectPTMnCounterclock000:fSYS/4001:fSYS010:fH/16011:fH/64100:fSUB101:fSUB110:PTCKnrisingedgeclock111:PTCKnfallingedgeclock

Thesethreebitsareusedtoselect theclocksourcefor thePTMn.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 PTnON:PTMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionofthePTMn.Settingthebithighenablesthecountertorun,clearingthebitdisablesthePTMn.Clearingthisbit tozerowillstopthecounterfromcountingandturnoff thePTMnwhichwillreduceitspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.If thePTMnis in theCompareMatchOutputMode,PWMoutputModeorSinglePulseOutputModethenthePTMnoutputpinwillberesettoitsinitialcondition,asspecifiedbythePTnOCbit,whenthePTnONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas"0"

PTMnC1 Register – n=0~3Bit 7 6 5 4 3 2 1 0

Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnDPX PTnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PTnM1~PTnM0:SelectPTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMOutputModeorSinglePulseOutputMode11:Timer/CounterMode

Thesebits setup the requiredoperatingmode for thePTMn.Toensure reliableoperation thePTMnshouldbeswitchedoffbeforeanychangesaremade to thePTnM1andPTnM0bits.IntheTimer/CounterMode, thePTMnoutputpincontrolmustbedisabled.

Bit5~4 PTnIO1~PTnIO0:SelectPTMnexternalpinfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMOutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

Rev. 1.00 7 i 1 01 Rev. 1.00 73 i 1 01



CaptureInputMode00:InputcaptureatrisingedgeofPTPnIorPTCKn01:InputcaptureatfallingedgeofPTPnIorPTCKn10:Inputcaptureatfalling/risingedgeofPTPnIorPTCKn11:Inputcapturedisabled

Timer/CounterModeUnused

ThesetwobitsareusedtodeterminehowthePTMnoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodethePTMnisrunning.IntheCompareMatchOutputMode,thePTnIO1andPTnIO0bitsdeterminehowthePTMnoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.ThePTMnoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero, thennochangewill takeplaceon theoutput.The initialvalueof thePTMnoutputpinshouldbesetupusingthePTnOCbit in thePTMnC1register.Note thattheoutputlevelrequestedbythePTnIO1andPTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingthePTnOCbitotherwisenochangewilloccuronthePTMnoutputpinwhenacomparematchoccurs.AfterthePTMnoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingthelevelofthePTnONbitfromlowtohigh.InthePWMOutputMode, thePTnIO1andPTnIO0bitsdeterminehowthePTMnoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytoonlychangethevaluesofthePTnIO1andPTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif thePTnIO1andPTnIO0bitsarechangedwhenthePTMnisrunning.

Bit3 PTnOC:PTMnPTPnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMOutputMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for thePTMnoutputpin.ItsoperationdependsuponwhetherPTMnisbeingused in theCompareMatchOutputModeor in thePWMOutputMode/SinglePulseOutputMode.IthasnoeffectifthePTMnisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelofthePTMnoutputpinbeforeacomparematchoccurs.In thePWMOutputModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 PTnPOL:PTMnPTPnOutputpolarityControl0:Non-invert1:Invert

Thisbitcontrols thepolarityof thePTPnoutputpin.Whenthebit issethigh thePTMnoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectifthePTMnisintheTimer/CounterMode.

Bit1 PTnDPX:PTMnCaptureTriggerSourceSelection0:FromPTPnIpin1:FromPTCKnpin

Rev. 1.00 7 i 1 01 Rev. 1.00 73 i 1 01



Bit0 PTnCCLR:SelectPTMnCounterclearcondition0:PTMnComparatorPmatch1:PTMnComparatorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththePTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTnCCLRbitisnotusedinthePWMOutputMode,SinglePulseorCaptureInputMode.

PTMnDL Register – n=0~3Bit 7 6 5 4 3 2 1 0

Name D7 D D5 D4 D3 D D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:PTMnCounterLowByteRegisterbit7~bit0PTMn10-bit/16-bitCounterbit7~bit0

PTMnDH Register – n=0~1Bit 7 6 5 4 3 2 1 0

Name D15 D14 D13 D1 D11 D10 D9 D8R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:PTMnCounterHighByteRegisterbit7~bit0PTMn16-bitCounterbit15~bit8

PTMnDH Register – n=2~3Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:PTMnCounterHighByteRegisterbit1~bit0

PTMn10-bitCounterbit9~bit8

PTMnAL Register – n=0~3Bit 7 6 5 4 3 2 1 0


Bit7~0 D7~D0:PTMnCCRALowByteRegisterbit7~bit0PTMn10-bit/16-bitCCRAbit7~bit0

Rev. 1.00 74 i 1 01 Rev. 1.00 75 i 1 01



PTMnAH Register – n=0~1Bit 7 6 5 4 3 2 1 0

Name D15 D14 D13 D1 D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:PTMnCCRAHighByteRegisterbit7~bit0PTMn16-bitCCRAbit15~bit8

PTMnAH Register – n=2~3Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:PTMnCCRAHighByteRegisterbit1~bit0

PTMn10-bitCCRAbit9~bit8

PTMnRPL Register – n=0~3Bit 7 6 5 4 3 2 1 0


Bit7~0 D7~D0:PTMnCCRPLowByteRegisterbit7~bit0PTMn10-bit/16-bitCCRPbit7~bit0

PTMnRPH Register – n=0~1Bit 7 6 5 4 3 2 1 0

Name D15 D14 D13 D1 D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:PTMnCCRPHighByteRegisterbit7~bit0PTMn16-bitCCRPbit15~bit8

PTMnRPH Register – n=2~3Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:PTMnCCRPHighByteRegisterbit1~bit0

PTMn10-bitCCRPbit9~bit8

Rev. 1.00 74 i 1 01 Rev. 1.00 75 i 1 01



Periodic Type TM Operating Modes TheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTnM1andPTnM0bitsinthePTMnC1register.

Compare Match Output ModeTo select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothPTMAnFandPTMPnFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IfthePTnCCLRbitinthePTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly thePTMAnFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTnCCLRishighnoPTMPnFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbeclearedtozero.

Asthenameofthemodesuggests,afteracomparisonismade,thePTMnoutputpin,willchangestate.ThePTMnoutputpinconditionhoweveronlychangesstatewhenaPTMAnFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMPnFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectonthePTMnoutputpin.ThewayinwhichthePTMnoutputpinchangesstatearedeterminedbytheconditionofthePTnIO1andPTnIO0bitsinthePTMnC1register.ThePTMnoutputpincanbeselectedusingthePTnIO1andPTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionofthePTMnoutputpin,whichissetupafterthePTnONbitchangesfromlowtohigh,issetupusingthePTnOCbit.NotethatifthePTnIO1andPTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.00 7 i 1 01 Rev. 1.00 77 i 1 01



Counte Vaue

0x3FF/0xFFFF

CCRP

CCR

PTnON

PTnPU

PTnPOL

CCRP Int. Fag PTMPnF

CCR Int. Fag PTMnF

PTMn O/P Pin

Time

CCRP=0

CCRP > 0

Counte ovefowCCRP > 0Counte ceaed by CCRP vaue

Pause

Resume

Sto

Counte Restat

PTnCCLR = 0; PTnM [1:0] = 00

Outut in set to initia Leve Low if PTnOC=0

Outut Togge with PTMnF fag

Note PTnIO [1:0] = 10 ctive High Outut seectHee PTnIO [1:0] = 11

Togge Outut seect

Outut not affected by PTMnF fag. Remains High unti eset by PTnON bit

Outut PinReset to Initia vaue

Outut contoed by othe in-shaed function

Outut Invetswhen PTnPOL is high

Compare Match Output Mode – PTnCCLR=0 (n=0~3)Note:1.WithPTnCCLR=0aComparatorPmatchwillclearthecounter

2.ThePTMnoutputpiniscontrolledonlybythePTMAnFflag3.TheoutputpinisresettoitsinitialstatebyaPTnONbitrisingedge

Rev. 1.00 7 i 1 01 Rev. 1.00 77 i 1 01



Counte Vaue

0x3FF/0xFFFF

CCRP

CCR

PTnON

PTnPU

PTnPOL


CCR Int. Fag PTMnF

PTMn O/P Pin

Time

CCR=0

CCR = 0Counte ovefowCCR > 0 Counte ceaed by CCR vaue

Pause

Resume

Sto Counte Restat

PTnCCLR = 1; PTnM [1:0] = 00

Outut in set to initia Leve Low if PTnOC=0

Outut Togge with PTMnF fag

Note PTnIO [1:0] = 10 ctive High Outut seectHee PTnIO [1:0] = 11

Togge Outut seect

Outut not affected by PTMnF fag. Remains High unti eset by PTnON bit

Outut PinReset to Initia vaue

Outut contoed by othe in-shaed function

Outut Invetswhen PTnPOL is high

PTMPF not geneated

No PTMnF fag geneated on CCR ovefow

Outut does not change

Compare Match Output Mode – PTnCCLR=1 (n=0~3)Note:1.WithPTnCCLR=1aComparatorAmatchwillclearthecounter

2.ThePTMnoutputpiniscontrolledonlybythePTMAnFflag3.TheoutputpinisresettoitsinitialstatebyaPTnONbitrisingedge4.APTMPnFflagisnotgeneratedwhenPTnCCLR=1

Rev. 1.00 78 i 1 01 Rev. 1.00 79 i 1 01



Timer/Counter Mode To select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output Mode To select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register shouldbe set to 10respectively.ThePWMfunctionwithinthePTMnisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignalof fixedfrequencybutofvaryingdutycycleonthePTMnoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMOutputMode,thePTnCCLRbithasnoeffectonthePWMoperation.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregister isusedtocleartheinternalcounterandthuscontrol thePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTnOCbitinthePTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTnIO1andPTnIO0bitsareusedtoenablethePWMoutputortoforcethePTMnoutputpintoafixedhighorlowlevel.ThePTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 10-bit PTMn, PWM Output Mode

CCRP 1~1023 0Peiod 1~103 cocks 104 cocksDuty CCR

IffSYS=16MHz,PTMnclocksourceselectfSYS/4,CCRP=512andCCRA=128,

ThePTMnPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• 16-bit PTMn, PWM Output Mode

CCRP 1~65535 0Peiod 1~5535 cocks 553 cocksDuty CCR

IffSYS=16MHz,PTMnclocksourceselectfSYS/4,CCRP=512andCCRA=128,

ThePTMnPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=7.8125kHz,duty=128/512=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

Rev. 1.00 78 i 1 01 Rev. 1.00 79 i 1 01



Counte Vaue

CCRP

CCR

PTnON

PTnPU

PTnPOL


CCR Int. Fag PTMnF

PTMn O/P Pin(PTnOC=1)

Time

Counte ceaed by CCRP

Pause Resume Counte Sto if PTnON bit ow

Counte Reset when PTnON etuns high

PTnM [1:0] = 10

PWM Duty Cyce set by CCR

PWM esumes oeation

Outut contoed by othe in-shaed function Outut Invets

When PTnPOL = 1PWM Peiod set by CCRP


PWM Output Mode (n=0~3)Note:1.CounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenPTnIO[1:0]=00or014.ThePTnCCLRbithasnoinfluenceonPWMoperation

Rev. 1.00 80 i 1 01 Rev. 1.00 81 i 1 01



Single Pulse Mode To select thismode, bitsPTnM1andPTnM0 in thePTMnC1 register shouldbe set to 10respectivelyandalsothePTnIO1andPTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseonthePTMnoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTnONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalPTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaPTMninterrupt.ThecountercanonlyberesetbacktozerowhenthePTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTnCCLRbitisnotusedinthisMode.

PTnON bit0 → 1

S/W Command SET“PTnON”

oPTCKn Pin Tansition

PTnON bit1 → 0

CCR Taiing Edge

S/W Command CLR“PTnON”

oCCR Comae Match

PTPn Outut Pin

Puse Width = CCR Vaue

CCR Leading Edge

Single Pulse Generation (n=0~3)

Rev. 1.00 80 i 1 01 Rev. 1.00 81 i 1 01



Counte Vaue

CCRP

CCR

PTnON

PTnPU

PTnPOL


CCR Int. Fag PTMnF


Time

Counte stoed by CCR

PauseResume Counte Stos

by softwae

Counte Reset when PTnON etuns high

PTnM [1:0] = 10 ; PTnIO [1:0] = 11

Puse Width set by CCR

Outut Invetswhen PTnPOL = 1

No CCRP Inteuts geneated


PTCKn in

Softwae Tigge

Ceaed by CCR match

PTCKn in Tigge

uto. set by PTCKn in

Softwae Tigge

Softwae Cea

Softwae TiggeSoftwae

Tigge

Single Pulse Mode (n=0~3)Note:1.CounterstoppedbyCCRA

2.CCRPisnotused3.ThepulseistriggeredbythePTCKnpinorbysettingthePTnONbithigh4.APTCKnpinactiveedgewillautomaticallysetthePTnONbithigh5.IntheSinglePulseMode,PTnIO[1:0]mustbesetto"11"andcannotbechanged.

Rev. 1.00 8 i 1 01 Rev. 1.00 83 i 1 01



Capture Input Mode ToselectthismodebitsPTnM1andPTnM0inthePTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPnIorPTCKnpinwhichisselectedusingthePTnDPXbit inthePTMnC1register.The inputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTnIO1andPTnIO0bitsinthePTMnC1register.ThecounterisstartedwhenthePTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsonthePTPnIorPTCKnpin thepresentvalue in thecounterwillbelatchedintotheCCRAregistersandaPTMninterruptgenerated.IrrespectiveofwhateventsoccuronthePTPnIorPTCKnpin,thecounterwillcontinuetofreerununtilthePTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aPTMninterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTnIO1andPTnIO0bitscanselecttheactivetriggeredgeonthePTPnIorPTCKnpintobearisingedge,fallingedgeorbothedgetypes.IfthePTnIO1andPTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPnIorPTCKnpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AsthePTPnIorPTCKnpinispinsharedwithotherfunctions,caremustbetakenifthePTMnisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTnCCLR,PTnOCandPTnPOLbitsarenotusedinthisMode.

Rev. 1.00 8 i 1 01 Rev. 1.00 83 i 1 01



Counter Value

YY

CCRP

PTnON

PTnPU


CCR Int. Fag PTMnF

CCR Vaue

Time

Counte ceaed by CCRP

PauseResume

Counte Reset

PTnM[1:0] = 01

PTM Catue PinPTPnI o PTCKn

XX

Counte Sto

PTnIO [1:0] Vaue

ctive edge

ctive edge ctive edge

00 - Rising edge 01 - Faing edge 10 - Both edges 11 - Disabe Catue

XX YY XX YY

Capture Input Mode (n=0~3)Note:1.PTnM[1:0]=01andactiveedgesetbythePTnIO[1:0]bits

2.APTMnCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.PTnCCLRbitnotused4.Nooutputfunction–PTnOCandPTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

Rev. 1.00 84 i 1 01 Rev. 1.00 85 i 1 01



Analog to Digital Converter Theneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D Converter OverviewThisdevicecontainsamulti-channelanalogtodigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoa12-bitdigitalvalue.Italsocanconvert theinternalsignals, thepowersupplyVCC1dividedvoltage,theOverCurrentProtectioncircuitoutputsignalortheBandgapreferencevoltage,intoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSACS3~SACS0bits.

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

External Input Channels Internal Signals Channel Select Bits

N1 N3 N4 N N7

N0: OCPO0 signaN5: High votage owe suy divided votageVDET

Bandga votage

SCS3~SCS0

SCS3~SCS0

/D Convete

STRT EOCB ENDC VSS

/D Cock

÷ N

(N=0~7)

fSYS

SCKS~SCKS0

VDD

ENDC

SDOL

SDOH

N0N1

/D DataRegistes

DRFS

DCREF

SVRS1~SVRS0

VBG

N7

Note:AN0~AN7are internalorexternalsignal inputchannels, thedetailscanbefound in theSADC0register.

A/D Converter Structure

Rev. 1.00 84 i 1 01 Rev. 1.00 85 i 1 01



A/D Converter Register DescriptionOveralloperationof theA/Dconverter iscontrolledusing four registers.Areadonly registerpairexiststostoretheA/Dconverterdata12-bitvalue.Theremainingtworegisters,SADC0andSADC1,arecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.

Register NameBit

7 6 5 4 3 2 1 0SDOL (DRFS=0) D3 D D1 D0 — — — —SDOL (DRFS=1) D7 D D5 D4 D3 D D1 D0SDOH (DRFS=0) D11 D10 D9 D8 D7 D D5 D4SDOH (DRFS=1) — — — — D11 D10 D9 D8SDC0 STRT EOCB ENDC DRFS SCS3 SCS SCS1 SCS0SDC1 — — — SVRS1 SVRS0 SCKS SCKS1 SCKS0

A/D Converter Registers List

A/D Converter Data Registers – SADOL, SADOHAsthisdevicecontainsaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasSADOH,andalowbyteregister,knownasSADOL.After theconversionprocess takesplace, theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theSADC0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.

ADRFSSADOH SADOL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 D11 D10 D9 D8 D7 D D5 D4 D3 D D1 D0 0 0 0 0

1 0 0 0 0 D11 D10 D9 D8 D7 D D5 D4 D3 D D1 D0

A/D Data Registers

A/D Converter Control Registers – SADC0, SADC1TocontrolthefunctionandoperationoftheA/Dconverter,twocontrolregistersknownasSADC0andSADC1areprovided.These8-bit registersdefinefunctionssuchas theselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter,thedigitiseddataformat,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterendofconversionstatus.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachoftheexternalorinternalanalogsignalinputsmustberoutedtotheconverter.TheSACS3~SACS0bitsintheSADC0registerareusedtodeterminewhichexternalanalogchannelinputorinternalanalogsignalisselectedtobeconnectedtotheinternalA/Dconverter.

Therelevantpin-sharedfunctionselectionregisters,PAPS0andPAPS1,determinewhichpinsonI/OPortsareusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorconnectedtothepinwillbeautomaticallyremovedif thepinisselectedtobeanA/Dconverterinput.

Rev. 1.00 8 i 1 01 Rev. 1.00 87 i 1 01



• SADC0 Register

Bit 7 6 5 4 3 2 1 0Name STRT EOCB ENDC DRFS SCS3 SCS SCS1 SCS0R/W R/W R R/W R/W R/W R/W R/W R/WPOR 0 1 0 0 0 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:Start0→1:ResettheA/DconverterandsetEOCBto"1"

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.WhenthebitissethightheA/Dconverterwillbereset.

Bit6 EOCB:EndofA/Dconversionflag0:A/Dconversionended1:A/Dconversioninprogress

Thisreadonlyflagisusedtoindicatewhether theA/Dconversioniscompletedornot.WhentheEOCBflagisset to1, it indicatesthattheA/Dconversionprocessisrunning.Thebitwillbeclearedto0aftertheA/Dconversioniscomplete.

Bit5 ENADC:A/Dconverterfunctionenablecontrol0:Disable1:Enable

ThisbitcontrolstheA/Dinternalfunction.ThisbitshouldbesethightoenabletheA/Dconverter.Ifthebitissetlow,thentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.

Bit4 ADRFS:A/Dconverterdataformatselect0:A/Dconverterdataformat→SADOH=D[11:4];SADOL=D[3:0]1:A/Dconverterdataformat→SADOH=D[11:8];SADOL=D[7:0]

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.

Bit3~0 SACS3~SACS0:A/Dconverteranalogchannelinputselect0000:AN0–InternalOCP0circuitoutputOCPAO0signal0001:AN10010:Reserved0011:AN30100:AN40101:AN5–Highvoltagepowersupplydividedvoltage,VDET

0110:AN60111:AN71000:FromBandgap1001~1111:Undefined,theinputwillbefloatingifselected

• SADC1 Register

Bit 7 6 5 4 3 2 1 0Name — — — SVRS1 SVRS0 SCKS SCKS1 SCKS0R/W — — — R/W R/W R/W R/W R/WPOR — — — 0 0 0 0 0

Bit7~5 Unimplemented,readas"0"Bit4~3 SAVRS1~SAVRS0:A/Dconverterreferencevoltageselect

00:AVDD

01:ExternalADCREFpin10:AVDD

11:AVDD

Rev. 1.00 8 i 1 01 Rev. 1.00 87 i 1 01



Bit2~0 SACKS2~SACKS0:A/Dconversionclocksourceselect000:fSYS001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:fSYS/128

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.

A/D Converter OperationTheSTARTbitintheSADC0registerisusedtostarttheADconversion.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.TheEOCBbit in theSADC0register isused to indicatewhen theanalog todigitalconversionprocess is complete.Thisbitwillbeautomatically set to "0"by themicrocontroller after aconversioncyclehasended.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andif theinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternal interruptaddressforprocessing.If theA/Dinternal interrupt isdisabled,themicrocontrollercanbeusedtopolltheEOCBbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theSACKS2~SACKS0bitsintheSADC1register.AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYSandbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,asthesystemclockoperatesatafrequencyof8MHz,theSACKS2~SACKS0bitsshouldnotbesetto000,001or111.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/Dclockperiodwhichmayresult ininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)SACKS

[2:0]=000(fSYS)

SACKS[2:0]=001

(fSYS/2)

SACKS[2:0]=010

(fSYS/4)

SACKS[2:0]=011

(fSYS/8)

SACKS[2:0]=100(fSYS/16)

SACKS[2:0]=101(fSYS/32)

SACKS[2:0]=110(fSYS/64)

SACKS[2:0]=111(fSYS/128)

1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs *MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs *4MHz 50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs *8MHz 15ns * 50ns * 500ns 1μs 2μs 4μs 8μs 16μs *

1MHz 83ns * 17ns * 333ns * 7ns 1.33μs 2.67μs 5.33μs 10.67μs *1MHz .5ns * 15ns * 50ns * 500ns 1μs 2μs 4μs 8μs

A/D Clock Period ExamplesControlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theENADCbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheENADCbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedin the timingdiagram,mustbeallowedbeforeanA/Dconversionis initiated.EvenifnopinsareselectedforuseasA/Dinputs,iftheENADCbitishigh,thensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheENADCissetlowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

Rev. 1.00 88 i 1 01 Rev. 1.00 89 i 1 01



A/D Converter Reference VoltageThereferencevoltagesupplytotheA/Dconvertercanbesuppliedfromthepositivepowersupplypin,AVDD,orfromanexternalreferencesourcesuppliedonpinADCREF.ThedesiredselectionismadeusingtheSAVRS1andSAVRS0bitsintheSADC1register.AstheADCREFpinispin-sharedwithotherfunctions,whentheADCREFpinisselectedasthereferencevoltagesupplypin,therelatedpin-sharedselectionbitsshouldfirstbeproperlyconfiguredtoenabletheADCREFpinfunction.

A/D Converter Input SignalsAlltheexternalA/Danalogchannelinputpins,AN1,AN3,AN4,AN6andAN7,arepin-sharedwiththeI/Opinsaswellasotherfunctions.ThecorrespondingcontrolbitsforeachA/DexternalinputpininthePAPS0andPAPS1registerdeterminewhethertheinputpinsaresetupasA/Dconverteranalog inputsorwhether theyhaveother functions. If thepin issetup tobeasanA/Danalogchannelinput, theoriginalpinfunctionswillbedisabled.Inthisway,pinscanbechangedunderprogramcontrol tochangetheir functionbetweenA/Dinputsandotherfunctions.Allpullhighresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedif thepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputintheportcontrolregistertoenabletheA/Dinputaswhenthepin-sharedfunctioncontrolbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.ThereareinternalanalogsignalsderivedfromAN0–OverCurrentProtectionanalogoutputsignalOCPAO0,AN5–highvoltagepowersupplydetectionsignalVDETortheBandgapreferencevoltageVBG,whichcanbeconnectedto theA/Dconverteras theanaloginputsignalbyconfiguringtheSACS3~SACS0bits.TheA/Dconverterhasitsownreferencevoltagepin,ADCREF.However,thereferencevoltagecanbesuppliedfromthepowersupplypinortheexternalreferencevoltagepin,achoicewhichismadethroughtheSAVRS1~SAVRS0bits in theSADC1 register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueoftheselectedA/Dreferencevoltage.

Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforanexternalinputA/DconversionwhichisdefinedastADCarenecessary.Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKclockcycleswheretADCKisequaltotheA/Dclockperiod.

ENDC

STRT

EOCB

SCS[3:0]

off on off ontONST

tDS

/D saming timetDS

/D saming time

Stat of /D convesion Stat of /D convesion Stat of /D convesion

End of /D convesion

End of /D convesion

tDC/D convesion time



0011B 0010B 0000B 0001B

/D channe switch

A/D Conversion Timing

Rev. 1.00 88 i 1 01 Rev. 1.00 89 i 1 01



Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsSACKS2~SACKS0intheSADC1register.

• Step2EnabletheA/DbysettingtheENADCbitintheSADC0registertoone.

• Step3SelectwhichsignalistobeconnectedtotheinternalA/DconverterbycorrectlyconfiguringtheSACS3~SACS0bitsSelecttheexternalchannelinput,AN1,AN3,AN4,AN6orAN7,tobeconverted,gotoStep4.Selecttheinternalanalogsignal,AN0,AN5ortheBandgapreferencevoltage,tobeconverted,gotoStep5.

• Step4ThecorrespondingpinsshouldbeconfiguredasA/Dinputfunctionbyconfiguringtherelevantpin-sharedfunctioncontrolbits.Afterthisstep,gotoStep6.

• Step5SelectA/DconverteroutputdataformatbysettingtheADRFSbitintheSADC0register.

• Step6Select thereferencevoltagesourcebyconfiguring theSAVRS1~SAVRS0bits in theSADC1register.

• Step7IfA/Dconversioninterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconversioninterruptcontrolbit,ADE,mustbothbesethighinadvance.

• Step8TheA/DconversionprocedurecannowbeinitializedbysettingtheSTARTbit intheSADC0registerfromlowtohighandthenlowagain.

• Step9Tocheckwhentheanalogtodigitalconversionprocessiscomplete,theEOCBbitintheSADC0registercanbepolled.Theconversionprocessiscompletewhenthisbitgoeslow.WhenthisoccurstheA/DdataregistersSADOLandSADOHcanbereadtoobtaintheconversionvalue.Asanalternativemethod,iftheinterruptsareenabledandthestackisnotfull,theprogramcanwaitforanA/Dinterrupttooccur.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheEOCBbitintheSADC0registerisused,theinterruptenablestepabovecanbeomitted.

Rev. 1.00 90 i 1 01 Rev. 1.00 91 i 1 01



Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff toreducepowerconsumption,byclearingbitENADCto0 in theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Opins,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Conversion FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheactualA/Dconverterreferencevoltage,VREF,thisgivesasinglebitanaloginputvalueofVREFdividedby4096.

1LSB=VREF÷4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×(VREF÷4096)

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVREFlevel.NotethatheretheVREFvoltageistheactualA/DconverterreferencevoltagedeterminedbytheSAVRSfield.

FFFH

FFEH

FFDH

03H

0H

01H

0 1 3 4093 4094 4095 409

VREF409

Analog Input Voltage

A/D Conversion Result

1.5 LSB

0.5 LSB

（）

Ideal A/D Transfer Function

Rev. 1.00 90 i 1 01 Rev. 1.00 91 i 1 01



A/D Conversion Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheEOCBbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: Using an EOCB polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ;selectfSYS/8asA/Dclockset ENADCmov a,04h ;setupPAPS0toconfigurepinAN1mov PAPS1,amov a,21hmov SADC0,a ;enableandconnectAN1channeltoA/Dconverter:start_conversion:clr START ;highpulseonstartbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dpolling_EOC:sz EOCB ;polltheSADC0registerEOCBbittodetectendofA/Dconversionjmp polling_EOC ;continuepollingmov a,SADOL ;readlowbyteconversionresultvaluemov SADOL_buffer,a ;saveresulttouserdefinedregistermov a,SADOH ;readhighbyteconversionresultvaluemov SADOH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion ;startnextA/Dconversion

Rev. 1.00 9 i 1 01 Rev. 1.00 93 i 1 01



Example: Using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ;selectfSYS/8asA/Dclockset ENADCmov a,04h ;setupPAPS0toconfigurepinsAN1mov PAPS0,amov a,21hmov SADC0,a ;enableandconnectAN1channeltoA/Dconverterstart_conversion:clr START ;highpulseonSTARTbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dclr ADF ;clearADCinterruptrequestflagset ADE ; enable ADC interruptset EMI ;enableglobalinterrupt::; ADC interrupt service routineADC_ISR:mov acc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmov status_stack,a ;saveSTATUStouserdefinedmemory::mov a,SADOL ;readlowbyteconversionresultvaluemov SADOL_buffer,a ;saveresulttouserdefinedregistermov a,SADOH ;readhighbyteconversionresultvaluemov SADOH_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ;restoreSTATUSfromuserdefinedmemorymov a,acc_stack ;restoreACCfromuserdefinedmemoryreti

Rev. 1.00 9 i 1 01 Rev. 1.00 93 i 1 01



Operational Amplifier – OPAThedeviceincludesanoperationalamplifierwhichhasaninternalinputoffsetcalibrationfunctionandadjustablebandwidth.

OP0INPOP

+-

OP0OUTOP0INN

O0OF[5:0]O0OFM

OP0ENOP0BW[1:0]

O0RSP

Operational Amplifier Block Diagram

Operational Amplifier OperationTheoperationalamplifiercanadjustitsbandwidthandprovidesaninputoffsetcalibrationfunction.Thecalibrateddata isstoredinO0OF[5:0]bits.TheO0OFMiscalibrationmodecontrolbitandtheO0RSPisusedtoindicatetheinputreferencevoltagecomesfromOP0INPorOP0INNpinincalibrationmode.TheOP0INPandOP0INNpinsaretheoperationalamplifierpositiveandnegativeinputpairandtheOP0OUTistheoperationalamplifieranalogoutputvoltagepin.TheoperationalamplifierbandwidthcanbesetbyOP0BW[1:0].TheOP0ENbit isusedtoenableordisabletheoperationalamplifier.

Operational Amplifier RegistersTheOP0CandOP0VOSregisterscontroltheoveralloperationoftheoperationalamplifier,suchastheenableordisablecontrol,inputpathselectionandinputoffsetcalibration.

Register Name

Bit7 6 5 4 3 2 1 0

OP0C — OP0EN — — — — OP0BW1 OP0BW0OP0VOS O0OFM O0RSP O0OF5 O0OF4 O0OF3 O0OF O0OF1 O0OF0

Operational Amplifier Registers List

OP0C RegisterBit 7 6 5 4 3 2 1 0

Name — OP0EN — — — — OP0BW1 OP0BW0R/W — R/W — — — — R/W R/WPOR — 0 — — — — 0 0

Bit7 Unimplemented,readas"0"Bit6 OP0EN:Operationalamplifierenableordisablecontrol

0:Disable1:Enable

Bit5~2 Unimplemented,readas"0"Bit1~0 OP0BW1~OP0BW0:Operationalamplifierbandwidthcontrol

RefertotheA.C.Characteristicssectionforthedetailedinformationunderdifferentsettings.

Rev. 1.00 94 i 1 01 Rev. 1.00 95 i 1 01



OP0VOS RegisterBit 7 6 5 4 3 2 1 0

Name O0OFM O0RSP O0OF5 O0OF4 O0OF3 O0OF O0OF1 O0OF0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 0 0 0 0 0

Bit7 O0OFM:OperationalAmplifierNormalOperationorInputOffsetCalibrationModeselection0:NormalOperation1:InputOffsetCalibrationMode

Bit6 O0RSP:OperationalAmplifierInputOffsetVoltageCalibrationReferenceselection0:SelectnegativeinputOP0INNasthereferenceinput1:SelectpositiveinputOP0INPasthereferenceinput

Bit5~0 O0OF5~O0OF0:OperationalAmplifierInputOffsetVoltageCalibrationvalue

Operational Amplifier Input Offset CalibrationTheOperationalAmplifierprovidesinputoffsetcalibrationfunction.Tooperateintheinputoffsetcalibrationmodefor theOperationalAmplifier, theO0OFMbit in theOP0VOSregistershouldfirstbesetto"1"followedbythereferenceinputselectionbyconfiguringtheO0RSPbit.NotethatbecausetheOperationalAmplifierinputsarepin-sharedwithI/Opins,theyshouldbeconfiguredasOperationalAmplifierinputsfirst.

Foroperationalamplifierinputoffsetcalibration, theproceduresaresummarizedinthefollowingsteps.

Step1.SetO0OFM=1andconfigureO0RSP,theOperationalAmplifierwilloperateintheinputoffsetCalibrationmode.TomakesureVOSasminimiseaspossibleaftercalibration, theinputreferencevoltageincalibrationshouldbethesameasinputDCoperatingvoltageinnormaloperation.

Step2.SetO0OF[5:0]=000000andthenreadtheOP0OUTbit.

Step3.IncreasetheO0OF[5:0]valueby1andthenreadtheOP0OUTbit.IftheOP0OUTbitvaluehasnotchanged,thenrepeatStep3until theOP0OUTbitvaluehaschanged.IftheOP0OUTbitvaluehaschanged,recordtheO0OF[5:0]valueasVOS1andthengotoStep4.

Step4.SetO0OF[5:0]=111111andreadtheOP0OUTbit.

Step5.DecreasetheO0OF[5:0]valueby1andthenreadtheOP0OUTbit.IftheOP0OUTbitvaluehasnotchanged,thenrepeatStep5until theOP0OUTbitvaluehaschanged.IftheOP0OUTbitvaluehaschanged,recordtheO0OF[5:0]valueasVOS2andthengotoStep6.

Step6.RestoreO0OF[5:0]=VOS=(VOS1+VOS2)/2.TheoffsetCalibrationprocedureisnowfinished.If(VOS1+VOS2)/2isnotanintegerhendiscardthedecimal,whereVOS=VOUT-VIN.

Rev. 1.00 94 i 1 01 Rev. 1.00 95 i 1 01



Over Current Protection – OCPThedeviceincludesanovercurrentprotectionfunction.TheOCPdetectsaninputvoltagewhichisproportionaltothemonitoredsourcecurrent.IftheinputvoltageislargerthanthereferencevoltagesetbytheDAC,theOCPwillgenerateanoutputsignaltoindicatethatanovercurrenteventhasoccurred,andtriggersaninterrupttoinformtheMCU.

OCPI0

OCPAO0

OCPINT0(to OCP interrupt)

OCPCHY0S4

-

+

G20~G00

R2

OPA+

-

8 bit DAC

CPOUT0

Debounce

FLT20~FLT00R1(R1 = 4kΩ)

ENOCP10~ENOCP00

MUX

OCPDA0[7:0]OCPVS0

AVDD

OCP0REF

fSYS

S0

S1

S2

S3

CMP

OCPAO0(to A/D Converter)

OCPO0(to PTM0 PTP0I input)Pin

Control

OCPIS

Pin Control

PA6S[1:0]

Over Current Protection Circuit

Over Current Protection OperationTheOCPcircuit inputsignaloriginatesfromOCPI0, thesourceofwhichcanbeselectedbytheOCPISbit in theSSCTLregister.After this, fourswitchesS0~S3formamodeselectfunction.AnoperationalamplifierandtworesistorsformaPGAfunction.ThePGAgaincanbepositiveornegativedeterminedbytheinputvoltageconnectedtothepositiveornegativeinputofthePGA.The8-bitDACisusedtogenerateareferencevoltage.Thecomparatorcomparesthereferencevoltageandtheamplifiedoutputvoltage.FinallythecomparatoroutputCPOUT0isfilteredtogenerateaharddecisionsignalOCPINT0,ifanovercurrenteventoccurs,thesignalwilltriggeraninterrupttoinformtheMCU.

TheOCPO0signalisalsothede-bouncedversionofCPOUT0.ItcanbeinternallyconnectedtothePTP0IpinbythePT0ISbitandusedforcaptureinputfunctionofthePTM0.

TheOCPinputsignalamplifiedby internaloperationalamplifiercanbedirectlyoutputon theOCPAO0pin,andalsobe internallyconnected to theA/Dconverter inputAN0selectedby theSACS3~SACS0bitsintheSADC0registerfortheamplifiedinputvoltageread.

Over Current Protection RegistersTheOCPC00andOCPC10registersarecontrolregisterswhichusedtocontroltheOCPoperatingmodes, theOPAfunctionandde-bounce time.TheOCPDA0register isused tocontrolD/Aconverterreferencevoltage.TheOCPOCAL0andOCPCCAL0registersareusedtocancelouttheoperationalamplifierandcomparatorinputoffset.

Register Name

Bit7 6 5 4 3 2 1 0

SSCTL — — PT0IS OCPIS — — HXT_EX EN_VDETOCPC00 ENOCP10 ENOCP00 OCPVS0 OCPCHY0 — — — OCPO0OCPC10 — — G0 G10 G00 FLT0 FLT10 FLT00OCPD0 D7 D D5 D4 D3 D D1 D0

OCPOCL0 OOFM0 ORSP0 OOF50 OOF40 OOF30 OOF0 OOF10 OOF00OCPCCL0 CPOUT0 COFM0 CRSP0 COF40 COF30 COF0 COF10 COF00

Over Current Protection Registers List

Rev. 1.00 9 i 1 01 Rev. 1.00 97 i 1 01



SSCTL RegisterBit 7 6 5 4 3 2 1 0

Name — — PT0IS OCPIS — — HXT_EX EN_VDETR/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 PT0IS:PTP0Iinputsourcepinselection

0:FromPA01:FrominternalOCP0Osignal

Bit5 OCPIS:OCPI0inputsourcepinselection0:FromPD61:FromPD7

Bit3~2 Unimplemented,readas"0"Bit1 HXT_EX:HXTPWMoutputcontrol

Describedelsewhere.Bit0 EN_VDET:Highvoltagepowersupplydetectionfunctioncontrol

Describedelsewhere.

OCPC00 RegisterBit 7 6 5 4 3 2 1 0

Name ENOCP10 ENOCP00 OCPVS0 OCPCHY0 — — — OCPO0R/W R/W R/W R/W R/W — — — RPOR 0 0 0 0 — — — 0

Bit7~6 ENOCP10~ENOCP00:OCPfunctionoperatingmodeselection00:OCPfunctionisdisabled,S1andS3on,S0andS2off01:Non-invertingmode,S0andS3on,S1andS2off10:Invertingmode,S1andS2on,S0andS3off11:Calibrationmode,S1andS3on,S0andS2off

Note:Iftheovercurrentprotectionfunctionisdisabled,thisresultsintheoperationalamplifier,comparator,D/Aconverteranddebouncefunctionsallbeingswitchedoff,aswellasthecomparatoroutputandOCPAO0bothbeinglow.

Bit5 OCPVS0:OCPDACreferencevoltageselection0:FromAVDD

1:FromOCP0REFpinBit4 OCPCHY0:OCPComparatorhysteresisfunctioncontrol

0:Disable1:Enable

Bit3~1 Unimplemented,readas"0"Bit0 OCPO0:OCPdigitaloutputbit

0:Themonitoredsourcecurrentisnotover1:Themonitoredsourcecurrentisover

Rev. 1.00 9 i 1 01 Rev. 1.00 97 i 1 01



OCPC10 RegisterBit 7 6 5 4 3 2 1 0

Name — — G0 G10 G00 FLT0 FLT10 FLT00R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5~3 G20~G00:PGAR2/R1ratioselection,itwilldefinePGAgainininverting/non-invertingmode

000:Unitygainbuffer(non-invertingmode)orR2/R1=1(invertingmode)001:R2/R1=5010:R2/R1=10011:R2/R1=15100:R2/R1=20101:R2/R1=30110:R2/R1=40111:R2/R1=50

Bit2~0 FLT20~FLT00:OCPoutputfilterdebouncetimeselection000:Bypass,withoutdebounce001:(1~2)×tDEB

010:(3~4)×tDEB

011:(7~8)×tDEB

100:(15~16)×tDEB

101:(31~32)×tDEB

110:(63~64)×tDEB111:(127~128)×tDEB

Note:tDEB=1/fSYS

OCPDA0 RegisterBit 7 6 5 4 3 2 1 0


Bit7~0 D7~D0:OCPDACoutputvoltagecontrolbitsOCPDACOutput=(DACreferencevoltage/256)×N,N=OCPDA0[7:0]

OCPOCAL0 RegisterBit 7 6 5 4 3 2 1 0

Name OOFM0 ORSP0 OOF50 OOF40 OOF30 OOF0 OOF10 OOF00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 0 0 0 0 0

Bit7 OOFM0:OCPOperationalAmplifierNormalOperationorInputOffsetCalibrationModeselection0:NormalOperation1:InputOffsetCalibrationMode

Bit6 ORSP0:OCPOperationalAmplifierInputOffsetVoltageCalibrationReferenceselection0:Selectnegativeinputasthereferenceinput1:Selectpositiveinputasthereferenceinput

Bit5~0 OOF50~OOF00:OCPOperationalAmplifierInputOffsetVoltageCalibrationvalue

Rev. 1.00 98 i 1 01 Rev. 1.00 99 i 1 01



OCPCCAL0 RegisterBit 7 6 5 4 3 2 1 0

Name CPOUT0 COFM0 CRSP0 COF40 COF30 COF0 COF10 COF00R/W R R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 1 0 0 0 0

Bit7 CPOUT0:OCPComparatorOutput,positivelogic(readonly)Bit6 COFM0:OCPComparatorNormalOperationorInputOffsetCalibrationModeselection

0:NormalOperation1:InputOffsetCalibrationMode

Bit5 CRSP0:OCPComparatorInputOffsetCalibrationReferenceInputselect0:Selectnegativeinputasthereferenceinput1:Selectpositiveinputasthereferenceinput

Bit4~0 COF40~COF00:OCPComparatorInputOffsetCalibrationvalue

Input Voltage RangeTogetherwithdifferentPGAoperatingmodes,theinputvoltageontheOCPpincanbepositiveornegativeforflexibleoperation.

• ForVIN>0,thePGAoperatesinthenon-invertingmodeandtheoutputvoltageofthePGAis:VOPGA=(1+R2/R1)×VIN(2)

• WhenthePGAoperatesinthenon-invertingmode,italsoprovidesaunitygainbufferfunction.IfENOCP10~ENOCP00=01andG20~G00=000, thePGAgainwillbe1and thePGA isconfiguredasaunitygainbuffer.TheswitchesS2andS3willbeoffinternallyandtheoutputvoltageofthePGAis:

VOPGA=VIN(3)

• For0>VIN>-0.4V,thePGAoperatesintheinvertingmode,theoutputvoltageofthePGAis:VOPGA=-(R2/R1)×VIN(4)

Note:IfVINisnegative,itcannotbelowerthan-0.4Vwhichwillresultincurrentleakage.

Offset CalibrationTheOCPcircuithas4operatingmodescontrolledbyENOCP10~ENOCP00,oneofthemiscalibrationmode.Incalibrationmode,theoperationalamplifierandcomparatoroffsetcanbecalibrated.

OCP Operational Amplifier CalibrationStep1.SetENOCP10~ENOCP00=11andOOFM0=1, theOCPwilloperate in theoperational

amplifierinputoffsetCalibrationmode.

Step2.SetOOF50~OOF00=000000andthenreadtheCPOUT0bit.

Step3.LetOOF50~OOF00=OOF50~OOF00+1andthenreadtheCPOUT0bit.IftheCPOUT0bithasnotchanged,thenrepeatStep3untiltheCPOUT0bithaschanged.If theCPOUT0bithaschanged,recordtheOOF50~OOF00valueasVOS1andthengotoStep4.

Step4.SetOOF50~OOF00=111111andreadtheCPOUT0bit.

Step5.LetOOF50~OOF00=OOF50~OOF00-1andthenreadtheCPOUT0bit.IftheCPOUT0bithasnotchanged,thenrepeatStep5untiltheCPOUT0bithaschanged.If theCPOUT0bithaschanged,recordtheOOF50~OOF00valueasVOS2andthengotoStep6.

Step6.RestoreOOF50~OOF00=VOS=(VOS1+VOS2)/2, theoffsetCalibrationprocedure isnowfinished.

Rev. 1.00 98 i 1 01 Rev. 1.00 99 i 1 01



OCP Comparator Calibration Step1.SetENOCP10~ENOCP00=11andCOFM0=1,theOCPwillnowoperateinthecomparator

inputoffsetcalibrationmode.

Step2.SetCOF40~COF00=00000andreadtheCPOUT0bit.

Step3.LetCOF40~COF00=COF40~COF00+1andthenreadtheCPOUT0bit.IftheCPOUT0bithasnotchanged,thenrepeatStep3untiltheCPOUT0bithaschanged.If theCPOUT0bithaschanged,recordtheCOF40~COF00valueasVOS1andthengotoStep4.

Step4.SetCOF40~COF00=11111andthenreadtheCPOUT0bit.

Step5.LetCOF40~COF00=COF40~COF00-1andthenreadtheCPOUT0bit.IftheCPOUT0bithasnotchanged,thenrepeatStep5untiltheCPOUT0bithaschanged.If theCPOUT0bithaschanged,recordtheCOF40~COF00valueasVOS2andthengotoStep6.

Step6.RestoreCOF40~COF00=VOS=(VOS1+VOS2)/2, theoffsetCalibrationprocedure isnowfinished.

Rev. 1.00 100 i 1 01 Rev. 1.00 101 i 1 01



High Voltage DriverThedeviceincludesahighvoltagedriverfunction,whichiscomposedof twosections, thehighvoltagedrivercontrolandthehighvoltagedrivercombination.

High Voltage Driver Control

High Voltage Driver Combination

VDD

VSS

VCC1

VSS1

OUT0

OUT1

GT0

GB0

GT1

GB1

GLT0

GLB0

Mistake-Proof CKT

LevelShift

GLT1

GLB1

Mistake-Proof CKT

LevelShift

Total × 2 Sets

Thermal Protection CKT THSO

PDN

PWM AlignCKT

OCPCKT

Dead-Time CKT

Mistake-Proof CKT

Polarity CKT

Total × 2 Sets

OCPO0

PWM0T

PWM0B

PDH0TPDH0B

IO0T

IO0B

GT0

GB0

GT1

GB1

PWM0

PWM1

PMS0[1:0]

PRT0TPRT0B

PSS0

DTS0[7:0]

POS0TPOS0B

PWM AlignCKT

OCPCKT

Dead-Time CKT

Mistake-Proof CKT

Polarity CKT

PWM1T

PWM1B

PDH1TPDH1B

IO1T

IO1B

PMS1[1:0]

PRT1TPRT1B

PSS1

DTS1[7:0]

POS1TPOS1B

OCPO0

THS_EN

VDD VCC1

VDD

VSS VSS1

VSS

Rs

OCP0

SELOCPO0

ADC

PSS PMSL DTS0DTS1 POSL

High Voltage Driver Structure

Rev. 1.00 100 i 1 01 Rev. 1.00 101 i 1 01



High Voltage Driver ControlTherearetwogroupsofhighvoltagedrivercontrolcircuits.Eachgroupiscomposedoffivecircuits,PWMaligncircuit,overcurrentprotectioncircuit,deadtimecontrolcircuit,mistake-proofcircuitandpolaritycontrolcircuit.

High Voltage DriverControl

PWMignCKT

OCPCKT

Dead-Time CKT

Mistake-Poof CKT

Poaity CKT

Total × 2 Sets

OCPO0

PWM0T

PWM0B

PDH0TPDH0B

IO0T

IO0B

GT0

GB0

GT1

GB1

PWM0

PWM1

PMS0[1:0]

PRT0TPRT0B

PSS0

DTS0[7:0]

POS0TPOS0B

PWMignCKT

OCPCKT

Dead-Time CKT

Mistake-Poof CKT

PoaityCKT

PWM1T

PWM1B

PDH1TPDH1B

IO1T

IO1B

PMS1[1:0]

PRT1TPRT1B

PSS1

DTS1[7:0]

POS1TPOS1B

OCPO0

PSS[1:0]

PMSL[3:0]

DTS0[7:0]DTS1[7:0]

POSL[3:0]

Note:PWM0standsfor thePWMoutputsignalfromPTP2of thePTM2.PWM1standsfor thePWMoutputsignalfromPTP3ofthePTM3.

Rev. 1.00 10 i 1 01 Rev. 1.00 103 i 1 01



High Voltage Driver Control RegistersThehighvoltagedrivercontrolisimplementedusingseveralregisters.TheseregistersareusedtoselectthePWMinputsource,thePWMalignmode,enableordisabletheovercurrentprotectionfunction,setupthedeadtimeandcontroltheoutputpolarity,etc.

Register Name

Bit7 6 5 4 3 2 1 0

PSS — — — — — — PSS1 PSS0PMSL — — — — PMS11 PMS10 PMS01 PMS00

PDHCL — — — — PDH1T PDH1B PDH0T PDH0BDTS0 DT0CKS1 DT0CKS0 DT0E DT0D4 DT0D3 DT0D DT0D1 DT0D0DTS1 DT1CKS1 DT1CKS0 DT1E DT1D4 DT1D3 DT1D DT1D1 DT1D0POSL — — — — POS1T POS1B POS0T POS0BPRTL — — — — PRT1T PRT1B PRT0T PRT0BOPCL — — — — OCPTE1 — OCPTE0 —RPDH — — — — — — RPDH1 RPDH0

High Voltage Driver Control Registers List

PSS RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — PSS1 PSS0R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1 PSS1:SelectPWMSourceforOUT1HighVoltageLevelShiftDriver

0:PWMsourcefromPTM2output1:PWMsourcefromPTM3output

Bit0 PSS0:SelectPWMSourceforOUT0HighVoltageLevelShiftDriver0:PWMsourcefromPTM2output1:PWMsourcefromPTM3output

PMSL RegisterBit 7 6 5 4 3 2 1 0

Name — — — — PMS11 PMS10 PMS01 PMS00R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 PMS11~PMS10:SelectthePWMalignmodeofOUT1highvoltagelevelshiftdriver

00:ComplementaryPWMsignalpair01:Topsidenon-complementaryPWMsignal10:Bottomsidenon-complementaryPWMsignal11:I/Otypecontrol(PDH1T~PDH1Bcontroltop/bottomsidesrespectively)

Bit1~0 PMS01~PMS00:SelectthePWMalignmodeofOUT0highvoltagelevelshiftdriver00:ComplementaryPWMsignalpair01:Topsidenon-complementaryPWMsignal10:Bottomsidenon-complementaryPWMsignal11:I/Otypecontrol(PDH0T~PDH0Bcontroltop/bottomsidesrespectively)

Rev. 1.00 10 i 1 01 Rev. 1.00 103 i 1 01



PDHCL RegisterBit 7 6 5 4 3 2 1 0

Name — — — — PDH1T PDH1B PDH0T PDH0BR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 PDH1T~PDH1B:ControltheTop/BottomoutputsoftheOUT1highvoltagelevel

shiftdriver00:Top/Bottomturnoff01:Topturnoff/Bottomturnon,outputlow10:Topturnon/Bottomturnoff,outputhigh11:Top/Bottomturnoff(Top/Bottomturnonisforbidden)

Bit1~0 PDH0T~PDH0B:ControltheTop/BottomoutputsoftheOUT0highvoltagelevelshiftdriver00:Top/Bottomturnoff01:Topturnoff/Bottomturnon,outputlow10:Topturnon/Bottomturnoff,outputhigh11:Top/Bottomturnoff(Top/Bottomturnonisforbidden)

OPCL RegisterBit 7 6 5 4 3 2 1 0

Name — — — — OCPTE1 — OCPTE0 —R/W — — — — R/W — R/W —POR — — — — 0 — 0 —

Bit7~4 Unimplemented,readas"0"Bit3 OCPTE1:OvercurrentprotectionfunctionenablecontroloftheOUT1highvoltage

levelshiftdriver0:Disable1:Enable

Whenthebit ishigh,theovercurrentprotectionfunctionoftheOUT1highvoltagelevelshiftdriverwillbeenabled,ifanovercurrentconditionoccurs,theTop/BottomoutputswillbecontrolledbythePRT1T~PRT1Bbits.

Bit2 Unimplemented,readas"0"Bit1 OCPTE0:OvercurrentprotectionfunctionenablecontroloftheOUT0highvoltage

levelshiftdriver0:Disable1:Enable

Whenthebit ishigh,theovercurrentprotectionfunctionoftheOUT0highvoltagelevelshiftdriverwillbeenabled,ifanovercurrentconditionoccurs,theTop/BottomoutputswillbecontrolledbythePRT0T~PRT0Bbits.

Bit0 Unimplemented,readas"0"

Rev. 1.00 104 i 1 01 Rev. 1.00 105 i 1 01



PRTL RegisterBit 7 6 5 4 3 2 1 0

Name — — — — PRT1T PRT1B PRT0T PRT0BR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3~2 PRT1T~PRT1B:ControltheTop/BottomGateoutputsoftheOUT1/PDH1whenan

overcurrentconditionoccurs00:Top/Bottomturnoff01:Topturnoff/Bottomturnon,outputlow10:Topturnon/Bottomturnoff,outputhigh11:Top/Bottomturnoff

Thesebitsareavailableonlywhentheovercurrentprotectioncircuitof theOUT1highvoltagelevelshiftdriverisenabledbysettingtheOCPTE1bithigh.

Bit1~0 PRT0T~PRT0B:ControltheTop/BottomGateoutputsoftheOUT0/PDH0whenanovercurrentconditionoccurs00:Top/Bottomturnoff01:Topturnoff/Bottomturnon,outputlow10:Topturnon/Bottomturnoff,outputhigh11:Top/Bottomturnoff

Thesebitsareavailableonlywhentheovercurrentprotectioncircuitof theOUT0highvoltagelevelshiftdriverisenabledbysettingtheOCPTE0bithigh.

DTS1 RegisterBit 7 6 5 4 3 2 1 0

Name DT1CKS1 DT1CKS0 DT1E DT1D4 DT1D3 DT1D DT1D1 DT1D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 DT1CKS1~DT1CKS0:Deadtimeclocksource(fDT1)selectionoftheOUT1highvoltagelevelshiftdriver00:fDT1=fSYS01:fDT1=fSYS/210:fDT1=fSYS/411:fDT1=fSYS/8

Bit5 DT1E:DeadtimeinsertioncontroloftheOUT1highvoltagelevelshiftdriver0:Nodeadtimeinsertion1:Deadtimeinsertion

If thisbit issethigh toenable thedead time insertion, thedead time is furtherlycontrolledbytheDT1D4~DT1D0bits.

Bit4~0 DT1D4~DT1D0:DeadtimecounterfordeadtimeunitoftheOUT1highvoltagelevelshiftdriverDeadtime=(DT1D[4:0]+1)/fDT1

Rev. 1.00 104 i 1 01 Rev. 1.00 105 i 1 01



DTS0 RegisterBit 7 6 5 4 3 2 1 0

Name DT0CKS1 DT0CKS0 DT0E DT0D4 DT0D3 DT0D DT0D1 DT0D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 DT0CKS1~DT0CKS0:Deadtimeclocksource(fDT0)selectionoftheOUT0highvoltagelevelshiftdriver00:fDT0=fSYS01:fDT0=fSYS/210:fDT0=fSYS/411:fDT0=fSYS/8

Bit5 DT0E:DeadtimeinsertioncontroloftheOUT0highvoltagelevelshiftdriver0:Nodeadtimeinsertion1:Deadtimeinsertion

If thisbit issethigh toenable thedead time insertion, thedead time is furtherlycontrolledbytheDT0D4~DT0D0bits.

Bit4~0 DT0D4~DT0D0:DeadtimecounterfordeadtimeunitoftheOUT0highvoltagelevelshiftdriverDeadtime=(DT0D[4:0]+1)/fDT0

POSL RegisterBit 7 6 5 4 3 2 1 0

Name — — — — POS1T POS1B POS0T POS0BR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas"0"Bit3 POS1T:SelecttheToppolaritytheOUT1highvoltagelevelshiftdriver

0:Non-inverted1:Inverted

Bit2 POS1B:SelecttheBottompolarityoftheOUT1highvoltagelevelshiftdriver0:Non-inverted1:Inverted

Bit1 POS0T:SelecttheToppolaritytheOUT0highvoltagelevelshiftdriver0:Non-inverted1:Inverted

Bit0 POS0B:SelecttheBottompolarityoftheOUT0highvoltagelevelshiftdriver0:Non-inverted1:Inverted

RPDH RegisterBit 7 6 5 4 3 2 1 0

Name — — — — — — RPDH1 RPDH0R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas"0"Bit1 RPDH1:PDH1/OUT1highvoltageoutputstatusreadbacksignal

0:Low1:High

Bit0 RPDH0:PDH0/OUT0highvoltageoutputstatusreadbacksignal0:Low1:High

Rev. 1.00 10 i 1 01 Rev. 1.00 107 i 1 01



Dead TimeDuringthetransitionoftheexternaldrivingtransistors,theremaybeamomentwhenboththetopandbottomsidesaresimultaneouslyon,whichwillresultinamomentaryshortcircuit.Toavoidthissituation,adeadtimecanbeinserted.Thedeadtimeshouldbeconfiguredwitharangeof0.3μs~5μs.ItsdurationisdeterminedbytheDTS0~DTS1registers.

The followingshows thedead time insertion timing.Note thatafter thedead timefunction isenabled,itisinsertedateachrisingedgeonly,thefallingedgesremainunchanged.

T0 B0

Dead-TimeInsetion

Dead-TimeInsetion

Dead-TimeInsetion

T1 B1

Dead Time Insertion Timing

Mistake-Proof for the High Voltage Driver ControlIncorrectwriteoperationsorexternal factorssuchanESDcondition,maycause incorrecton/offcontrol resulting in the topandbottomsidesofexternal transistorsbeingboth turnedonsimultaneously.Amistake-proofcircuit isprovidedtoavoidsuchsituationsbyforcingboth theoutputMOStransistorstoanoffstatetoprotectthemotor.

Mistake-PoofCKT

GTXI

GBXI

GTXO

GBXO

GTXI GBXI GTXO GBXO0 0 0 00 1 0 11 0 1 01 1 0 0

Note:0meansMOSoff,1meansMOSon.TheexternalMOSgateoutputstatusisdeterminedbythePolarityControlcircuit,andwhether theoutput is invertedornot iscontrolledbythePOSLregister.

Rev. 1.00 10 i 1 01 Rev. 1.00 107 i 1 01



High Voltage Output Read BackTheactualoutputstatusonthePDHn/OUTnpincanbereadbackusingtheRPDH1~RPDH0bits.

HighVotageDive

LeveShiftRPDHn

PDHn

VCC1

High Voltage Driver CombinationThehighvoltagedrivercombinationcontains twogroupsofhighvoltagedrivingcircuits.Eachgroupismainlycomposedofamistake-proofcircuit,alevelshiftcircuitandathermalprotectioncircuit.Withthetwointegrated12Vhighvoltageprocesslevelshiftcircuits,thehighvoltagedrivercombinationprovides twooutput lines,OUT0~OUT1,whichcanbeusedfordrivingdifferentpolarityoutputsof theDCMotorDriverTopside(PMOS)orBottomside(NMOS) tosupportmultiplieexternaldrivingcircuits.

High Voltage Driver Combination

VDD

VSS

VCC1

VSS1

OUT0

OUT1

GT0

GB0

GT1

GB1

GLT0

GLB0

Mistake-PoofCKT

LeveShift

GLT1

GLB1

LeveShift

Total × 2 Sets

Thema Potection CKT THSOTHS_EN

PDN

Mistake-PoofCKT

High Voltage Driver Combination Block Diagram

Rev. 1.00 108 i 1 01 Rev. 1.00 109 i 1 01



High Voltage Driver Combination RegistersTheoveralloperationofthehighvoltagedrivercombinationiscontrolledusingtheHVCregister.Theregistercontrolsthehighvoltagedrivercombinationenableanddisableoperationandsetupsathermalprotectionfunction.

• HVC Register

Bit 7 6 5 4 3 2 1 0Name PDN THS_EN THSO — — — — —R/W R/W R/W R — — — — —POR 0 0 0 — — — — —

Bit7 PDN:Highvoltagedrivercombinationcircuiton/offcontrol0:On1:Off

Bit6 THS_EN:Thermalprotectionfunctionenable/disablecontrol0:Disable,nothermalprotection1:Enable,hasthermalprotection

Bit5 THSO:Thermalprotectionflag0:Nooverthermalcoditionoccurs1:Overthermalconditionoccurs

Bit4 Unimplemented,readas"0"Bit3~0 Reservedbits,thesebitsshouldbekeptlow.

High Voltage Driver Combination ApplicationsThehighvoltagedrivercombinationcircuitsareavailableforavarietyofapplicationsaccordingtodifferentproductrequirements.Theycandrivedifferentexternalcomponentsusingdifferentdrivingcurrents.EachPMOSorNMOShas its individualswitch,so thatavarietyofcombinationsareallowed.Thefollowingaretwoexamples.

• H-BridgeGroup:DirectlydrivetheDCMotor

GT0

GB0

HO0

GT1

GB1

HO1

M

• PMOS/NMOSusedindependently

GT0

GB0

GT1

GB1

OUT0 OUT1

Rev. 1.00 108 i 1 01 Rev. 1.00 109 i 1 01



Mistake-Proof for the High Voltage Driver CombinationIncorrectwriteoperationsorexternal factorssuchanESDcondition,maycause incorrecton/off control resulting in the topandbottomsidesof external transistorbeingboth turnedonsimultaneously.Amistake-proofcircuitisprovidedtoavoidsuchsituation.

Mistake-PoofCKT

HTXI

HBXI

HTXO

HBXO

HTXI HBXI HTXO HBXO PDHn0 0 0 0 00 1 0 1 01 0 1 0 11 1 0 1 0

Note:0meansMOSoff,1meansMOSon.

High Voltage Driver Combination Operation and Thermal ProtectionTheon/offfunctionofthewholehighvoltagedrivercombinationcircuitiscontrolledusingthePDNbitintheHVCregister.ThecircuitcanbepoweredonbyclearingthePDNbittozero,andpoweredoffbysetting thePDNbithigh.Thehighvoltagedrivercombinationcircuitcontainsa thermalprotectionfunction.TheTHS_ENbit isusedtoenableordisablethethermalprotectionfunction.TheTHSObit isused tomonitor temperatureconditions, if the temperatureexceeds thepresetrange,thebitwillchangefrom0to1toindicateanoverthermaloccurrence.

Ifthethermalprotectionhasbeenenabled,theTHSObitintheHVCregistercanbeusedtocheckwhetheranover thermalconditionhasoccurred.TheTHSObithasan initialvalueof0. If thedetectedtemperatureexceedsthepresetvalue,thebitwillbeautomaticallysetto1.Additionally,thethermalprotectionflagintheinterruptcontrolregisterwillalsobesethigh,ifthecorrespondinginterrupthasbeenenabled,athermalprotectioninterruptwillbegeneratedtoinformtheMCU.

Rev. 1.00 110 i 1 01 Rev. 1.00 111 i 1 01



High Voltage Power Supply DetectionThedeviceprovidesahighvoltagepowersupplydetectioncircuitforthehighvoltagefunction.TheVCC1powersupplydetectionfunctionisenabledordisabledbytheEN_VDETbit.Thisdetectioncircuitcanoutputapowersupplydividedvoltageusingdividerresistors.Thisdividedvoltage,VDET,canalsobereadbyconnectingittotheA/DconverterastheinternalinputsignalAN5.

VCC1

VSS1

DCN5

R1

R

EN_VDET

VDD/VDD

VDD/VDD

VDET

Note:R1:R2=4:1(12K/3K),VDET=R2/(R1+R2)×VCC1=0.2VCC1.VCC1 Power Supply Detection Circuit

Rev. 1.00 110 i 1 01 Rev. 1.00 111 i 1 01



I2C InterfaceThe I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

Device Save

Device Maste

DeviceSave

VDD

SDSCL

I2C Master/Slave Bus Connection

I2C Interface OperationTheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.Asmanydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it is themasterdevice thathasoverallcontrolof thebus.For thisdevice,whichonlyoperatesinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.

It is suggested that theuser shouldnot allow thedevice to enter IDLEorSLEEPmodebyapplicationprogramduringprocessingI2Ccommunication.

IfthepinisconfiguredtoSDAorSCLfunctionofI2Cinterface,thepinisconfiguredtoopen-collectInput/OutputportanditsPull-highfunctioncanbeenabledbyprogrammingtherelatedGenericPull-highControlRegister.

STRT signa fom Maste

Send save addessand R/W bit fom Maste

cknowedge fom save

Send data byte fom Maste

cknowedge fom save

STOP signa fom Maste

Rev. 1.00 11 i 1 01 Rev. 1.00 113 i 1 01



Shift Registe

Tansmit/Receive

Conto Unit

fSYS

fSUB

Data Bus

IC ddess Registe(IIC)

IC Data Registe(IICD)

ddess Comaato

Read/Wite Save IICSRWBit

Detect Stat o Sto

Time-outConto ICTOF

ddess MatchIC Inteut

DebounceCicuity

SCL Pin

MUX IICTXK

Data out

ICTOEN

ddess Match

ICDBNC1&

ICDBNC

SD PinData in

Diection Conto

IICHTX Bit

8-bit Data Comete

ICTOF bit

IICHCF Bit

IICHBB Bit

IICHS Bit

I2C Block Diagram

TheI2CDBNC1andI2CDBNC0bitsdeterminethedebouncetimeoftheI2Cinterface.Thisusesthesystemclockto ineffectaddadebouncetimeto theexternalclocktoreducethepossibilityofglitchesontheclocklinecausingerroneousoperation.Thedebouncetime, ifselected,canbechosen tobeeither2or4systemclocks.Toachieve therequiredI2Cdata transferspeed, thereexistsarelationshipbetweenthesystemclock,fSYS,andtheI2Cdebouncetime.ForeithertheI2CStandardorFastmodeoperation,usersmusttakecareoftheselectedsystemclockfrequencyandtheconfigureddebouncetimetomatchthecriterionshowninthefollowingtable.

I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz)No Debounce fSYS > MHz fSYS > 5 MHz

system cock debounce fSYS > 4 MHz fSYS > 10 MHz4 system cock debounce fSYS > 8 MHz fSYS > 0 MHz

I2C Minimum fSYS Frequency

I2C RegistersTherearefourcontrolregistersassociatedwiththeI2Cbus,IICC0,IICC1,IICAandI2CTOC,andonedataregister,IICD.Furtherexplanationoneachofthebitsisgivenbelow.TheI2CTOCregisterisdescribedintheI2CTime-outControlsection.

Register Name

Bit7 6 5 4 3 2 1 0

IICC0 — — — — ICDBNC1 ICDBNC0 IICEN —IICC1 IICHCF IICHS IICHBB IICHTX IICTXK IICSRW IICRNIC IICRXKIICD IICDD7 IICDD IICDD5 IICDD4 IICDD3 IICDD IICDD1 IICDD0IIC IIC IIC5 IIC4 IIC3 IIC IIC1 IIC0 —

ICTOC ICTOEN ICTOF ICTOS5 ICTOS4 ICTOS3 ICTOS ICTOS1 ICTOS0

I2C Registers List

TherearetwocontrolregistersfortheI2Cinterface,IICC0andIICC1.TheregisterIICC0isusedforI2Ccommunicationsettings.TheIICC1registercontainstherelevantflagswhichareusedtoindicatetheI2Ccommunicationstatus.

Rev. 1.00 11 i 1 01 Rev. 1.00 113 i 1 01



IICC0 RegisterBit 7 6 5 4 3 2 1 0

Name — — — — ICDBNC1 ICDBNC0 IICEN —R/W — — — — R/W R/W R/W —POR — — — — 0 0 0 —

Bit7~4 Unimplemented,readas"0"Bit3~2 I2CDBNC1~I2CDBNC0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclockdebounce10:4systemclockdebounce11:4systemclockdebounce

Bit1 IICEN:I2Cenable0:Disable1:Enable


IICC1 Register Bit 7 6 5 4 3 2 1 0

Name IICHCF IICHS IICHBB IICHTX IICTXK IICSRW IICRNIC IICRXKR/W R R R R/W R/W R R/W RPOR 1 0 0 0 0 0 0 1

Bit7 IICHCF:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheIICHCFflagis thedatatransferflag.Thisflagwillbezerowhendataisbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.Belowisanexampleoftheflowofatwo-byteI2Cdatatransfer.First,I2CslavedevicereceiveastartsignalfromI2CmasterandthenIICHCFbit isautomaticallyclearedtozero.Second,I2Cslavedevicefinishreceivingthe1stdatabyteandthenIICHCFbit isautomaticallysettoone.Third,userreadthe1stdatabytefromIICDregisterbytheapplicationprogramandthenIICHCFbitisautomaticallyclearedtozero.Fourth, I2Cslavedevicefinishreceiving the2nddatabyteandthenIICHCFbit isautomaticallysettooneandsoon.Finally,I2CslavedevicereceiveastopsignalfromI2CmasterandthenIICHCFbitisautomaticallysettoone.

Bit6 IICHAAS:I2CBusaddressmatchflag0:Notaddressmatch1:Addressmatch

TheIICHAASflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthenthisbitwillbehigh,ifthereisnomatchthentheflagwillbelow.

Bit5 IICHBB:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheIICHBBflagistheI2Cbusyflag.Thisflagwillbe"1"whentheI2CbusisbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto"0"whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Rev. 1.00 114 i 1 01 Rev. 1.00 115 i 1 01



Bit4 IICHTX:SelectI2Cslavedeviceistransmitterorreceiver0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 IICTXAK:I2CBustransmitacknowledgeflag0:Slavesendacknowledgeflag1:Slavedonotsendacknowledgeflag

TheIICTXAKbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitsofdata, thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetIICTXAKbit to"0"beforefurtherdataisreceived.

Bit2 IICSRW:I2CSlaveRead/Writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheIICSRWflag is the I2CSlaveRead/Write flag.This flagdetermineswhetherthemasterdevicewishes to transmitor receivedata fromthe I2Cbus.When thetransmittedaddressandslaveaddressismatch,thatiswhentheIICHAASflagissethigh,theslavedevicewillchecktheIICSRWflagtodeterminewhetheritshouldbeintransmitmodeorreceivemode.IftheIICSRWflagishigh,themasterisrequestingtoreaddatafromthebus,sotheslavedeviceshouldbeintransmitmode.WhentheIICSRWflagiszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 IICRNIC:I2CAddressMatchWakeUpControl0:Disable1:Enable

Thisbitshouldbesetto1toenabletheI2CaddressmatchwakeupfromtheSLEEPorIDLEMode.IftheIICRNICbithasbeensetbeforeenteringeithertheSLEEPorIDLEmodetoenabletheI2Caddressmatchwakeup,thenthisbitmustbeclearedbytheapplicationprogramafterwake-uptoensurecorrectiondeviceoperation.

Bit0 IICRXAK:I2CBusReceiveacknowledgeflag0:Slavereceiveacknowledgeflag1:Slavedonotreceiveacknowledgeflag

TheIICRXAKflagisthereceiveracknowledgeflag.WhentheIICRXAKflagis"0",itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedevice in the transmitmode, theslavedevicecheckstheIICRXAKflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.TheslavetransmitterwillthereforecontinuesendingoutdatauntiltheIICRXAKflagis"1".Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

Rev. 1.00 114 i 1 01 Rev. 1.00 115 i 1 01



TheIICDregisterisusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheIICDregister.AfterthedataisreceivedfromtheI2Cbus,themicrocontrollercanreaditfromtheIICDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheIICDregister.

IID RegisterBit 7 6 5 4 3 2 1 0

Name IICDD7 IICDD IICDD5 IICDD4 IICDD3 IICDD IICDD1 IICDD0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

"x": unknownBit7~0 IICDD7~IICDD0:I2CDataBufferbit7~bit0

TheIICAregisteristhelocationwherethe7-bitslaveaddressoftheslavedeviceisstored.Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheIICAregister,theslavedevicewillbeselected.

IIA RegisterBit 7 6 5 4 3 2 1 0

Name IIC IIC5 IIC4 IIC3 IIC IIC1 IIC0 —R/W R/W R/W R/W R/W R/W R/W R/W —POR 0 0 0 0 0 0 0 —

Bit7~1 IICA6~IICA0:I2CslaveaddressIICA6~IICA0is theI2Cslaveaddressbit6~bit0.Bits7~1of theIICAregisterdefinethedeviceslaveaddress.Bit0isnotdefined.Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheIICAregister,theslavedevicewillbeselected.


Rev. 1.00 11 i 1 01 Rev. 1.00 117 i 1 01



I2C Bus Communication CommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignal isplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress,theIICHAASbitintheIICC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine,theslavedevicemustfirstchecktheconditionoftheIICHAASandI2CTOFbitstodeterminewhethertheinterruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdatatransfercompletionorI2Cbustime-outoccurrence.Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheIICSRWbit.Thisbitwillbecheckedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus,themicrocontrollermustinitialisethebus,thefollowingarestepstoachievethis:

• Step1Configurethepin-sharedI/OportstoI2Cfunction.

• Step2SetIICENbitintheIICC0registerto"1"toenabletheI2Cbus.

• Step3WritetheslaveaddressofthedevicetotheI2CbusaddressregisterIICA.

• Step4SettheIICEinterruptenablebittoenabletheI2Cinterrupt.

Stat

SET IICEN

Wite Save ddess to IIC

IC Bus Inteut=?

CLR IICEPo IICF to decide

when to go to IC Bus ISR

SET IICEWait fo Inteut

Go to Main Pogam Go to Main Pogam

YesNo

Configue the in-shaed I/O otsto IC function

I2C Bus Initialisation Flow Chart

Rev. 1.00 11 i 1 01 Rev. 1.00 117 i 1 01



I2C Bus Start Signal TheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbytheslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected,this indicates that theI2Cbusisbusyandtherefore theIICHBBbitwillbeset.ASTARTconditionoccurswhenahightolowtransitionontheSDAlinetakesplacewhentheSCLlineremainshigh.

Slave AddressThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheIICSRWbitoftheIICC1register.Theslavedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.TheslavedevicewillalsosetthestatusflagIICHAASwhentheaddressesmatch.

Asan I2Cbus interruptcancome from three sources,when theprogramenters the interruptsubroutine,theIICHAASandI2CTOFbitsshouldbeexaminedtoseewhethertheinterruptsourcehascomefromamatchingslaveaddressorfromthecompletionofadatabytetransferorI2Ctime-out.Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheIICDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheIICDregistertoreleasetheSCLline.

I2C Bus Read/Write Signal TheIICSRWbitintheIICC1registerdefineswhetherthemasterdevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifitistobeatransmitterorareceiver.IftheIICSRWflagis"1"thenthisindicatesthatthemasterdevicewishestoreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheIICSRWflagis"0"thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

I2C Bus Slave Address Acknowledge Signal After themasterhas transmittedacallingaddress,anyslavedeviceon theI2Cbus,whoseowninternaladdressmatchesthecallingaddress,mustgenerateanacknowledgesignal.Theacknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.IfnoacknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheIICHAASflagishigh,theaddresseshavematchedandtheslavedevicemustchecktheIICSRWflagtodetermineifitistobeatransmitterorareceiver.IftheIICSRWflagishigh,theslavedeviceshouldbesetuptobeatransmittersotheIICHTXbitintheIICC1registershouldbesetto"1".IftheIICSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasareceiverandtheIICHTXbitintheIICC1registershouldbesetto"0".

Rev. 1.00 118 i 1 01 Rev. 1.00 119 i 1 01



I2C Bus Data and Acknowledge Signal Thetransmitteddatais8-bitswideandistransmittedaftertheslavedevicehasacknowledgedreceiptof itsslaveaddress.Theorderofserialbit transmissionis theMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata, thereceivermusttransmitanacknowledgesignal, level"0",beforeitcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfromthemasterreceiver,thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignal toreleasetheI2CBus.ThecorrespondingdatawillbestoredintheIICDregister.Ifsetupasa transmitter, theslavedevicemustfirstwrite thedata tobetransmittedintotheIICDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheIICDregister.

Whentheslavereceiver receives thedatabyte, itmustgenerateanacknowledgebit,knownasIICTXAK,on the9thclock.Theslavedevice,which is setupasa transmitterwillcheck theIICRXAKbitintheIICC1registertodetermineifitistosendanotherdatabyte,ifnotthenitwillreleasetheSDAlineandawaitthereceiptofaSTOPsignalfromthemaster.

StatSCL

SD

SCL

SD

1

S=Stat (1 bit)S=Save ddess (7 bits)SR=SRW bit (1 bit)M=Save device send acknowedge bit (1 bit)D=Data (8 bits)=CK (RXK bit fo tansmitte TXK bit fo eceive 1 bit)P=Sto (1 bit)

0

CKSave ddess SRW

StoData CK

1 1 0 1 0 1 0

1 0 0 1 0 1 0 0

S S SR M D D …… S S SR M D D …… P

Note:*Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheIICDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheIICDregistertoreleasetheI2CSCLline.

I2C Communication Timing Diagram

Rev. 1.00 118 i 1 01 Rev. 1.00 119 i 1 01



Stat

ICTOF=1?

SET ICTOENCLR ICTOF

RETI

IICHS=1?

IICHTX=1? IICSRW=1?

Read fom IICD to eease SCL Line

RETI

IICRXK=1?

Wite data to IICD to eease SCL Line

CLR IICHTXCLR IICTXK

Dummy ead fom IICD to eease SCL Line RETI

RETI

SET IICHTX

Wite data to IICD to eease SCL Line

RETI

CLR IICHTXCLR IICTXK

Dummy ead fom IICD to eease SCL Line

RETI

YesNo

No Yes

Yes NoYesNo

No

Yes

I2C Bus ISR Flow Chart

I2C Time-out ControlInordertoreducetheproblemofI2Clockupduetoreceptionoferroneousclocksources,atime-outfunctionisprovided.IftheclocksourcetotheI2Cisnotreceivedforawhile,thentheI2Ccircuitryandregisterswillberesetafteracertaintime-outperiod.

The time-outcounterstartscountingonanI2Cbus"START"&"addressmatch"condition,andisclearedbyanSCLfallingedge.BeforethenextSCLfallingedgearrives,ifthetimeelapsedisgreater thanthetime-outsetupbytheI2CTOCregister, thenatime-outconditionwilloccur.Thetime-outfunctionwillstopwhenanI2C"STOP"conditionoccurs.

Rev. 1.00 10 i 1 01 Rev. 1.00 11 i 1 01



StatSCL

SD

SCL

SD

1 0

CKSave ddess SRW

Sto

1 1 0 1 0 1 0

1 0 0 1 0 1 0 0

IC time-out counte stat

IC time-out counte eset on SCL negative tansition

I2C Time-out

WhenanI2Ctime-outcounteroverflowoccurs, thecounterwillstopandtheI2CTOENbitwillbecleared tozeroandtheI2CTOFbitwillbesethighto indicate thata time-outconditionhasoccurred.Thetime-outconditionwillalsogenerateaninterruptwhichusestheI2Cinterruptvector.WhenanI2Ctime-outoccurs,theI2Cinternalcircuitrywillberesetandtheregisterswillberesetintothefollowingcondition:

Registers After I2C Time-outIICD IIC IICC0 No change

IICC1 Reset to POR condition

TheI2CTOFflagcanbeclearedbytheapplicationprogram.Thereare64time-outperiodswhichcanbeselectedusingbitsintheI2CTOCregister.Thetime-outtimeisgivenbytheformula:

((1~64)×32)/fSUB.

Thisgivesarangeofabout1msto64ms.

I2CTOC RegisterBit 7 6 5 4 3 2 1 0

Name ICTOEN ICTOF ICTOS5 ICTOS4 ICTOS3 ICTOS ICTOS1 ICTOS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 I2CTOEN:I2CTime-outControl0:Disable1:Enable

Bit6 I2CTOF:Time-outflag0:Notime-out1:Time-outoccurred

Bit5~0 I2CTOS5~I2CTOS0:Time-outDefinitionI2Ctime-outclocksourceisfSUB/32.I2Ctime-outtimeisgivenby:(I2CTOS[5:0]+1)×(32/fSUB)

Rev. 1.00 10 i 1 01 Rev. 1.00 11 i 1 01



InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforcea temporarysuspensionof themainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainstwoexternalinterruptsandseveral internal interrupts functions.Theexternal interruptsaregeneratedby theactionof theexternal INT0~INT1pins,while the internal interruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,TimeBaseandEEPROM.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory.ThefirstistheINTC0~INTC3registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI4registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheoperationalamplifierdigitaloutputinterruptandtheexternalinterrupttriggeredgetype.Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag.

Function Enable Bit Request Flag NotesGoba EMI — —INTn Pin INTnE INTnF n=0~1Ove Cuent Potection OCP0E OCP0F —Thema Potection THE THF —Operational Amplifier OP0E OP0F —/D Convete DE DF —Muti-function MFnE MFnF n=0~4LVD LVDE LVDF —IC IICE IICF —EEPROM wite oeation EPWE EPWF —

Time Base TBnE TBnF n=0~1

PTMPTMPnE PTMPnF

n=0~3PTMnE PTMnF

Interrupt Register Bit Naming Conventions

Register Name

Bit7 6 5 4 3 2 1 0

INTEG — — OP0S1 OP0S0 INT1S1 INT1S0 INT0S1 INT0S0INTC0 — OCP0F INT1F INT0F OCP0E INT1E INT0E EMIINTC1 DF OP0F THF — DE OP0E THE —INTC MF3F MFF MF1F MF0F MF3E MFE MF1E MF0EINTC3 MF4F EPWF IICF LVDF MF4E EPWE IICE LVDEMFI0 — — PTMF PTMPF — — PTME PTMPEMFI1 — — PTM1F PTMP1F — — PTM1E PTMP1EMFI — — PTM0F PTMP0F — — PTM0E PTMP0EMFI3 — — PTM3F PTMP3F — — PTM3E PTMP3EMFI4 — — TB1F TB0F — — TB1E TB0E

Interrupt Registers List

Rev. 1.00 1 i 1 01 Rev. 1.00 13 i 1 01



INTEG RegisterBit 7 6 5 4 3 2 1 0

Name — — OP0S1 OP0S0 INT1S1 INT1S0 INT0S1 INT0S0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5~4 OPA0S1~OPA0S0:interruptedgecontrolforoperationalamplifierdigitaloutput

00:Disable01:Risingedge(whenpositiveinputvoltage>negativeinputvoltage)10:Fallingedge(whennegativeinputvoltage>positiveinputvoltage)11:Risingandfallingedges(whenpositiveinputvoltage>negativeinputvoltageornegativeinputvoltage>positiveinputvoltage)

Bit3~2 INT1S1~INT1S0:interruptedgecontrolforINT1pin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

Bit1~0 INT0S1~INT0S0:interruptedgecontrolforINT0pin00:Disable01:Risingedge10:Fallingedge11:Risingandfallingedges

INTC0 RegisterBit 7 6 5 4 3 2 1 0

Name — OCP0F INT1F INT0F OCP0E INT1E INT0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 OCP0F:OCPinterruptrequestflag

0:Norequest1:Interruptrequest

Bit5 INT1F:INT1interruptrequestflag0:Norequest1:Interruptrequest

Bit4 INT0F:INT0interruptrequestflag0:Norequest1:Interruptrequest

Bit3 OCP0E:OCPinterruptcontrol0:Disable1:Enable

Bit2 INT1E:INT1interruptcontrol0:Disable1:Enable

Bit1 INT0E:INT0interruptcontrol0:Disable1:Enable

Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable

Rev. 1.00 1 i 1 01 Rev. 1.00 13 i 1 01




Name DF OP0F THF — DE OP0E THE —R/W R/W R/W R/W — R/W R/W R/W —POR 0 0 0 — 0 0 0 —

Bit7 ADF:A/DConverterinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 OPA0F:OperationalAmplifierinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 THF:HighVoltageDriverCombinationThermalProtectioninterruptrequestflag0:Norequest1:Interruptrequest

Bit4 Unimplemented,readas"0"Bit3 ADE:A/DConverterinterruptcontrol

0:Disable1:Enable

Bit2 OPA0E:OperationalAmplifierinterruptcontrol0:Disable1:Enable

Bit1 THE:HighVoltageDriverCombinationThermalProtectioninterruptcontrol0:Disable1:Enable



Name MF3F MFF MF1F MF0F MF3E MFE MF1E MF0ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 MF3F:Multi-functioninterrupt3requestflag0:Norequest1:Interruptrequest




Bit3 MF3E:Multi-functioninterrupt3control0:Disable1:Enable


Rev. 1.00 14 i 1 01 Rev. 1.00 15 i 1 01






Name MF4F EPWF IICF LVDF MF4E EPWE IICE LVDER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0


Bit6 EPWF:DataEEPROMinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 IICF:I2Cinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 LVDF:LVDinterruptrequestflag0:Norequest1:Interruptrequest


Bit2 EPWE:DataEEPROMinterruptcontrol0:Disable1:Enable

Bit1 IICE:I2Cinterruptcontrol0:Disable1:Enable

Bit0 LVDE:LVDinterruptcontrol0:Disable1:Enable

MFI0 RegisterBit 7 6 5 4 3 2 1 0

Name — — PTMF PTMPF — — PTME PTMPER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 PTMA2F:PTM2ComparatorAmatchinterruptrequestflag


Bit4 PTMP2F:PTM2ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"

Rev. 1.00 14 i 1 01 Rev. 1.00 15 i 1 01



Bit1 PTMA2E:PTM2ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit0 PTMP2E:PTM2ComparatorPmatchinterruptcontrol0:Disable1:Enable


Name — — PTM1F PTMP1F — — PTM1E PTMP1ER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0




Bit3~2 Unimplemented,readas"0"Bit1 PTMA1E:PTM1ComparatorAmatchinterruptcontrol

0:Disable1:Enable








0:Disable1:Enable


Rev. 1.00 1 i 1 01 Rev. 1.00 17 i 1 01









0:Disable1:Enable



Name — — TB1F TB0F — — TB1E TB0ER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas"0"Bit5 TB1F:TimeBase1interruptrequestflag


Bit4 TB0F:TimeBase0interruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas"0"Bit1 TB1E:TimeBase1interruptcontrol

0:Disable1:Enable

Bit0 TB0E:TimeBase0interruptcontrol0:Disable1:Enable

Rev. 1.00 1 i 1 01 Rev. 1.00 17 i 1 01



Interrupt OperationWhen theconditions foran interrupteventoccur, suchasaTMComparatorP,ComparatorAmatchorA/Dconversioncompletionetc., therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea"JMP"whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha"RETI",whichretrieves theoriginalProgramCounteraddress fromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Rev. 1.00 18 i 1 01 Rev. 1.00 19 i 1 01



EMI

InteutName

Request Fags

Enabe Bits

Maste Enabe Vector

EMI auto disabed in ISR

PioityHigh

Inteuts contained within Muti-Function Inteuts

xxE Enabe Bit

xxF Request Fag auto eset in ISR

Legend

xxF Request Fag no auto eset in ISR

ThemaPotection THF THE

EMIM. Funct. 4 MF4F MF4E

14H

PTM P PTMPF PTMPE

PTM PTMF PTME

PTM0 P PTMP0F PTMP0E

PTM0 PTM0F PTM0E

04HINT0 Pin INT0F INT0E EMI

0CHOCP OCP0F OCP0E EMI

EMI 08HINT1 Pin INT1F INT1E

3CH

IC IICF IICE EMI

/D DF DE EMI

EMILVD LVDF LVDE

34H

EEPROM EPWF EPWE EMI

1CH

Inteut Name

Request Fags

Enabe Bits

18HOP OP0F OP0E EMI

EMIM. Funct. 0 MF0F MF0E 0H


PTM1 PTM1F PTM1EEMIM. Funct. 1 MF1F MF1E 4H

EMIM. Funct. MFF MFE 8H


PTM3 PTM3F PTM3E

EMIM. Funct. 3 MF3F MF3E CH

30H

38HTime base 0 TB0F TB0E

Time base 1 TB1F TB1E

Low

Interrupt Structure

Rev. 1.00 18 i 1 01 Rev. 1.00 19 i 1 01



External InterruptTheexternalinterruptsarecontrolledbysignaltransitionsonthepinINTn.Anexternalinterruptrequestwill takeplacewhentheexternal interruptrequestflag,INTnF,areset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INTnE,mustfirstbeset.Additionallythecorrect interruptedgetypemustbeselectedusingtheINTEGregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins,theycanonlybeconfiguredasexternalinterruptpinsiftheirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeensetandtheexternalinterruptpinisselectedbythecorrespondingpin-sharedfunctionselectionbits.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Over Current Protection InterruptAnOCPInterruptrequestwilltakeplacewhentheOCPInterruptrequestflag,OCP0F,isset,whichoccurswhenalargecurrentisdetected.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andOCPInterruptenablebit,OCP0E,mustfirstbeset.Whentheinterrupt isenabled, thestackisnotfullandanovercurrent isdetected,asubroutinecalltotheOCPInterruptvector,willtakeplace.Whentheinterruptisserviced,theOCPInterruptflag,OCP0F,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Operational Amplifier InterruptTheOperationalAmplifierinterruptiscontrolledbytheoutputsignaltransitions.Additionallythecorrect interruptedgetypemustbeselectedusing theINTEGregister toenable theOperationalAmplifierinterruptfunctionandtochoosethetriggeredgetype.AnOperationalAmplifierinterruptrequestwilltakeplacewhentheOperationalAmplifierinterruptrequestflag,OPA0F,isset,whichwilloccurwhentheOperationalAmplifieroutputsignalchangesstate,whosetypeischosenbytheedgeselectbits.Whentheinterruptisenabled,thestackisnotfullandtheOperationalAmplifieroutputgeneratesatransition,asubroutinecalltotheOperationalAmplifierinterruptvector,willtakeplace.Whentheinterruptisserviced,theOperationalAmplifierinterruptrequestflag,OPA0F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

The INTEGregister isused toselect the typeofactiveedge thatwill trigger theOperationalAmplifierinterrupt.AchoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranOperationalAmplifier interrupt.Notethat theINTEGregistercanalsobeusedtodisabletheOperationalAmplifierinterruptfunction.

Rev. 1.00 130 i 1 01 Rev. 1.00 131 i 1 01



A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Thermal Protection InterruptIf theHighVoltageDriverCombinationThermalProtection function is enabled, aThermalProtectionInterruptrequestwilltakeplacewhentheThermalProtectionInterruptrequestflag,THF,isset,whichoccurswhenthedetectedtemperatureexceedsthepreset temperature.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andThermalProtectionInterruptenablebit,THE,mustfirstbeset.Whentheinterruptisenabled,thestack isnotfullandanover thermalcondition isdetected,asubroutinecall to theThermalProtectionInterruptvector,willtakeplace.Whentheinterruptisserviced,theThermalProtectionInterruptflag,THF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Multi-function InterruptWithin thisdevice therearemultipleMulti-function interrupts.Unlike theother independentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMandTimerBaseInterrupts.

AMulti-functioninterruptrequestwilltakeplacewhenanyoftheMulti-functioninterruptrequestflags,MFnFareset.TheMulti-function interrupt flagswillbesetwhenanyof their includedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfull,andeitheroneoftheinterruptscontainedwithineachofMulti-functioninterruptoccurs,asubroutinecalltooneoftheMulti-functioninterruptvectorswilltakeplace.Whentheinterruptisserviced,therelatedMulti-FunctionrequestflagwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhentheinterruptisserviced,therequestflagsfromtheoriginalsourceoftheMulti-functioninterrupts,namelytheTMandTimerBaseInterruptswillnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

LVD InterruptAnLVDInterruptrequestwilltakeplacewhentheLVDInterruptrequestflag,LVDF,isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andLowVoltageInterruptenablebit,LVDE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecall totheLVDInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableother interrupts,andtheLVDinterruptrequestflag,LVDF,willbealsoautomaticallycleared.

Rev. 1.00 130 i 1 01 Rev. 1.00 131 i 1 01



I2C InterruptAnI2CInterruptrequestwill takeplacewhentheI2CInterruptrequest flag, IICF, isset,whichoccurswhenabyteofdatahasbeenreceivedortransmittedbytheI2Cinterface,I2CaddressmatchorI2Ctime-out.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andtheSerialInterfaceInterruptenablebit,IICE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanyofthesesituationsoccurs,asubroutinecalltotheI2CInterruptvector,will takeplace.WhentheI2CInterfaceInterruptisserviced,theinterruptrequest flag, IICF,willbeautomatically resetand theEMIbitwillbecleared todisableotherinterrupts.

EEPROM InterruptAnEEPROMInterruptrequestwill takeplacewhentheEEPROMInterruptrequestflag,EPWF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchto itsrespective interruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,EPWE,must firstbeset.When the interrupt isenabled, thestack isnot fullandanEEPROMWritecycleends,asubroutinecalltotheEEPROMInterruptvectorwilltakeplace.WhentheEEPROMInterfaceInterruptisserviced,theinterruptrequestflag,EPWF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

Time Base InterruptsTheTimeBaseinterruptsarecontainedwithintheMulti-functionInterrupts.Thefunctionof theTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappenstheirrespectiveinterruptrequestflags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMI,andrelevantMulti-functionInterruptenablebit,MF4E,andTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltotheirrespectivevectorlocationswilltakeplace.WhentheTimeBaseinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableother interrupts,howeveronlytherelatedMF4Fflagwillbeautomaticallycleared.AstheTimeBaseinterruptrequestflag,TB0ForTB1F,willnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource,fTB,originatesfromtheinternalclocksourcefSYS/4orfSUBwhichcanbeselectedbytheTBCKbitintheTBCregister.ThisfTBclockpassesthroughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBCregistertoobtainlongerinterruptperiodswhosevalueranges.

fSYS/4

MUX

÷8 ~ 15

÷1 ~ 15fSUB

TBCK

Time Base 0 Inteut

Time Base 1 Inteut

fTB

TB0~TB00

TB11~TB10

MUX

LIRC

LXT

Configuation Otion

Time Base Interrupts

Rev. 1.00 13 i 1 01 Rev. 1.00 133 i 1 01



TBC RegisterBit 7 6 5 4 3 2 1 0

Name TBON TBCK TB11 TB10 LXTSP TB0 TB01 TB00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 1 0 1 1 1

Bit7 TBON:TimeBase0andTimeBase1Control0:Disable1:Enable

Bit6 TBCK:SelectfTBclock0:fSUB1:fSYS/4

Bit5~4 TB11~TB10:SelectTimeBase1Time-outPeriod00:212/fTB01:213/fTB10:214/fTB11:215/fTB

Bit3 LXTSP:LXTQuickStartControl0:Disable1:Enable

Bit2~0 TB02~TB00:SelectTimeBase0Time-outPeriod000:28/fTB001:29/fTB010:210/fTB011:211/fTB100:212/fTB101:213/fTB110:214/fTB111:215/fTB

PTM InterruptsThePeriodicTypeTMshavetwointerrupts,onecomesfromthecomparatorAmatchsituationandtheothercomesfromthecomparatorPmatchsituation,allof thePTMinterruptsarecontainedwithin theMulti-functionInterrupts.Foreachof thePeriodicTypeTMsthereare twointerruptrequestflagsPTMPnFandPTMAnFandtwoenablebitsPTMPnEandPTMAnE.APTMinterruptrequestwilltakeplacewhenanyofthePTMrequestflagsareset,asituationwhichoccurswhenaPTMcomparatorPorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI, respectivePTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaPTMcomparatormatchsituationoccurs,asubroutinecall totherelevantMulti-functionInterruptvectorlocations,will takeplace.WhenthePTMinterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AsthePTMinterruptrequestflagswillnotbeautomaticallycleared, theyhavetobeclearedbytheapplicationprogram.

Rev. 1.00 13 i 1 01 Rev. 1.00 133 i 1 01



Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandis independentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageoroperationalamplifierinputchangemaycause theirrespectiveinterruptflag tobesethighandconsequentlygenerateaninterrupt.Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine isexecuted,asonly theMulti-function interrupt request flags,MFnF,willbeautomaticallycleared, the individual request flag for the functionneeds tobeclearedby theapplicationprogram.

It isrecommendedthatprogramsdonotusethe"CALL"instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.00 134 i 1 01 Rev. 1.00 135 i 1 01



Low Voltage Detector – LVDThedevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheENLVDbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.TheVBGENbitisusedtocontrolinternalBandgapreferencevoltageenabledordisabled.AnyoftheENLVDandVBGENbitsissethigh,theBandgapreferencevoltagewillbeenabled.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0

Name — — LVDO ENLVD VBGEN VLVD VLVD1 VLVD0

R/W — — R R/W R/W R/W R/W R/W

POR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 ENLVD:LowVoltageDetectorControl0:Disable1:Enable

Bit3 VBGEN:BandgapVoltageOutputControl0:Disable1:Enable

Bit2~0 VLVD2~VLVD0:SelectLVDVoltage000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

Rev. 1.00 134 i 1 01 Rev. 1.00 135 i 1 01



LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD, fallsbelowthispre-determinedvalue, theLVDObitwillbesethighindicatingalowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbya referencevoltagewhichwillbeautomaticallyenabled.When thedevice is intheSLEEPmode, thelowvoltagedetectorwillbedisabledevenif theENLVDbit ishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

VDD

LVDEN

LVDO

VLVD

tLVDS

LVD Operation

TheLowVoltageDetectoralsohasitsowninterrupt,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.Inthiscase,theLVDFinterruptrequest flagwillbeset,causingan interrupt tobegenerated ifVDD fallsbelowthepresetLVDvoltage.Thiswillcausethedevicewake-up,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVDFflagshouldbefirstsethighbeforethedeviceenterstheIDLEMode.NotethattheLVDfunctionwillbeautomaticallydisabledifthedeviceenterstheSLEEPMode.

Rev. 1.00 13 i 1 01 Rev. 1.00 137 i 1 01



Configuration OptionsConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsOscillator Options

1High Seed System Osciato Seection – fH:• HXT• HIRC

Low Seed System Osciato Seection – fSUB:• LXT• LIRC

3

HIRC Fequency Seection:• 16MHz• 12MHz• 8MHz

Watchdog Timer Options

4WDT Function:• Always enable• Controlled by WDT Control Register

5WDT Cock Seection – fS:• fSUB

• fSYS/4

Rev. 1.00 13 i 1 01 Rev. 1.00 137 i 1 01



Application Circuits

HT45F4630

512 Byte EEPROM

PWM

I2CTouch Key IC

125kHz RFID

Temp. Seneor

IO x 18

ADC

MDC

Motor Driver

Over Current

Protector

Latch location detector

HT45F4630

512 Byte EEPROM

I2C13.56MHz

RFID Tranceiver

Temp. Seneor

IO x 18

ADC

MDC

Motor Driver

Over Current

Protector

Latch location detector

Rev. 1.00 138 i 1 01 Rev. 1.00 139 i 1 01



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.00 138 i 1 01 Rev. 1.00 139 i 1 01



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

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Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticDD [m] dd Data Memoy to CC 1 Z C C OVDDM [m] dd CC to Data Memoy 1Note Z C C OVDD x dd immediate data to CC 1 Z C C OVDC [m] dd Data Memoy to CC with Cay 1 Z C C OVDCM [m] dd CC to Data memoy with Cay 1Note Z C C OVSUB x Subtact immediate data fom the CC 1 Z C C OVSUB [m] Subtact Data Memoy fom CC 1 Z C C OVSUBM [m] Subtact Data Memoy fom CC with esut in Data Memoy 1Note Z C C OVSBC [m] Subtact Data Memoy fom CC with Cay 1 Z C C OVSBCM [m] Subtact Data Memoy fom CC with Cay esut in Data Memoy 1Note Z C C OVD [m] Decima adjust CC fo ddition with esut in Data Memoy 1Note CLogic OperationND [m] Logica ND Data Memoy to CC 1 ZOR [m] Logica OR Data Memoy to CC 1 ZXOR [m] Logica XOR Data Memoy to CC 1 ZNDM [m] Logica ND CC to Data Memoy 1Note ZORM [m] Logica OR CC to Data Memoy 1Note ZXORM [m] Logica XOR CC to Data Memoy 1Note ZND x Logica ND immediate Data to CC 1 ZOR x Logica OR immediate Data to CC 1 ZXOR x Logica XOR immediate Data to CC 1 ZCPL [m] Comement Data Memoy 1Note ZCPL [m] Comement Data Memoy with esut in CC 1 ZIncrement & DecrementINC [m] Incement Data Memoy with esut in CC 1 ZINC [m] Incement Data Memoy 1Note ZDEC [m] Decement Data Memoy with esut in CC 1 ZDEC [m] Decement Data Memoy 1Note ZRotateRR [m] Rotate Data Memoy ight with esut in CC 1 NoneRR [m] Rotate Data Memoy ight 1Note NoneRRC [m] Rotate Data Memoy ight though Cay with esut in CC 1 CRRC [m] Rotate Data Memoy ight though Cay 1Note CRL [m] Rotate Data Memoy eft with esut in CC 1 NoneRL [m] Rotate Data Memoy eft 1Note NoneRLC [m] Rotate Data Memoy eft though Cay with esut in CC 1 CRLC [m] Rotate Data Memoy eft though Cay 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV [m] Move Data Memoy to CC 1 NoneMOV [m] Move CC to Data Memoy 1Note NoneMOV x Move immediate data to CC 1 NoneBit OperationCLR [m].i Cea bit of Data Memoy 1Note NoneSET [m].i Set bit of Data Memoy 1Note NoneBranch OperationJMP add Jum unconditionay NoneSZ [m] Ski if Data Memoy is zeo 1Note NoneSZ [m] Ski if Data Memoy is zeo with data movement to CC 1Note NoneSZ [m].i Ski if bit i of Data Memoy is zeo 1Note NoneSNZ [m].i Ski if bit i of Data Memoy is not zeo 1Note NoneSIZ [m] Ski if incement Data Memoy is zeo 1Note NoneSDZ [m] Ski if decement Data Memoy is zeo 1Note NoneSIZ [m] Ski if incement Data Memoy is zeo with esut in CC 1Note NoneSDZ [m] Ski if decement Data Memoy is zeo with esut in CC 1Note NoneCLL add Suboutine ca NoneRET Retun fom suboutine NoneRET x Retun fom suboutine and oad immediate data to CC NoneRETI Retun fom inteut NoneTable Read OperationTBRD [m] Read table (specific page) to TBLH and Data Memory Note NoneTBRDC [m] Read tabe (cuent age) to TBLH and Data Memoy Note NoneTBRDL [m] Read tabe (ast age) to TBLH and Data Memoy Note NoneMiscellaneousNOP No oeation 1 NoneCLR [m] Cea Data Memoy 1Note NoneSET [m] Set Data Memoy 1Note NoneCLR WDT Cea Watchdog Time 1 TO PDFCLR WDT1 Pe-cea Watchdog Time 1 TO PDFCLR WDT Pe-cea Watchdog Time 1 TO PDFSWP [m] Swa nibbes of Data Memoy 1Note NoneSWP [m] Swa nibbes of Data Memoy with esut in CC 1 NoneHLT Ente owe down mode 1 TO PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

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CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

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JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

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RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

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RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0rotatedintobit7. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

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SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.00 150 April 16, 2016 Rev. 1.00 151 April 16, 2016



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24-pin SSOP (150mil) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max. — 0.3 BSC —B — 0.154 BSC —C 0.008 — 0.01 C’ — 0.341 BSC —D — — 0.09 E — 0.05 BSC —F 0.004 — 0.010 G 0.01 — 0.050 H 0.004 — 0.010α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max. — .000 BSC —B — 3.900 BSC —C 0.0 — 0.30 C’ — 8.0 BSC —D — — 1.75 E — 0.35 BSC —F 0.10 — 0.5 G 0.41 — 1.7 H 0.10 — 0.5 α 0° — 8°

Rev. 1.00 15 i 1 01 Rev. 1.00 153 i 1 01



Coyight© 01 by HOLTEK SEMICONDUCTOR INC.

The infomation aeaing in this Data Sheet is beieved to be accuate at the time of ubication. Howeve Hotek assumes no esonsibiity aising fom the use of the specifications described. The applications mentioned herein are used solely fo the uose of iustation and Hotek makes no waanty o eesentation that such aications wi be suitabe without futhe modification no ecommends the use of its oducts fo aication that may esent a isk to human ife due to mafunction o othewise. Hotek's oducts ae not authoized fo use as citica comonents in ife suot devices o systems. Hotek eseves the ight to ate its products without prior notification. For the most up-to-date information, please visit ou web site at htt://www.hotek.com.tw.

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dc motor driver assp mcu - home - holtekrev. 1.00 4 i 1 01 rev. 1.00 5 i 1 01 ht45f4630 dc motor...

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