de1 tren sopc

8/13/2019 De1 Tren Sopc

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NIOS II programming using SoPC Builder on

DE2 FPGA Kit

Bi vit nhm mc ch gii thiu v hng dn cch thc hin mt h thng SoPC FPGA

da trn Vi x l 32-bit Nios II ca altera v hng dn cch pht trin cc ng dng trn hthng Nios II. Ni dung gm 3 phn :

Phn1: Xy dngmththngnhng ngintrn FPGA sdngSoPC Builder.

Phn2: Lptrnh iukhinI/O cho Nios II

Phn3: Tomtcomponent tch hpvo hthngNios II

Phn1: Xy dngmththngnhng ngintrn FPGA sdngSoPC Builder.

Phn ny gip chng ta to mt h thng (system) vi li NIOS II. V cc bc lm vic vi NIOS II IDE.

GiithiuhthngSoPC v chngtrnh SoPC builder:

Trchtchng ta tora mtproject trong phnmmQUARTUS II theo cc bcsau:

Hnh 1 : Giao dinQuartus

- M chng trnh QUATUS II File>New Project Wizard t tn ng dn, tn project. Sau nhn Next.

- Thm cc file cn thit vo project (nu c), sau nhn Next.

- Chn la thit b FPGA cn thit. trong trng hp l kit DE1 th m hiu l EP2C20F484C7 (nu dng KIT DE2 th m hiu

ca FPGA l EP2C35F672C6), sau bm next.

- Bc tip theo l chn cc cch thc m phng. Trong bi ny ta khng cn dng cc cng c m phng nn khng chn

phn ny, nn ta chn lun finish hon thnh vic to project.

Tiptheo ta tohthngNIOS II bngSOPC Builder :


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H thng SoPC (System on Programable Chip) bao gm cc thnh phn chnh:

- CPU Nios II

- Memory (onchip memory hoc Ram ngoi)

- JTAG

- Port I/O

- Cc component

Ta m tool SoPC builder trong phn mm QUATUS II

Sau t tn h thng chn ngn ng m t phn cng l Verilog hay VHDL, nhn OK.

Hnh 2 : SoPC Builder


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Hnh 3 : ChnhSoPC datrn ngn ngverilog

* ToVXL Nios II cho hthng:

Chn kiu NIOS II: ty vo tnh nng ca h thng m chn li NIOS II cho ph hp .Trong vi d ny v khng cn nhiu

chc nng nn ta chon phin bn n gin nht l phin bn NIOS II/e bng cch check vo mc NIOS II/e nh hnh bndi.


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Hnh 4 : ChnLoiNIOS II

i vi kiu NIOS ny n gin nn ta tip tc next n phn chn thnh phn JTAG. Trong bi ny ta s dng phin bn

NIOS II/e nn ch cho php chn JTAG level 1. Ri nhn next hon thnh khai bo


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Hnh 5 : ChnDebug level

Chn la mt s chc nng khc ca NIOS II v d nh phn cng dng thc hin cc php tnh c du chm ng, ccqui nh v ngt, ri chn finish hon thnh.


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Hnh 6 : Toxong Nios II

* Ch l exception vector v reset vector cha c mapping v ta cha kt ni Nios vi bt k b nh no, ta s quay tr

li set hai vector ny ngay khi to b nh data v program cho Nios II.

* Tohthngbnhcho Nios II:

Nios II ch l mt li vi x l ch cha phi l vi iu khin do n cn phi c ti thiu nh d liu v b nh chng

trnh c th hot ng c.

n gin nht l dng On-Chip Memory bng cch double_click On-Chip Memory(RAM or ROM). Nhng lu nn

chn dung lng b nh ph hp tng ng dng. V d y chn 32Kbytes, chiu rng mi nh l 32 bit nu l kit DE2,

nu l DE1 ta chn b nh l 16KB. Sau chn Finish hon thnh.

Sau khi to b nh xong, ta to kt ni gia Nios II v b nh nu n cha c kt ni. Ch l phi kt ni c hai bus

instruction_master v data_master


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Hnh 7 : Tobnhhthng

* ToUART thng qua chunJTAG cho Nios II:

Trong Communication double click chn JTAG UART. Nu khng bit chnh g ht th c nhn Finish hon thnh.


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Hnh 8 : JTAG UART

Sau bcny ta c hthngnginc thhotngcnhhnh sau :


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Hnh 9 : HthngSoPC tithiu

bc ny nu h thng vn cn b bo li vng nh do tranh chp a ch trong h thng, th khc phc li ny ta

vo: System> Auto-Assign Base Addresses.

Hnh 10 : Litranh chpbnh

Bc tip theo ta kch doblle vo component Nios. Trong mc Reset Vector v Expection Vectorchn onchip_mem

sa li nh ni trn .


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Hnh 11 : Salireset vector v exception vector

- Trong th System Generation:

Nu cn m phng ta cn check vo box Simulation. Create simulator files. Trong bi ny ta khng cn m phng nnkhng check vo box ny.

Sau nhn nt Generate to h thng.- Ch h thng chy xong v nhn exit


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Hnh 12 : Tohthngthnh cng

ToTop Module trong Quartus

To Top Module cho Project, sau gi module h thng va mi to vo.Gn chn cho Top Module.

- Lu :

Chn Assignments / Device, Nhn nt Device & Pin Options , Trong th Unused Pins chn As input tri-stated trong Reserve all unusued pins, Nhn OK.

Di y l on mu ca bi ny

module bai1 (CLOCK_50,KEY);

input CLOCK_50;input KEY;

system IC1(// 1) global signals:.clk_0(CLOCK_50),


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.reset_n(KEY),

);endmodule

Note: Trong on chng trnh trn ta thyc module system y l module do chng trnh tng hp to ra. Module

ny s c tn trng vi tn ta t ban u

Hnh : tch hphthngSoPC vo hthng

cho h thng. Ta s tm thy Module ny trong th mc lu chng trnh ang thc hin system.v, thc hin file top v

bin dch ng m khng b li ta nn m file system.v v tm n phn khai bo ca module system, copy nguyn phn

khai bo ny dn vo top module ca chng ta ( nh hnh di ) v gn cc tn hiu khai bo top module nh trn.

Tnghphthng

Chn Processing / Start Compilation tng hp h thng.

Khi h thng c tng hp. Cc File *.sof v file * .pof s c to ra.

Lptrnh iukhinNios sdngngn ngC

Cc bc thc hin:

- M chng trnh Nios IIv Chn ni lu tr phn mm: File/ switch workspace, sau chn ng dn v OK.


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Hnh 13 : Giao dinpht trinNios II IDE

- M chng trnh Nios II

Chn File>New>NiosII C/C++ Application

- t tn cho chng trnh trong khung Name (nu ta munto 1 th vin mi, y chng ta xi th vin c sn c

h tr l hello_ world_small_0)

- Ti khung SOPC builder System chn ng dn ti file c ui *.ptf m Quartus sinh ra trong qu trnh tng hp.


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Hnh 14 : Toexample hello_world_small

- n y ta c th vit code C vo file hello_ worl_small.c c sn hay to mt file mi v s dng cc lnh c trong C v

cc lnh h tr ring cho Nios lp trnh iu khin cho h thng.

- Trong bi ny ta s thc hin chc nng n gin nht trong C l xut mt on text ra mn hnh.(ta dung lun chng

trnh trong hello_ worl_small.c),

- Trc ht ta chy chng bin dch trong quartus v np xung kit :

Nu phn mm bn khng c licence th s c bng cnh bo v gii hn thi gian mphng do khng c licence, bn

khng quan tm v bm OK b qua. Tip theo l np xung kit:


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- Sau khi Np xong chng trnh Quartus, gi y ta c mt h thng y vi trung tm l vi x l 32bit Nios II. By

gi ta qua giao din Nios II IDE np chng trnh cho NIOS:

Hnh 15 : Npchngtrnh cho Nios II

Sau khi np xong, nu chy ng, mn hnh s xut ra dng ch hello from Nios II ! nh hnh sau


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Hnh 16 : Example Hello world small

Lc ny th phn mm NIOS II tht s hot ng v iu khin phn cng m ta np xung kit DE1 lc ny, hai thnh

phn phn cng v mm ny c kt ni vi nhau, chng ta c th dng phn ny tc ng n phn kia, v d ta thay

i chng trnh trn NIOS II th kt qu hin th trn kit s khc (phn ny cha c hin th ) hay khi ta bm nt iu khin

trn kit (vd l nt reset chng hn ) th kt qu hin th trn NIOSII cng s thay i.

Phn2: Lptrnh iukhinI/O cho Nios II

- Ta thc hin cc bc nh to project trong QUARTUS II, v s dng toll SoPC builder. y ta cng to h thng vi ccthnh phn cn bn nh phn 1 ch c thm vo component pi/o, nh hnh di:


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Hnh 17 : ToI/O Port cho Nios II

- Sau hon ton tng t nh bi mt ta s tin hnh to file top trong Quartus II, gn chn kt ni h thng v kt nixung kit.

- Tip theo l lm vic vi phn mm NIOS IDE, cng tng t nh phn 1.

Di y chng ta s lm 1 v d v phn ny thng qua vic iu khin led 7 on.

Trong v d ny ta s lm theo yu cu sau:

Xy dnghthnggm:

- Nios, memory,JTAG

- PIO: SW[15:0], HEX0, HEX7

S dng lnh IORD c d liu t SW Gii m d liu ra m led 7 on Thc hin php cng hai s 8 bit Gii m kt qu ra m led 7 on Dng lnh IOWR ghi ra led 7 on

Di y l cu trc h thng SoPC ta thit k v chng trnh Module top ta vit dng xung board DE1:


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Hnh 18 : SoPC system

Hnh 19 : Example iukhinLed 7 on- SoPC


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Tip theo s l cng on thc hin gn chn cho chip FPGA, cc chn m ta s dng s phi c kt ni ti cc led by

on ta c th iu khin chng, ta c th tham kho datasheet ca kit DE bit cc chn ca Led 7 on c kt ni

vi chn no, qua gn chn cho ng.

Hnh 20 : Gn chn cho v diukhinled 7 on

Sau ta xung board tng t nh hng dn phn 1, v tin hnh vit code trn Nios IDE iu khin. Cc bc

xy dng ta lm tng t nh hng dn phn 1, vi a code v d mu sau:

(ch l trc khi vit chng trnh chnh iu khin h thng th ta nn vit mt chng trnh tht n gin m bo

h thng chy ng nhm to ra cc file h thng cn thit, phc v chy chng trnh chnh nh v d y l file

"system.h")

Code iu khin h thng

#include "system.h"

#include "io.h"

int giai_ma(int a);

void main(){int x,y,z,t,chuc,dv;

while(1){

x = IORD(INA_BASE,0);y = IORD(INB_BASE,0);z = x


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switch (a)

{case 0 : led = 0x40;break; //0

case 1 : led = 0x79;break; //1

case 2 : led = 0x24;break; //2case 3 : led = 0x30;break; //3case 4 : led = 0x19;

break; //4case 5 : led = 0x12;break; //5



case 8 : led = 0x00;break; //8case 9 : led = 0x10;

break; //9default : led = 0xff;

break; // khong sang}return led;

Trong HEX0_BASE, HEX1_BASE, LEDG_BASE, INA_BASE, INB_BASE L a ch ca cc thnh phn HEX0, HEX1, LEDR, INA,

INB (c khai bo trong file system.h )

hiu r nhng cu lnh dung c vghi thanh ghi dung y ( cng nh l ni chung trong lp trinh Nios IDE) ta s

tham kho cc nh ngha v cc lnh c ghi ngoi vi di y:

Hnh 21 : cc hm cghi I/O cbncaNios II


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Sau khi khi thc hin xong cc bc lp trnh. Ta tin hnh tng hp v np xung kit kim tra kt qu.

-Thay i cc gii tr ca SW

-Kim tra s hin th trn LED-7-on

Phn3: Tomtcomponent tch hpvo hthngNios IICc bckhitocomponent

Trong SoPC builder chn New component Chn cc fileverilog vit. Ch ra file no cha top module nh chc nng cho cc port I/O Thm vo cc file software (nu c) Nhn finish to ra mt component mi

Tm hiuvcch tnh achthng qua component iukhinLED

Yu cu :

- Xy dng mt component gip CPU giao tip vi led:

LEDR[7:0] c ni vi ng a ch ni ca component. LEDG [7:0] c ni vi ng data.

- Phn ny gip ta tm hiu:

Cch iu khin giao tip gia Nios v component 8bit. Cch tnh a ch ni cho component ca Nios vidata l 8bit.

Ta vit mt file verilog lm top module cho component. Module ny ch c nhim v kim tra tn hiu CS c tch cc hay

khng.

Nu tch cc th ni cc ng data v addr vi LEDR Nu khng tch cc cc tn hiu data v addr s trng thi khng sng.

module led_control(cs,rst_n,we,clk,addr,data,addr_out,data_out);input cs,rst_n,clk;input we;input [3:0]addr;

input [7:0]data;output reg [7:0]data_out;

output reg [3:0]addr_out;always @(posedge clk or negedge rst_n)begin

if (rst_n == 1'b0)begin

data_out


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end

endmodule

Cc bc thc hin nh sau :

Vit code verilog/VHDL cho component m ta mun tch hp vo h thng SoPC

Vo SoPC builder> chn New component> Trong chng trnh Nios dng lnh IOWR,IORD vi cc offset tng dn tng n v. Kim tra s hin th trn LEDR v rt ra kt lun

u tin tato component nh sau :

Hnh 22: Touser component

- Click next vo th HDL File

- Trong th HDL File, chn file m t thnh phn cn to. Bng cch click vo Add_button v chn ng dn ti file cn

thm vo. Nh phi chn Top Level Module lfile no. V d chn b iu khin LED (led_control) l thnh phn trong h

thng.

Sau khi chn cc file th chng trnh s t ng kim tra li. Nu c li, th chng trnh s bo li ti dng th my ca file

ang kim tra (lu cch kim tra li ny khng ging vi cch kim tra li trong Quartus m kim tra c v li c php ln

li v cch khai bo tn hiu giao tip cn thit ln cc thng s k thut yu cu i vi ngoi vi.

- Sau khi kim tra xong, click Next chn th Signals chn cc ng tn hiu ph hp vi kt cu Avalon. Trong bc

ny cn ch r cc tn hiu Clock, Reset, Write-enable, Read-enable, Write-data, Read-data, v cc tn hiu export.

Cc khai bo trn nm trong cc nhm interface khc nhau. Bao gm:

Avalon Interface: giao tip gia component v NIOS. uc chia lm 2 nhm nh. Mt nhm t hnh thnh trong qutrnh gn cc component ca nh sn xut vo h thng. Mt nhm c kt ni bi ngi thit k h thng.


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Clock Interface: bao gm tn hiu clock, reset. Conduit_Ports Interface: c dng cho cc tn hiu giao tip ra ngoi h thng NIOS.

hiu thm v ngha ca cc nhm interface, ta c th tham kho hnh sau y:

Hnh 23 : Tomtcomponent tngthch Avalon Bus

Trong bi ny ta s khai bo cc tn hiu nh sau:


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Hnh 24 : Cc tn hiucacomponent cnphicgn cho ngchcnng

- Trong Tab Signal cn ch r cc tn hiu: Clk, CS, Reset ...


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Hnh 25 : Cuhnh cc tn hiu

- Ti lc ny ta thy chng trnh vn b bo li. Li ny l do cc interface cha c cc xung clk lin quan. khc phc li

ny ta s khai bo xung clock cho interface bc sau.


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Hnh 26 : Bo litn hiuclock

- Tab Interfaces dng iu khin Timing cho component


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Hnh 27 : Cuhnh timing v clock cho component

Cc thng s cn xc nh lin quan ti Setup-Time v Hold-Time. Cc thng s trn ph thuc ch yu vo yu cu timing

ca component. Trong v d ny ta c th gi nguyn gi tr mc nh. Nhng cn ch r tn hiu Clock ca h thng.

Sau khi thit lp timing ta c th coi lai dng sng kim tra nh th c ng cha

- Tip tc thit lp cc thng s cho interface

- Trong Tab Component Wizard ta thit lp tn v nhm cng nh phin bn ca component.

- Nhn Finish kt thc to mt thnh phn.

- Quay tr li SOPC Bilder. Gn CPU, memory, JTAG vo h thng. Ly ngoi vi mi to thm vo h thng bng cch

double_click vo component va to.


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Hnh 28 : Hthngctch hpthm ngoivi led_control

- Thit lp cc thng s nh gn a ch, khai bo a ch reset vector, nh hng dn bi 1. Sau thc hin

Generate h thng.

- Vit Top Module, tng hp v gn chn cho h thng

- Thc hin to, khai bo cc thng s ca project

- Dng Nios IDE vit chng trnh iu khin

- iu khin component ta dng lnh:IOWR_8DIRECT(BASE,OFFSET,DATA); //(V ngdata c rng8 bit)

Top_module:

module lab1

(

CLOCK_50,KEY,

LEDR,LEDG);

input CLOCK_50;input KEY;output [7:0]LEDR;

output [3:0]LEDG;

system IC1(// 1) global signals:

.clk_0(CLOCK_50),


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.reset_n(KEY),

// the_control .addr_out_from_the_control(LEDG),

.data_out_from_the_control(LEDR)

);

endmodule

Chng trnh iu khin:

#include "system.h"#include "io.h"

void delay (void);

int main(){

int x;while(1)

{for(x = 0; x


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Hnh 29 : Ktquchytrn Nios II

Nh vy l ta tm hiu qua cch thc pht trin mt ng dng trn Nios II s dng h thng to t ng bi cng c

SoPC Builder ca Quartus. Hy vng bi vit mang li nhiu thng tin cho cc bn, nu cn trao i g vui lng gi comment

cho chng ti. Rt hy vng nhn c cc kin nh gi v gp ca cc bn.

de1 tren sopc

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