S. Reda EN160 SP’07

Design and Implementation of VLSI Systems(EN0160)

Lecture 29: Datapath Subsystems 3/3

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2007

[sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07

Outline

• Last two lectures– We talked about different kind of adders

• This lecture1. Comparators

2. Shifters

3. Multipliers

S. Reda EN160 SP’07

Comparators

• 0’s detector: A = 00…000• 1’s detector: A = 11…111• Equality comparator: A = B• Magnitude comparator: A < B

S. Reda EN160 SP’07

1. 1’s and 0’s detectors

• 1’s detector: N-input AND gate• 0’s detector: NOTs + 1’s detector (N-input NOR)

A0

A1

A2

A3

A4

A5

A6

A7

allones

A0

A1

A2

A3

allzeros

allones

A1

A2

A3

A4

A5

A6

A7

A0

When is this circuit structure a good idea?

S. Reda EN160 SP’07

1. Equality comparator

• Check if each bit is equal (XNOR, aka equality gate)• 1’s detect on bitwise equality

A[0]B[0]

A = B

A[1]B[1]

A[2]B[2]

A[3]B[3]

S. Reda EN160 SP’07

1. Magnitude comparator

A0

B0

A1

B1

A2

B2

A3

B3

A = BZ

C

A B

N A B

Compute B-A and look at signB-A = B + ~A + 1For unsigned numbers, carry out is sign bit

S. Reda EN160 SP’07

2. Shifters

• Shifting a data word by a constant amount is trivial• A programmable shifter is more complex

Ai

Ai-1

Bi

Bi-1

Right Leftnop

Bit-Slice i

...Multibit shifter can be cascaded together

S. Reda EN160 SP’07

2. Barrel Shifter

Sh3Sh2Sh1Sh0

Sh3

Sh2

Sh1

A3

A2

A1

A0

B3

B2

B1

B0

: Control Wire

: Data Wire

• Signal passes through at most one transmission gate• Total transistors = N2

• Dominated by wiring

S. Reda EN160 SP’07

2. Logarithmic shifterSh1 Sh1 Sh2 Sh2 Sh4 Sh4

A3

A2

A1

A0

B1

B0

B2

B3

• Total shift is decomposed into stages of 2• Speed of shifting N bits depends on log N• Number of transistor = 2(log N)* N

S. Reda EN160 SP’07

Multipliers

x

Partial products

Multiplicand

Multiplier

Result

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 1

Z X·· Y Zk2k

k 0=

M N 1–+

= =

Xi2i

i 0=

M 1–

Yj2j

j 0=

N 1–

=

XiYj2i j+

j 0=

N 1–

i 0=

M 1–

=

X Xi2i

i 0=

M 1–

=

Y Yj2j

j 0=

N 1–

=

with

S. Reda EN160 SP’07

Array multiplier

Y0

Y1

X3 X2 X1 X0

X3

HA

X2

FA

X1

FA

X0

HA

Y2X3

FA

X2

FA

X1

FA

X0

HA

Z1

Z3Z6Z7 Z5 Z4

Y3X3

FA

X2

FA

X1

FA

X0

HA

Where is the critical path?

S. Reda EN160 SP’07

Critical path of MxN multiplier

HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

S. Reda EN160 SP’07

Carry Save Multiplier

HA HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Vector Merging Adder

The carry bits are not immediately added, but rather are “saved” for the next adder stage