Design Technology CenterDesign Technology CenterNational Tsing Hua UniversityNational Tsing Hua University

A New Paradigm for Scan Chain Diagnosis Using Signal Processing Techniques

Shi-Yu Huang ( 黃錫瑜 )Jan. 6, 2006

National Tsing-Hua University, Taiwan

Acknowledgements曾昭文 楊振勳

2

Fault ModelsFault Models

Scan Chain Faults

Functional Faults Timing Faults

Setup-TimeViolation Faults

(Transition Faults)Stuck-atBridging

Slow-To-RiseFault

Slow-To-FallFault

Hold-TimeViolation Fault

3

A Stuck-At Fault In the ChainA Stuck-At Fault In the Chain

Effect: A killer of the scan-test sequence

D Q

inputpins

clock

outputpins

D Q D Q

Combinational Logic

scan-input(SI)

scan-output(SO)M

UX

MUX

MUX

scan-enable

11010100 00000000xs-a-0 ?

All-0 syndrome

4

Definition: Snapshot ImageDefinition: Snapshot Image

inputpins

clock

outputpins

Scaninput(SI)

Scanoutput(SO)

Mission Logic

00D Q

11 00

MUX

MUX

MUX

xs-a-0 11

MUX

Snapshot image: {(F1, F2, F3, F4) | (0, 1, 0, 1)}

F1 F2 F3 F4

Def: A snapshot image is the combination of flip-flop valuesat certain time instance

5

Definition: Observed ImageDefinition: Observed Image

inputpins

clock

outputpins

Scaninput(SI)

Scanoutput(SO)

Mission Logic

00D Q

11 00

MUX

MUX

MUX

xs-a-0 11

MUX

Snapshot image: {(F1, F2, F3, F4) | (0, 1, 0, 1)}Observed image: {(F1, F2, F3, F4) | (0, 0, 0, 1)}

F1 F2 F3 F4

Def: An observed image is the scanned-out version of a snapshot image.

6

Test Application: Scan-Capture-ScanTest Application: Scan-Capture-Scan

1 0 0 0

corelogic

x1011

Step 1: Scan-in an ATPG pattern

0 1 1 0

corelogic

x

0 1 1 0

corelogic

x 0010

Step 2: Capture the response to FF’s

Step 3: Scan-out and compare

SI

SO

down-stream partIs distorted

S-A-0

up-stream partwill be distorted

S-A-0

S-A-0

7

Test Application: Run-and-ScanTest Application: Run-and-Scan

Step 1: Apply a sequence of functional patterns from PI’s Setting up a snapshot image at FF’s

Step 2: Scan-out an observed image

0 1 1 0

corelogic

xS-A-0

0 1 1 0

corelogic

x 0010

SO

S-A-0

up-stream partwill be distorted

Less distorted image

TestSequence

The fault location is embedded in the observed image

8

Prior Works & Our AdvantagesPrior Works & Our Advantages

Previous works Hardware Assisted

Extra logic on the scan chain [Edirisooriya 1995] [Nayaranan 1995] [Wu 1998]

Fault Simulation Based To find a faulty circuit matching the syndromes Tightening heuristic upper & lower bounds [Kundu 1993] [Cheney 2000] [Stanley 2000] [Guo 2001][Y. Huang 2003, 2004, 2005]

Advantages of our approach (1) Use signal processing techniques (2) Fault model independent (3) More capable of handling bridging faults

9

OutlineOutline

Introduction Proposed Approach

- Test Sequence Generation

- Profile Analysis Experimental Results Conclusion

10

Signal Frequency At Flip-FlopsSignal Frequency At Flip-Flops

1

0

0

0

1

0

1st vector 2nd vector 3rd vector

0

0

First flip-flop F1: {0, 0, 0, 0} signal-1 frequency 0 (to be improved)Second flip-flop F2: {0, 1, 0, 1} signal-1 frequency 0.5 (better)

Missionlogic

Missionlogic

Missionlogic

1st frame 2nd frame 3rd frameResetState

ObservedImage

F1

F2

A good set of test sequences should make each FF as random as possible

11

Diagnostic Test Sequence SelectionDiagnostic Test Sequence Selection

1

0

1

17th

0

01st 2nd

0

0

0

0 3rd 4th

1

0

0

1 5th 6th

Selected clock cycles {1, 4, 5, 7}:

1st sequence2nd sequence

3rd sequence

4th sequence

1st sequence: {v1}2nd sequence: {v1, v2 , v3 , v4}3rd sequence: {v1, v2 , v3 , v4 , v5 }4th sequence: {v1, v2 , v3 , v4 , v5 , v6 , v7 }

reset

12

Interleaved Random-Shift SequencesInterleaved Random-Shift Sequences

The advantages of interleaved random-shift sequences: The sequence is shorter in order to randomize FF values The fault contamination is less

Shift by one bit

0

0 2nd1streset

0

1 2nd

1

0

Shift by one bit

ObservedImage

RandomVector

RandomVector

RandomVector

13

Signal ProfilingSignal Profiling

A profile is the distribution of certain statistics of the flip-flops.

Fault-free model

Faulty flip-flop

Up-stream Down-stream

0 0 0.65 0.35

0.4 0.5 0.6 0.4

corelogic

TestSequences

fault-free image

ScanShifting

0.41 0.51 0.61 0.41

corelogic

perturbed image

Failing chip

x

0.4 0.5 0.6 0.4

similardifferent

Fault-free profile

Comparing failing profile with the fault-free profile Could reveal the fault location

14

Profile AnalysisProfile Analysis

Fault-free images(say 100 of them)

Failing images(say 100 of them)

reporta ranked list

of fault locations

Derive the fault-free profile

Derive the failing profile

Derive the difference profile

Perform filtering on the difference profile

Perform edge detection to derive ranking profile

difference profile= fault-free profile ⊕ failing profile

Collected from tester

Details of filtering and edge detection are referred to the paper.

15

Example: Single Stuck-At FaultExample: Single Stuck-At Fault

Example: FIR filterScan chain: 160 flip-flopsFault injected: SA-0 @ 80-th FF

Profiling

0

0.2

0.4

0.6

0.8

1 13 25 37 49 61 73 85 97 109

121

133

145

157

Scan-input <- DFF Index -> Scan-output

Sign

al P

roba

bilit

y(%

)

Fault-free Profile Faulty Profile

Sig

nal

-1 F

req

uen

cy (

%)

Scan Input FF index Scan Output

Fault-Free Profile Failing Profile

16

Why Smoothing the Difference Why Smoothing the Difference Profile?Profile?

There are lots of ripples on the raw profiling We wish to capture the trend

Profiling difference

0

0.2

0.4

0.6

0.8

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155

DFF Index

SP (%

)

Difference profile

Scan-In Scan-Out

Sig

nal

-1 F

req

uen

cy

17

Running-Sum FilteringRunning-Sum Filtering

Notations: D[i]: The signal-1 frequency for i-th FF in Difference Profile SD[i]: The signal-1 frequency of i-th FF in Smoothed Difference Profile

SD[i] = 0.2(D[i-4]+D[i-3]+ D[i-2]+ D[i-1]+ D[i])

18

Edge DetectionEdge Detection

differenceweightscore

ji

ih

hg

gf

fx

ex

dx

cx

bx

ax

difference

weight

0

3,3,3,3,3,0,3,2,2,1,1

19

Example: Filtering & Edge DetectionExample: Filtering & Edge Detection

Profiling difference

0

0.2

0.4

0.6

0.8

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155

DFF Index

SP (%

)S

ign

al-1

Fre

qu

ency

(%

)Difference Profile

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1 13

25

37

49

61

73

85

97

109

121

133

145

157

DFF Index

Smooth Profile Ranking ProfileRanking ProfileFiltered Difference Profile

Filtering & Edge Detection

Scan Input FF index Scan Output

20

Example: Double Transition FaultsExample: Double Transition Faults

FIR: 1 chain of 160 cellsSlow-Rise @ DFF80Slow-Rise @ DFF40

Profiling

0

0.2

0.4

0.6

0.8

1

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155

Scan-input <- DFF Index -> Scan-output

SP(%

)

Fault-free Profile

Faulty Profile

Fault-Free Profile

Failing Profile

Sig

nal

-1 F

req

uen

cy (

%)

Scan Input FF index Scan Output

The difference is not as prominent here as that for stuck-at faults. However, our profile analysis still works well.

21

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

1 13 25 37 49 61 73 85 97 109

121

133

145

157

DFF Index

Example: Double Transition Faults Example: Double Transition Faults (cont’)(cont’)

Profiling Difference

0

0.1

0.2

0.3

0.4

0.5

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155

DFF Index

SP(%

)S

ign

al-1

Fre

qu

ency

(%

)

Ranking Profile

Filtered Difference Profile

Scan Input FF index Scan Output

Difference Profile

Scan Input FF index Scan Output

22

OutlineOutline

Introduction Proposed Approach Experimental Results Conclusion

23

In-House Test CasesIn-House Test Cases

Design NameSize(#

Gates)

# Scan FF’s

# of Images

Used

(1) GCD 1.5k 66 500

(2) Montgomery

Inverse4.5k 202 500

(3) Viterbi

Decoder9.5k 620 500

(4) FIR Filter 11k 160 500

We assume one scan chain for a designDiagnostic test sequences are derived by interleaved random-shift operations

24

Result (1): Single Fault in the ChainResult (1): Single Fault in the Chain

Design1st – hit index Success Rate

Stuck-At Bridge Transition Stuck-At Bridge Transition

GCD 2.28 2.21 2.13 100% 98% 100%

MON 2.96 3.14 3.56 97% 92% 96%

FIR 2.00 2.28 1.44 100% 98% 100%

VITERBI 2.43 2.69 2.13 97% 95% 94%

Average 2.42 2.58 2.32 98.5% 96% 97.5%

(Quality Metrics):(1) Success rate: The percentage of finding a fault in top-10 candidates(2) 1st-hit index: The first candidate that turns out to be a real fault.

25

Result (2): Single Fault + Faulty LogicResult (2): Single Fault + Faulty Logic

Design1st – hit index Success Rate

Stuck-At Bridge Transition Stuck-At Bridge Transition

GCD 2.16 2.35 2.35 92% 98% 97%

MON 2.15 4.43 4.43 85% 92% 91%

FIR 2.53 2.32 2.32 97% 98% 95%

VITERBI 2.54 2.85 2.85 92% 95% 92%

Average 2.35 3.03 3.03 91.3% 96% 93.75%

(Quality Metrics):(1) Success rate: The percentage of finding a fault in top-10 candidates(2) 1st-hit index: The first candidate that turns out to be a real fault.

26

ConclusionConclusion

Limitations of Existing Methods (1) More or less bound to certain fault models (2) Not suitable for bridging faults (3) Not suitable for intermittent faults

Our contributions Use signal processing techniques Free of Fault Models Good for stuck-at, transition, bridging, etc. Works well when the core logic is also faulty