diges lec10

Upload: sonia-ahmed

Post on 14-Apr-2018

229 views

Category:

Documents


0 download

TRANSCRIPT

  • 7/30/2019 DigES Lec10

    1/57

    COURSE: DIGITALELECTRONICS

    BATCH: 12ELECTRONICSDEPARTMENT OF ELECTRONICS

    MEHRAN UNIVERSITY OF ENGINEERING &

    TECHNOLOGY, PAKISTAN

    SubjectTeacher:KehkashanAsma

    AssistantProfessor

    DeptofElectronics

    MUET,PK

  • 7/30/2019 DigES Lec10

    2/57

    This lecture

    Multivibrators Astable

    Monostable

    Bistable

    555 timer IC

    Monostable operation of 555 timer

    Problems

  • 7/30/2019 DigES Lec10

    3/57

    Multivibrators (MV)

    These devices are very useful as pulsegenerating, storing & counting circuits

    There are three types of multivibrators.

    A stable Mono stable

    Bi-stable

    These multivibrators are distinguished by

    the type of stable logic conditions at theiroutput.

  • 7/30/2019 DigES Lec10

    4/57

    ECE 3450

    M. A. Jupina,

    VU, 2010

    Multivibrator CircuitsAstable Multivibrator (Clocks or Oscillators)

    Transistor circuit Schmitt-Trigger Inverter (7414)

    555 Timer

    Crystal Oscillator

    Monostable Multivibrator (One-Shots) Transistor circuit

    555 Timer

    Non-Retriggerable (74121)

    Retriggerable (74123)

    VHDL CodingBistable Multivibrator (Flip-Flops) Transistor circuit

  • 7/30/2019 DigES Lec10

    5/57

    MV using transistor circuit

    A MV is basically two stage amplifier withpositive feedback from the output of oneamplifier to the input of the other.

    This feedback is supplied in such amanner that one transistor is driven tosaturation & other to cutoff.

  • 7/30/2019 DigES Lec10

    6/57

    Astable multivibrator An Astable multivibrator produce continuous square wave

    signal at its output when power is applied. Its name is derived from its characteristics of having no

    stable state.

    Astable multivibrator is also known as free runningrelaxation oscillator.

    It has no stable state but only two quasi-stable states b/wwhich it keeps oscillating continuously of its own accord

    without any external excitation. In this circuit neither of the two transistors reaches a

    stable state.

    A stable

    multi-vibrator5V0V

  • 7/30/2019 DigES Lec10

    7/57

    When one transistor is ON, the other isOFF & they continuously switch back n

    forth at a rate depending on RC timeconstant in the circuit.

    It has two energy storing elements i-e 2

    capacitors.

  • 7/30/2019 DigES Lec10

    8/57

    Transistor circuit ofAstable MV Circuit operation:

    The circuit operation would be easy tounderstand if it remembered that due tofeed back when Q1 is ON, Q2 is OFF orwhen Q2 is ON and Q1 is OFF.

    when the power is switched ON one ofthe transistor will start conductingbefore the other because no twotransistor can be exactly alike.

    Suppose transistor Q1 start conductingbefore Q2 does. The feedback system is

    such that Q1 will be rapidly driven tosaturation and Q2 cut off . If Q1 is insaturation/ON pointA (output1) has lowvoltage, c1 is discharged hence Q2 goesin cut off because base of Q2 isconnected with it.

    As Q2 is OFF, pointB (output2) has highvoltage that will keep the Q1 saturated.

    Now slowly C1 charges, and as itreaches >=0.7v it starts putting Q2 insaturation hence now Q2 is ON & Q1 isOFF.

    PointA = high, pointB = low; this cyclerepeats.

  • 7/30/2019 DigES Lec10

    9/57

    Switching times

    T1 =0.69 R1C1 T2=0.69 R2C2 T= T1 +T2

    T= 0.69 (R1C1 + R2C2) For 50% duty cycle R1=R2=R and

    C1=C2=C T= 1.38 RC

    f= 1/T =1/1.38RC =0.7/RC f= 0.7/RC

  • 7/30/2019 DigES Lec10

    10/57

    Monostable Mutivibrators

    A Mono stable MV produces a temporary logic level voltageat output after all activity signal is applied to its input.

    Its name is derived from its characteristics having anyonestable logic level signal output. The output state of somemonostable MV in their stable state is a logic zero andsome of logic one.

    Mono stable MV has one absolutely stable state.

    It has one half stable state.

    It has one energy storing element that is capacitor

  • 7/30/2019 DigES Lec10

    11/57

    Transistor circuitof monostable MV

    Circuit operation:Initially Q2 is in saturation and Q1is in cut off.

    When the trigger is applied to baseof Q1, Q1 will turn ON and Q2 turnsoff. Therefore point B gives high

    voltage.

    When trigger is removed Q1 goesback to cut off and Q2 will be insaturation.

    It is also called one shot MMV

    T=0.69C1R2

  • 7/30/2019 DigES Lec10

    12/57

    Bi-stable Multivibrators

    Its another name is a flip-flop. Its name isderived from its characteristics of having two

    stable states output that is zero or one. Bi-stable MV can remain in a stable condition and

    produces the opposite logic state. Until all inputscauses it to output that is opposite logic leveloutput signal.

    There is no any storing element.

    It does not oscillate

    BMV

  • 7/30/2019 DigES Lec10

    13/57

    Transistor Circuitof Bi-stable MV

    Circuit operation:

    If transistor is Q1 conducting,Q2 is off. Therefore the point Bis high.

    If trigger is applied Q2 will

    turn ON, point B will be low.

    Therefore Q1 is turned off.

    Now even trigger is removedQ2 remains ON and Q1remains off.

    If trigger is applied Q1 will beturned ON and Q2 will be OFFand therefore point A will below and B will be high.

  • 7/30/2019 DigES Lec10

    14/57

    ECE 3450

    M. A. Jupina,VU, 2010

    Astable MV using schmitt trigger inverter

    (a) If input transition times are too long, a standard logicdevice-output might oscillate or change erratically; (b) alogic device with a Schmitt-trigger type of input will

    produce clean, fast output transitions.

  • 7/30/2019 DigES Lec10

    15/57

    ECE 3450

    M. A. Jupina,VU, 2010

    Schmitt-Trigger Oscillator

  • 7/30/2019 DigES Lec10

    16/57

    555 Timer

    Paul Godin

    Updated February 2008

  • 7/30/2019 DigES Lec10

    17/57

    A Versatile Device

    The 555 Timer is one of the best knownICs. The 555 is part of every experimenter's tool kit

    Capable of creating a wide variety of circuits,including:

    Oscillators with adjustable frequency and DutyCycle

    Monostable Multivibrators

    Analog to digital Converters

    Frequency Meters

    Many other applications.

    555.17

  • 7/30/2019 DigES Lec10

    18/57

    555 Timer Configurations

    In this course we will use the 555 timer in 2modes: Astable

    With some calculations, we can determine the

    values of the capacitor and the 2 resistors (Ra andRb) for astable operations.

    Monostable

    We can determine the value of the resistor and thecapacitor with a simple formula for one-shot

    operations.

    555.18

  • 7/30/2019 DigES Lec10

    19/57

    555 Layout

    Also available:556 (two-555s in one DIP package)555 in a metal can configuration

    555.19

    12

    3

    4

    8

    7

    6

    5

    Ground

    Trigger

    Output

    Reset

    Vcc

    Discharge

    Threshold

    Control

    1

    2

    34

    5

    6

    78

    Ground

    Trigger

    Output

    Reset

    Vcc

    Discharge

    Threshold

    Control

  • 7/30/2019 DigES Lec10

    20/57

    General Configuration

    Basic connections: Ground

    Vcc

    Note: some 555

    timers may functionat voltages otherthan 5 volts.

    Reset (active low)

    Output

    555.20

    1

    2

    3

    4

    8

    7

    6

    5

    Ground

    Trigger

    Output

    Reset

    Vcc

    Discharge

    Threshold

    Control

  • 7/30/2019 DigES Lec10

    21/57

    General Configuration

    Specializedconnections: Trigger monitors low voltage

    Threshold monitors high voltage

    Discharge path to ground, todischarge the capacitor

    Control specialized input filtering special applications

    555.21

    1

    2

    3

    4

    8

    7

    6

    5

    Ground

    Trigger

    Output

    Reset

    Vcc

    Discharge

    Threshold

    Control

  • 7/30/2019 DigES Lec10

    22/57

    555 Timer Operation

    555.22

  • 7/30/2019 DigES Lec10

    23/57

    Internal Operation of the 555Timer

    Understanding the internal operation ofthe 555 timer is important

    The device combines various circuit theories.

    Understanding its internal function makes iteasier to create new designs with the device.

    555.23

  • 7/30/2019 DigES Lec10

    24/57

    Comparator

    The comparator is an operational amplifier(op-amp) configuration.

    The comparator compares 2 analog voltages

    and provides a digital output.

    +

    -If V+ > V-, the output is a digital 1

    If V- > V+, the output is a digital 0

    555.24

  • 7/30/2019 DigES Lec10

    25/57

    Reference and Comparators

    The Comparatorsprovide digital logic toan SR Latch

    Comparators compare voltagelevels.

    If + is higher, output = 1If - is higher, output = 0

    A 3-resistor voltagedivider providesreference voltages

    555.25

  • 7/30/2019 DigES Lec10

    26/57

    Reference and Comparators

    Pin 8: Vccconnection

    Pin 5: Controlconnection, usedwith filter cap.

    Pin 1: Gndconnection

    Pin 6: Thresholdconnection (highComparator)

    Pin 2: Triggerconnection (lowComparator)

    555.26

  • 7/30/2019 DigES Lec10

    27/57

    Latch and Output

    The Q output controls the

    transistor (on or off).The SR Latch holdsits output states

    The transistor actslike a switch.

    The reset input can beused to enable or disablethe timer.

    The buffer has importantelectrical functions.

    555.27

  • 7/30/2019 DigES Lec10

    28/57

    Latch and OutputPin 4: Resetconnection (activelow reset)

    Pin 7:

    Dischargeconnection

    Pin 3: DigitalOutput

    555.28

  • 7/30/2019 DigES Lec10

    29/57

    555.29

  • 7/30/2019 DigES Lec10

    30/57

    + < -

    0

    - < +

    1

    Vc

    0

    1

    Animated charge cycle

    + > -

    1

    - > +

    01

    0

    Capacitor Charges via Ra and RbLatch in a set stateQ is low; Q output is highCapacitor continues to chargeLower comparator provides logiclow. Latch in hold state.Upper comparator + input isgreater than 2/3 Vcc referenceLatch receives a reset stateQ is high; Q output is lowTransistor is on and a connectionto ground is made.Capacitor begins to discharge

    555.30

  • 7/30/2019 DigES Lec10

    31/57

    Vc

    1

    01

    0+ < -

    - < +

    Animated discharge cycle

    01

    + > -

    0

    - > +

    1

    Capacitor is discharging. Q outputis low.Upper comparator + voltage lessthan reference voltage.Latch in a hold state.Lower comparator + voltage isgreater than voltage.Latch is set. Q is low.Q output is high.Transistor is off. Capacitorbegins to charge.

    555.31

  • 7/30/2019 DigES Lec10

    32/57

    Function of the Control Input (Pin5)

    Pin 5 is the control voltage connection,and is used to access the 2/3 Vcc point ofthe voltage divider. Normally, a 0.01F capacitor is connected to

    ground to provide output voltage stability. Used as an input for some applications.

    AC to pulse modulation

    voltage controlled oscillator

    555.32

  • 7/30/2019 DigES Lec10

    33/57

    Asta

    bleMultivibrator

    555.33

  • 7/30/2019 DigES Lec10

    34/57

    Oscillator Configuration

    Externally, the 555 requires an RC circuitto create the time delays required for the

    time high and the time low.

    Standard configuration requires common capacitor

    a resistor for the charge cycle

    a resistor for the discharge cycle

    555.34

    A t bl C fi ti #1

  • 7/30/2019 DigES Lec10

    35/57

    Astable Configuration #1(Standard Configuration)

    1

    23

    4

    8

    76

    5

    Ground

    Trigger

    Output

    Reset

    Vcc

    Discharge

    Threshold

    Control

    Vcc

    Ra

    Rb

    C

    Vcc

    555.35

  • 7/30/2019 DigES Lec10

    36/57

    AstableFilter Cap0.01F

    CalculatedValues

    Note: Duty Cyclemust be > 50%

    555.36

    A t bl C fi ti #1

  • 7/30/2019 DigES Lec10

    37/57

    Astable Configuration #1(Standard Configuration)

    Rb2Ra

    RbRa

    tt

    t

    DC21

    1

    C)Rb2Ra(693.

    1

    tt

    1f

    21

    CRb693.t

    C)RbRa(693.t

    2

    1

    Minimum duty cycle > 50%555.

    37

  • 7/30/2019 DigES Lec10

    38/57

    Calculations: Astable

    C)RR(693.0T

    CR693.0T

    BAH

    BL

    TH TL

    Notes:The value 0.693 is a factor associated with thecharge/discharge cycle of the 555 timer.

    Duty Cycle must be > 50%

    Time High, Time Low Set

    555.38

  • 7/30/2019 DigES Lec10

    39/57

    555.39

    Sample Calculation

    Design an oscillator with a frequency of200Hz with a duty cycle of 78%.1. Determine Period (T):

    2. Determine TH and TL:

    s005.0Hz200

    1

    F

    1T

    ms1.1s0011.0s005.0%22T

    ms9.3s0039.0s005.0%78T

    L

    H

    Time High, Time Low Set

  • 7/30/2019 DigES Lec10

    40/57

    555.40

    3. Since there are 2 variables in the TL equation, selectC:

    4. Determine RB by using the TL equation:

    7.158R

    F10R693.0ms1.1

    CR693.0T

    B

    B

    BL

    C=10F

    Sample Calculation

    Time High, Time Low Set

    S l C l l i

  • 7/30/2019 DigES Lec10

    41/57

    555.41

    5. Determine the value for RA:

    1.404R

    7.158R8.562F10)7.158R(693.0ms9.3

    C)RR(693.0T

    A

    A

    A

    BAH

    Sample Calculation

    Time High, Time Low Set

  • 7/30/2019 DigES Lec10

    42/57

    Calculations: Astable

    C)R2R(693.0

    1F

    )R2R(

    )RR(DC

    BA

    BA

    BA

    Notes:

    The value 0.693 is a factor associated with thecharge/discharge cycle of the 555 timer.

    Duty Cycle must be > 50%

    Frequency, Duty Cycle Set

    555.42

    S l D i

  • 7/30/2019 DigES Lec10

    43/57

    Sample Design

    Build an oscillator using a 555 timerwith a frequency of 72kHz at 75% D.C.Use a 100F capacitor.

    Frequency, Duty Cycle Set

    555.43

  • 7/30/2019 DigES Lec10

    44/57

    Design Solution

    1- Determine the ratio of the resistors Ra and Rb:

    2- Use the ratio in the frequency equation (substitution):

    Rb2Ra

    RbRb5.1Ra75.0RaRb5.1Ra75.0)Rb2Ra(75.0RbRa

    75.0Rb2Ra

    RbRaDC

    RbC4

    44.1

    C)Rb2Rb2(

    44.1

    C)Rb2Ra(

    44.1f

    Frequency, Duty Cycle Set

    555.44

  • 7/30/2019 DigES Lec10

    45/57

    Design Solution

    3- Solve for Rb:

    4-Solve for Ra:

    5-Use standard values (optional step):

    Ra=100k

    Rb=47k

    k50100k724

    44.1

    RbC4

    44.1kHz72

    k100Rb2Ra

    Frequency, Duty Cycle Set

    555.45

    i l i

  • 7/30/2019 DigES Lec10

    46/57

    Design Solution

    6- Calculate actual frequency and DC:

    %1Error

    757.0))k472(k100(

    )k47k100(DC

    %1.3Error

    kHz2.74

    F100))k472(k100(

    44.1f

    Frequency, Duty Cycle Set

    555.46

    D i S l ti

  • 7/30/2019 DigES Lec10

    47/57

    Design Solution

    7- Create the circuit diagram using EWB:

    555 Timer, 74.2kHz @ 75.7% D.C.

    Frequency, Duty Cycle Set

    555.47

    Mi i V l f R

  • 7/30/2019 DigES Lec10

    48/57

    Minimum Value for Ra

    The dischargetransistor causesthe capacitor todischarge toground.

    Ra must have aminimum value of25 to prevent ashort circuit of thepower supplythrough thedischarge transistor.

    Minimum Value

    555.48

    I Cl P ti P bl

  • 7/30/2019 DigES Lec10

    49/57

    In-Class Practice Problem

    Design an oscillator with a frequency of500Hz and a duty cycle of 80%. Use a 10FCapacitor. Calculate using each of theequation sets.

    555.49

  • 7/30/2019 DigES Lec10

    50/57

    Other Astable Configurations

    555.50

  • 7/30/2019 DigES Lec10

    51/57

    Astable Configuration#2Rb must be < .5 Ra 555.

    51

  • 7/30/2019 DigES Lec10

    52/57

    Astable Configuration #3555.

    52

  • 7/30/2019 DigES Lec10

    53/57

    Design Exercises

    555.53

  • 7/30/2019 DigES Lec10

    54/57

    Design Exercises

    1. Using a 555 timer, design an oscillatorwith an output of 6Hz with a duty cycle

    of 60%. Use a 100F capacitor. Build inEWB.

    2. Using a 555 timer, design an oscillatorwith an output of 10KHz with a dutycycle of 50%. Use a 3.3F Capacitor.Build in EWB.

    555.54

  • 7/30/2019 DigES Lec10

    55/57

    Monostable operation of 555Timer IC

  • 7/30/2019 DigES Lec10

    56/57

    Operation: Initially (before the trigger is applied, Vout is low,

    shorting pin7 to ground and discharging capacitor.

    Pin2 is normally held high by the R resistor (10 k) pull-up resistor. To trigger the one shot, a negative goingpulse less than Vcc is applied to pin2.

    The trigger forces the lower comparator high, which setsa flip-flop, making Vout high and opening the dischargepin pin7.

    Now the capacitor is free to charge from 0v up to Vcc viaRA.

    When Vc crosses the threshold of Vcc, the uppercomparator goes high, representing the flip-flop, makingVout low, and shorting the discharge transistor.

    The capacitor discharges rapidly to zero volt and the oneshot is held in the stable (Vout=low) until another trigger

    is applied.tw = 1.10 RAC

  • 7/30/2019 DigES Lec10

    57/57

    Homework: related exercises from williamklietz, floyd, tocci.