digital systems - e-learningforum.com 02, 2012 · dr. kamel a. m. soliman [email protected]...

1 Dr. Kamel A. M. Soliman

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Digital Systems

Course Code: 124

Dr. Kamel abd Elfattah Mohamed Soliman

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Course Instructor

Dr. Kamel abd Elfattah Mohamed

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Tel: 1330

1330

office hours Monday :10:00-12:30 Thrusday : 10:00 - 12:30


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CONTENTS

Chapter 1: Introduction to Digital Systems

Chapter 2: Binary Number System and Convertion

Chapter 3: Boolean Algebra

Chapter 4: Logic Gates

Chapter 5: Logic Families

Chapter 6: Logic Circuits

Chapter 7: Digital Devices

Appendix

Assignments


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Topic 1

Basic logic concepts: logic states, number systems, Boolean algebra,

basic logical operations, gates and truth tables. Combinational logic:

minimization techniques, multiplexers and de-multiplexers, encoders,

decoders, adders and subtractors, look-ahead carry, comparators,

programmable logic arrays and memories, design with MSI, logic families,

tri-state devices, CMOS and TTL logic interfacing.

Sequential logic: Flips-flops, monostable, multivibrators, latches and

registers, counters, shift registers. Analog to digital conversion, digital to

analog conversion.

Topic 2

This is core course of Electrical and Elecronic Engineering and Information

System Engineering that presents basic tools for the design of digital circuits. It serves

as a building block in many disciplines that utilize data of digital nature like digital

control, data communication, digital computers etc. The goal of this course is to;

1. Perform arithmetic operations in many number systems.

2. Manipulate Boolean algebraic structures.

3. Simplify the Boolean expressions using Karnaugh Map.

4. Amplement the Boolean Functions using NAND and NOR gates.

5. Analyze and design various combinational logic circuits.

6. Anderstand the basic functions of flip-flops.

7. Anderstand the importance of state diagram representation of sequential circuits.

8. Analyze and design clocked sequential circuits.


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This course makes significant contributions to the following program outcomes:

1. An ability to apply knowledge of mathematics, science, and engineering,

2. An ability to design and conduct experiments, as well as to analyze and interpret

data,

3. An ability to design a system, component , or process to meet desired needs

within realistic constraints

4. An ability to identify, formulate, and solve engineering problems,

5. An ability to use the techniques, skills, and modern engineering tools necessary

for engineering practice.

Course Objectives :

A student who successfully fulfills the course requirements will have

demonstrated an ability to:

o Perform artihmetic operaions in many number sytems

o Manipulate Boolean algebraic structures

o Analyze and design various combinational logic circuits

o Anlayze and design clocked sequential circuits

COURSE DESCRIPTION File

o Basic logic concepts: logic states, number systems, Boolean algebra, basic

logical operations, gates and truth tables. Combinational logic: minimization

techniques, multiplexers and de-multiplexers, encoders, decoders, adders and

subtractors, look-ahead carry, comparators, programmable logic arrays and

memories, design with MSI, logic families, tri-state devices, CMOS and TTL

logic interfacing.

http://opencourses.emu.edu.tr/mod/resource/view.php?id=8


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o Sequential logic: Flips-flops, monostable, multivibrators, latches and registers,

counters, shift registers. Analog to digital conversion, digital to analog

conversion.

ASSIGNMENTS

The homework assignments:

The first page must be the title page. The title page must contain the name,

surname and the number of the student. It should also contain the due date.

Please also include a table of points for each problem.

The solution must contain all the necessary steps.

Remember that you must turn in the homework on the assigned days. Late

submissions will not be accepted and graded.

Important Note:

You may discuss the homework problems with your friends for exchanging

general ideas, but you may not copy from one another. You may also not give any

parts of your homework to other students to look at. Any students violating these rules

or committing any other acts of academic dishonesty WILL be turned over to the

disciplinary committee for disciplinary action.

Textbook:

M. M. Mano, M. D. Ciletti, Digital Design ( Fourth Edition), Prentice-Hall 2007.


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References:

1. Fredrick J. Hill & Gerald R. Peterson, Introduction to Switching Theory &

Logical Design, John Wiley & Sons 1981

2. Thomas L. Floyd, Digital Fundamentals , Merrill, imprint of Macmillan

Publishing Company New York, 1994.

3. M. M. Mano & C. R. Kime, Logic and Computer Design Fundamentals,

Prentice-Hall 2001.

4. B. Stephen & V. Zvonko, Fundamentals of Digital Logic with VHDL Design

with CD-ROM, McGraw- Hill 2000


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Chapter 1

Introduction to Digital Systems

Digital systems are concerned with digital signals

Digital signals can take many forms

Here we will concentrate on binary signals since these are the most common

form of digital signals

o Can be used individually

Perhaps to represent a single binary quantity or the state of a single

switch

o Can be used in combination

To represent more complex quantities

Digital Technology:

The term digital is derived from the way computer perform operations by

counting digits.

Today, digital tech is applied in a wide range of areas.

The tech has progressed from vacuum-tube to discrete transistors to complex

ICs.

Digital and Analog Quantities:

2 categories of electronic circuits:

o Analog

o Digital

Analog quantity = continuous values

Digital quantity = a discrete set of values

Analog versus Digital:

Analog systems process time-varying signals that can take on any value across a

continuous range of voltages (in electrical/electronics systems).

Digital systems process time-varying signals that can take on only one of two

discrete values of voltages (in electrical/electronics systems).

o Discrete values are called 1 and 0 (ON and OFF, HIGH and LOW, TRUE

and FALSE, etc.)


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Analog Quantity:

Most things in nature analog form

o Temperature, pressure, distance, etc

Smooth, continuous curve like this:

Digital Quantity:

Sampled-value representation (quantization)

Each dot can be digitized as a digital code (consists of 1s and 0s)

Representing Information Electronically:

o “Analog electronics” deals with non-discrete values

o “Digital electronics” deals with discrete values

Benefits of Digital over Analog:

Reproducibility

Not effected by noise means quality

Ease of design

Data protection

Programmable


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Speed

Economy

Digital Revolution:

Digital systems started back in 1940s.

Digital systems cover all areas of life:

o still pictures

o digital video

o digital audio

o telephone

o traffic lights

o Animation

Digital Advantages:

Digital data can be processed and transmitted more efficiently and reliably than

analog data.

Digital data has a great advantage when storage is necessary.

Let‟s talk about digital music…

Digital Music:

The media is very compact but higher-density (and counting):

o CDs

o Memory cards

No more bulky and noise-prone media like cassette tape


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Binary Digits, Logic Levels, and Digital Waveforms:

Binary Digits:

Binary system (either 0 or 1)

o Bit (comes from binary digit)

Digital circuits:

o 1 represents HIGH voltage

o 0 represents LOW voltage

Groups of bits (combinations of 0s and 1s) are called codes

o Being used to represent numbers, letters, symbols, (i.e. ASCII code),

instructions, and etc.

Logic Levels:

The voltages used to represent a 1 and 0 are called logic levels.

o Ideally, there is only HIGH (1) and LOW (0).

o Practically, there must be thresholds to determine which one is HIGH or

LOW or neither of them.

CMOS

o (2V to 3.3V HIGH)

o (0V. To 0.8V LOW)


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Digital Waveforms:

Digital waveforms change between the LOW and HIGH levels. A positive going pulse

is one that goes from a normally LOW logic level to a HIGH level and then back

again. Digital waveforms are made up of a series of pulses.

At t0 leading edge, at t1 trailing edge

Pulse Definitions:

Actual pulses are not ideal but are described by the rise time, fall time, amplitude, and

other characteristics.


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Periodic Pulse Waveforms:

Periodic pulse waveforms are composed of pulses that repeats in a fixed interval called

the period. The frequency is the rate it repeats and is measured in hertz.

The clock is a basic timing signal that is an example of a periodic wave.

Pulse Definitions:

In addition to frequency and period, repetitive pulse waveforms are described by the

amplitude (A), pulse width (tW) and duty cycle. Duty cycle is the ratio of tW to T.


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Waveform Characteristics:

Waveforms = series of pulses (called pulse train)

o Periodic

Period (T) = T1 = T2 = T3 = … = Tn

Frequency (f) = 1/T

o Nonperiodic

Duty Cycle:

Ratio of the pulse width (tw) to the period (T)

Duty cycle = ( tw / T ) x 100%

Example:

From a portion of a periodic waveform (as shown) determine:

a) Period

b) Frequency

c) Duty cycle


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Waveform & Binary Information:

Data Transfer:

Binary data are transferred in two ways:

o Serial – bits are sent one bit at a time

o Parallel – all the bits in a group are sent out on separate lines at the same

time (one line for each bit)

Serial over Parallel

o Advantage: less transmission line

o Disadvantage: takes more time

Serial and Parallel Data:

Data can be transmitted by either serial transfer or parallel transfer.

Basic Logic Functions:


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1. Compared to analog systems, digital systems

a. are less prone to noise

b. can represent an infinite number of values

c. can handle much higher power

d. all of the above

2. The number of values that can be assigned to a bit are:

a. one

b. two

c. three

d. ten

3. The time measurement between the 50% point on the leading edge of a pulse to

the 50% point on the trailing edge of the pulse is called the

a. rise time

b. fall time

c. period

d. pulse width

4. The time measurement between the 90% point on the trailing edge of a pulse to

the 10% point on the trailing edge of the pulse is called the


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a. rise time

b. fall time

c. period

d. pulse width

5. The reciprocal of the frequency of a clock signal is the

a. rise time

b. fall time

c. period

d. pulse width

6. If the period of a clock signal is 500 ps, the frequency is:

a. 20 MHz

b. 200 MHz

c. 2 GHz

d. 20 GHz

7. AND, OR, and NOT gates can be used to form:

a. storage devices

b. comparators

c. data selectors

d. all of the above

Answers:

1. a

2. b

3. d

4. b

5. c

6. c

7. d


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Chapter 2

Binary Numbers

Outline of Chapter 2:

2.1 Binary Numbers

2.2 Number-base Conversions

2.3 Octal and Hexadecimal Numbers

2.4 Complements

2.5 Signed Binary Numbers

2.6 Binary Codes

2.7 Binary Storage and Registers

2.1 Binary Digital Signal:

An information variable represented by physical quantity.

For digital systems, the variable takes on discrete values.

o Two level, or binary values are the most prevalent values.

Binary values are represented abstractly by:

o Digits 0 and 1

o Words (symbols) False (F) and True (T)

o Words (symbols) Low (L) and High (H)

o And words On and Off

Binary values are represented by values or ranges of values of physical

quantities.


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Number Systems and Binary Arithmetic:

Most number systems are order dependent

Decimal

123410 = (1 103) + (2 10

2) + (3 10

1) + (4 10

0)

Binary

11012 = (1 23) + (1 2

2) + (0 2

1) + (1 2

0)

Octal

1238 = (1 83) + (2 8

2) + (3 8

1)

Hexadecimal

12316 = (1 163) + (2 16

2) + (3 16

1)

here we need 16 characters – 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

The Power of 2:


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Binary:

Decimal is base 10 and has 10 digits: 0,1,2,3,4,5,6,7,8,9

Binary is base 2 and has 2 digits:

0,1

For a number to exist in a given base, it can only contain the digits in that

base, which range from 0 up to (but not including) the base.

What bases can these numbers be in? 122, 198, 178, G1A4

Bases Higher than 10:

How are digits in bases higher than 10 represented?

With distinct symbols for 10 and above.

Base 16 has 16 digits:

0,1,2,3,4,5,6,7,8,9,A,B,C,D,E, and F

Binary Numbers and Computers: Computers have storage units called binary digits or bits.

Low Voltage = 0

High Voltage = 1 all bits have 0 or 1


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Binary and Computers:

Byte : 8 bits

The number of bits in a word determines the word length of the computer,

but it is usually a multiple of 8

32-bit machines

64-bit machines etc.

Addition:


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Column Addition:

Another example:

Remember that there are only 2 digits in binary, 0 and 1

1 + 1 is 0 with a carry


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Binary Subtraction:

Borrow a “Base” when needed:

Another example:


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Remember borrowing? Apply that concept here:

Binary Multiplication:

Bit by bit:


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Complements:

• 1‟s Complement (Diminished Radix Complement)

– All „0‟s become „1‟s

– All „1‟s become „0‟s

–

Example: (10110000)2

(01001111)2


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2.2 Number Base Conversions:

Decimal (Integer) to Binary Conversion:

• Divide the number by the „Base‟ (=2)

• Take the remainder (either 0 or 1) as a coefficient

• Take the quotient and repeat the division

Example: (13)10


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Decimal ‒to‒ Binary Conversion:

The Process : Successive Division

a) Divide the Decimal Number by 2; the remainder is the LSB of Binary

Number .

b) If the quotation is zero, the conversion is complete; else repeat step (a)

using the quotation as the Decimal Number. The new remainder is the

next most significant bit of the Binary Number.

Example:

Convert the decimal number 610 into its binary equivalent.

Example:


Solution:


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Example2:


Solution:

More Examples:

Solution:


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Binary ‒to‒ Decimal Process:

The Process : Weighted Multiplication

a) Multiply each bit of the Binary Number by it corresponding bit-weighting

factor (i.e. Bit-0→20=1; Bit-1→2

1=2; Bit-2→2

2=4; etc).


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b) Sum up all the products in step (a) to get the Decimal Number.

Example 1:

Convert the decimal number 01102 into its decimal equivalent.

Example 2: Convert the binary number 100102 into its decimal equivalent.

Example 3: Convert the binary number 01101012 into its decimal equivalent.


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More Examples:

Example 4:

What is the decimal equivalent of the binary number 1101110?


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Decimal (Fraction) to Binary Conversion:

Multiply the number by the „Base‟ (=2)

Take the integer (either 0 or 1) as a coefficient

Take the resultant fraction and repeat the division

Example: (0.625)10


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Summary & Review:

a) Divide the Decimal Number by 2; the remainder is the LSB of Binary

Number .

b) If the Quotient Zero, the conversion is complete; else repeat step (a) using

the Quotient as the Decimal Number. The new remainder is the next

most significant bit of the Binary Number.


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a) Multiply each bit of the Binary Number by it corresponding bit-weighting

factor (i.e. Bit-0→20=1; Bit-1→2

1=2; Bit-2→2

2=4; etc).

b) Sum up all the products in step (a) to get the Decimal Number.

Counting in Binary/Octal/Decimal:


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Converting Binary to Octal:

Mark groups of three (from right)

Convert each group

10101011 is 253 in base 8


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Example:

Converting Octal to Decimal:

What is the decimal equivalent of the octal number 642?


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Decimal to Octal Conversion:

Example: (175)10

Example: (0.3125)10

Problem:

What is 1988 (base 10) in base 8?


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Converting Hexadecimal to Decimal:

What is the decimal equivalent of the hexadecimal number DEF?

Remember, the digits in base 16 are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

Binary − Hexadecimal Conversion:

Mark groups of four (from right)

Convert each group

10101011 is AB in base 16

Octal − Hexadecimal Conversion:

Example:


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Decimal, Binary, Octal and Hexadecimal:

Decimal Binary Octal Hex

00 0000 00 0

01 0001 01 1

02 0010 02 2

03 0011 03 3

04 0100 04 4

05 0101 05 5

06 0110 06 6

07 0111 07 7

08 1000 10 8

09 1001 11 9

10 1010 12 A

11 1011 13 B

12 1100 14 C

13 1101 15 D

14 1110 16 E

15 1111 17 F


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1. For the binary number 1000, the weight of the column with the 1 is

a. 4

b. 6

c. 8

d. 10

2. The 2‟s complement of 1000 is

a. 0111

b. 1000

c. 1001

d. 1010

3. The fractional binary number 0.11 has a decimal value of

a. ¼

b. ½

c. ¾

d. none of the above

4. The hexadecimal number 2C has a decimal equivalent value of

a. 14

b. 44

c. 64


5. Assume that a floating point number is represented in binary. If the sign bit is 1, the

a. number is negative

b. number is positive

c. exponent is negative

d. exponent is positive

6. When two positive signed numbers are added, the result may be larger that the size

of the original numbers, creating overflow. This condition is indicated by

a. a change in the sign bit


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b. a carry out of the sign position

c. a zero result

d. smoke

7. The number 1010 in BCD is

a. equal to decimal eight

b. equal to decimal ten

c. equal to decimal twelve

d. invalid

Answers:

1. c

2. b

3. c

4. b

5. a

6. a

7. D


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Chapter 3

Boolean Algebra

Chapter Objectives:

Understand the relationship between Boolean logic and digital computer

circuits.

Learn how to design simple logic circuits.

Understand how digital circuits work together to form complex computer

systems.

Boolean Addition:

Boolean Multiplication:


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Commutative Laws:

Associative Laws:


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Distributive Law:

Rules of Boolean Algebra:


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Summary:


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Boolean identities:

Boolean laws:

Basic Boolean Identities:

• As with algebra, there will be Boolean operations that we will want to simplify

– We apply the following Boolean identities to help

• For instance, in algebra, x = y * (z + 0) + (z * 0) can be simplified

to just x = y * z


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DeMorgan’s Theorem:


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Boolean Analysis of Logic Circuits:


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Example on DeMorgan’s Theorem:

Simplify, simplify:

• These properties (Laws and Theorems) can be used to simplify equations to

their simplest form.

– Simplify F=X‟YZ+X‟YZ‟+XZ

Affect on implementation:

• F = X‟YZ + X‟YZ‟ + XZ

• Reduces to F = X‟Y + XZ


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Other examples:

• Examples:

1. X + XY = X·1 + XY = X(1+Y) = X·1 = X

2. XY+XY‟ = X(Y + Y‟) = X·1 = X

3. X+X‟Y = (X+X‟)(X+Y) = 1· (X+Y) = X+Y

4. X· (X+Y)=X·X+X·Y= X+XY=X(1+Y)=X·1=X

5. (X+Y) ·(X+Y‟) =XX+XY‟+XY+YY‟=

= X+XY‟+XY+0=X(1+Y‟+Y)=X·1=X

by a slightly different reduction

6. X(X‟+Y) = XX‟+XY = 0 + XY = XY

SOP and POS forms:

SOP Standard form:


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POS Standard form:

Karnaugh maps:


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EX 1: Simplify the following output using Karnaugh maps


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EX 9: Simplify the following circuit using Karnaugh maps and draw

its equivalent circuit

The simplified circuit of the previous Example


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1. The associative law for addition is normally written as

a. A + B = B + A

b. (A + B) + C = A + (B + C)

c. AB = BA

d. A + AB = A

2. The Boolean equation AB + AC = A(B+ C) illustrates

a. the distribution law

b. the commutative law

c. the associative law

d. DeMorgan‟s theorem

3. The Boolean expression A . 1 is equal to

a. A

b. B

c. 0

d. 1

4. The Boolean expression A + 1 is equal to

a. A

b. B

c. 0

d. 1

5. The Boolean equation AB + AC = A(B+ C) illustrates

a. the distribution law

b. the commutative law

c. the associative law

d. DeMorgan‟s theorem


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6. A Boolean expression that is in standard SOP form is

a. the minimum logic expression

b. contains only one product term

c. has every variable in the domain in every term


7. Adjacent cells on a Karnaugh map differ from each other by

a. one variable

b. two variables

c. three variables

d. answer depends on the size of the map

8. The minimum expression that can be read from the Karnaugh map shown is

a. X = A

b. X = A

c. X = B

d. X = B

9. The minimum expression that can be read from the Karnaugh map shown is

a. X = A

b. X = A

c. X = B

d. X = B


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Answers:

1. b

2. c

3. a

4. d

5. a

6. c

7. a

8. a

9. d


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Chapter 4

Logic Gates

CONTENTS:

4-1 Binary Quantities and Variables

4-2 Logic Gates

4-2-1 The Inverter

4-2-2 The AND Gate

4-2-3 The OR Gate

4-2-4 The NAND Gate

4-2-5 The NOR Gate

4-2-6 The Exclusive-OR and Exclusive-NOR Gates

4-2-7 Fixed-Function Logic: IC Gates

4-2-8 Troubleshooting

4-2-9 Programmable Logic

4.1 Binary Quantities and Variables:

A binary quantity is one that can take only 2 states


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A binary arrangement with two switches in series

A binary arrangement with two switches in parallel

Three switches in series

Three switches in parallel


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A series/parallel arrangement

Representing an unknown network


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4.2 Logic Gates:

The building blocks used to create digital circuits are logic gates

There are three elementary logic gates and a range of other simple gates

Each gate has its own logic symbol which allows complex functions to be

represented by a logic diagram

The function of each gate can be represented by a truth table or using Boolean

notation

4.2.1The NOT gate (or inverter)

Standard logic symbols for the inverter:

Inverter operation with a pulse input:


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Timing diagram:

Example:

The inverter complements an input variable:

Example of a 1’s complement circuit using inverters:


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A logic buffer gate:

4.2.2 The AND gate


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Standard logic symbols for the AND gate showing two inputs:

All possible logic levels for a 3-input AND gate:

Example of pulsed AND gate operation with a timing diagram showing input and

output relationships.


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Example:

Example:

Example:


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Boolean expressions for AND gates with two, three, and four inputs.

Application Examples:

The AND Gate as an Enable/Inhibit Device

An AND gate performing an enable/inhibit function for a frequency

counter.

A Seat Belt Alarm System

A simple seat belt alarm circuit using an AND gate.


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4.2.3 The OR Gate

Standard logic symbols for the OR gate showing two inputs

All possible logic levels for a 3-input OR gate.

Open file F03-18 to verify OR gate operation.


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Example of pulsed OR gate operation with a timing diagram showing input and

output time relationships.


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Boolean expressions for OR gates with two, three, and four inputs.


A simplified intrusion detection system using an OR gate.


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4.2.4 The NAND gate

Standard NAND gate logic symbols

Operation of a 3-input NAND gate:

Open file F03-26 to verify NAND gate operation.


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Standard symbols representing the two equivalent operations of a NAND

gate.


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EX. (1):

EX. (2):


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EX. (3):

4.2.5 The NOR Gate

Standard NOR gate logic symbols

Operation of a 3-input NOR gate:

Open file F03-34 to verify NOR gate operation.


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Standard symbols representing the two equivalent operations of a NOR

gate.


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EX. (1):

EX. (2):

4.2.6 Exclusive-OR

Standard logic symbols for the exclusive-OR gate.


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All possible logic levels for an exclusive-OR gate:

Open file F03-42 to verify XOR gate operation.

4.2.7 Exclusive-NOR

Standard logic symbols for the exclusive-NOR gate.


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All possible logic levels for an exclusive-NOR gate:

Open file F03-45 to verify XNOR gate operation.

Examples of pulsed exclusive-OR gate operation.

EX. (1):

EX. (2):


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2-bit adder An XOR gate used to add two bits.

4.2.8 Multiple Inputs

Extension to multiple inputs

o A gate can be extended to multiple inputs.

If its binary operation is commutative and associative.

o AND and OR are commutative and associative.

OR

x+y = y+x

(x+y)+z = x+(y+z) = x+y+z

AND

xy = yx

(x y)z = x(y z) = x y z

NAND and NOR are commutative but not associative → they are not extendable


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Figure 4.6 Demonstrating the nonassociativity of the NOR operator;

(x ↓ y) ↓ z ≠ x ↓(y ↓ z)

- Multiple NOR = a complement of OR gate, Multiple NAND

= a complement of AND.

- cascaded NAND operations = sum of products.

- The cascaded NOR operations = product of sums.

Figure 4.7 Multiple-input and cascated NOR and NAND gates

- The XOR and XNOR gates are commutative and associative.

- Multiple-input XOR gates are uncommon?

- XOR is an odd function: it is equal to 1 if the inputs variables have an odd

number of 1's.

Figure 4.8 3-input XOR gate


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4.2.9 Positive and Negative Logic

Positive and Negative Logic

o Two signal values <=> two logic values

o Positive logic: H=1; L=0

o Negative logic: H=0; L=1

Consider a TTL gate

o A positive logic AND gate

o A negative logic OR gate

o The positive logic is used in this book

Figure 4.9 Signal assignment and logic polarity

Figure 4.10 Demonstration of positive and negative logic


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4.2.10 Integrated Circuits

Level of Integration:

An IC (a chip)

Examples:

o Small-scale Integration (SSI): < 10 gates

o Medium-scale Integration (MSI): 10 ~ 100 gates

o Large-scale Integration (LSI): 100 ~ xk gates

o Very Large-scale Integration (VLSI): > xk gates

VLSI

o Small size (compact size)

o Low cost

o Low power consumption

o High reliability

o High speed

Logic Families:

The characteristics of digital logic families

o Fan-out: the number of standard loads that the output of a typical gate can

drive.

o Power dissipation.

o Propagation delay: the average transition delay time for the signal to

propagate from input to output.

o Noise margin: the minimum of external noise voltage that caused an

undesirable change in the circuit output.

The characteristics of digital logic families

o Fan-out: the number of standard loads that the output of a typical gate can

drive.

o Power dissipation.

o Propagation delay: the average transition delay time for the signal to

propagate from input to output.

o Noise margin: the minimum of external noise voltage that caused an

undesirable change in the circuit output.

CAD:

CAD – Computer-Aided Design

o Millions of transistors

o Computer-based representation and aid

o Automatic the design process

o Design entry


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Schematic capture

HDL – Hardware Description Language

- Verilog, VHDL

o Simulation

o sicPhyal realization

- ASIC, FPGA, PLD

Chip Design:

Why is it better to have more gates on a single chip?

o Easier to build systems

o Lower power consumption

o Higher clock frequencies

What are the drawbacks of large circuits?

o Complex to design

o Chips have design constraints

o Hard to test

Need tools to help develop integrated circuits

o Computer Aided Design (CAD) tools

o Automate tedious steps of design process

o Hardware description language (HDL) describe circuits

o VHDL (see the lab) is one such system

4.2.11 Fixed-Function Logic: IC Gates

Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin

numbers and basic dimensions.


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Pin configuration diagrams for some common fixed-function IC gate

configurations.

Logic symbols for hex inverter (04 suffix) and quad 3-input NAND (00 suffix).

The symbol applies to the same device in any CMOS or TTL series.

Performance Characteristics and Parameters:

Propagation Delay Time tP

o tPHL

o tPLH

DC Supply Voltage (Vcc)

Power Dissipation PD

o ICCL, ICCH


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o PD = Vcc(ICCL＋ICCH)/2

Input and Output Logic Levels

o VIL: the LOW level input voltage for a logic gate

o VIH : the HIGH level input voltage for a logic gate

o VOL : the LOW level output voltage for a logic gate

o VOH : the HIGH level output voltage for a logic gate

Speed-Power Product (SPP)

o SPP = tPPD

Fan-Out/ Fan-In (Loading)

The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate

inputs.


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The partial data sheet for a 74LS00

The effect of an open input on a NAND gate.


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4.2.12 Troubleshooting

Troubleshooting a NAND gate for an open input with a logic pulser and

probe.

Troubleshooting a NOR gate for an open output with a logic pulser and

probe.

Troubleshooting a NAND gate for an open input with a logic pulser and

probe.


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An example of a basic programmable OR array.

An example of a basic programmable AND array.

Block diagram of a PROM (programmable read-only memory).


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Block diagram of a PLA (programmable logic array).

Block diagram of a PAL (programmable array logic).

Block diagram of a GAL (generic array logic).


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Selected Key Terms:


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Answers:

1. c

2. b

3. a

4. a

5. d

6. b

7. c

8. d

9. d


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Chapter 5

Logic Families

Logic Family Definition:

A circuit configuration or approach used to produce a type of digital integrated

circuit.

Consequence: different logic functions, when fabricated in the form of an IC

with the same approach, or in other words belonging to the same logic family,

will have identical electrical characteristics.

The set of digital ICs belonging to the same logic family are electrically

compatible with each other.

Logic Family:

A collection of different IC‟s that have similar circuit characteristics (Q)

The circuit design of the basic gate of each logic family is the same

The most important parameters for evaluating and comparing logic families

include :

o Logic Levels

o Power Dissipation

o Propagation delay

o Noise margin

o Fan-out ( loading )

Digital integrated circuits are classified not only by their complexity or logical

operation, but also by the specific circuit technology to which they belong.


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A logic family is a collection of different integrated-circuit chips that have

similar input, output, and internal circuit characteristics, but they perform

different logic functions (AND, OR, NOT, etc.).

Example Logic Families:

General comparison or three commonly available logic families.

TTL TECHNOLOGY:

– Most famous IC family


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– It compromise between speed and power consumption.

– Including, low power and high speed TTL.

– TTL/LS is faster and uses 80% less power.

– The circuit speed is increased by reducing the values of the resistors.

– It is referred to as 74xx or 54xx series.

Operating ranges:

High-speed TTL (54H/74H): – Propagation delay is 6ns.

– Power dissipation is 22.5 mw per gate.

–

Low-power TTL (54L/74L): – Propagation delay time is 35ns.

– Power dissipation is 1mw per gate.

– Used in portable battery.

Schottky TTL (54S/74S): – Employs Schottky transistor.

– Propagation delay time is 3ns.

– Power dissipation is 20 mw per gate.

Advanced Schottky TTL (54AS/74AS) • Delay time is 1.5ns.

• Power dissipation is 20 mw per gate.

• Used for high speed applications.


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Low power Schottky TTL (54LS/74LS):


– Power dissipation is 2mw per gate.

– Minimize power dissipation.

Advanced low power Schottky (74ALS):


– Power dissipation is 1mw.

Tri-state TTL (TSL):

– It has a control input.

Standard Logic Gates:


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Various series of the TTL Logic family:

Operating Requirements:

– Vcc must not exceed 5.25 Volt.

– Input signal must never exceed Vcc, and fall below (GND).

– If an input is H, connect it to Vcc.

– If an input is L, connect it to (GND).

– Connect unused AND/NAND/OR inputs to a used input of the same chip.

– Force output of unused gated H to save current

– Use at least one decoupling capacitor (0.01-0.1 µF) for every 5-15 gate

packages .

– Avoid long wires within circuits.

– If the power supply is not on the circuit board.

o Connect a 1-10µf capacitor across the power leads.

MOS/CMOS Technology:

It is popular because of:

– Their low power dissipation.

– Their ability to operate over a wide supply voltage range.

Major advantage:

- The power dissipation is small compared to other circuits.

CMOS inverter approach the ideal switch because of:

– Small power dissipation.


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– Small volt drop across the ON transistor

– High input impedance.

Operating ranges:

Operating Requirements:

Input voltage should not exceed VDD.

Avoid slowly rising and falling input signals.

All unused input must be connected to VDD(+), or VSS(GND).

Never connect an input signal to a CMOS circuit when the power is OFF.

Observe handling precautions.

Various series of the CMOS Logic family:

ECL Technology:

• The storage time of saturation transistor is a major or limitation to the switching

speed of logic circuit.


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• In (ECL), maintaining the transistors in unsaturated condition.

– This eliminate storage time.

– Result in logic gates, which switch very fast.

– Storage time is the time required to drive a transistor out of saturation.

Operating ranges:

SSI Devices: (Scientific Symbol Identification)

– Each package contains a code identifying the package


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1. Define the meaning of the following integrated circuit part number:

MC 74ALS08P6?

2. What is the difference between commercial and military TTL logic families?

3. Compare between 74L and 40S integrated circuits for:

a) Logic family - Propagation delay time - Power dissipation

4. Draw the symbols of schottky diode and schottky transistor?

5. What are the operating requirements for TTL logic family?

6. Why MOS/CMOS technology is popular?

7. What is the major advantage of MOS/CMOS technology?

8. What are the operating requirements for MOS/CMOS logic family?

9. What are the operating ranges (temperature and power supply) for

MOS/CMOS technology?


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Chapter 6

LOGIC CIRCUITS

CONTENTS: – Drawing and Analysing Logic Circuits

– Universal Gates

– Combinatorial Logic

– SOP and NAND Circuits

– POS and NOR Circuits

– Programmable Logic Array

Drawing and Analysing Logic Circuits:

Fan-in: the number of inputs of a gate.

Gates may have fan-in more than 2.

o Example: a 3-input AND gate

Given a Boolean expression, we may implement it as a logic circuit.

Example: F1 = xyz' (note the use of a 3-input AND gate).

Example:

F2 = x + y'z


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Example:

F3 = xy' + x'z

ANALYSING LOGIC CIRCUITS:

– Given a logic circuit, we can analyse it to obtain the logic expression.

– Example: Given the logic circuit below, what is the Boolean expression of F4?

F4 = ?

UNIVERSAL GATES:

AND/OR/NOT gates are sufficient for building any Boolean function.

We call the set {AND, OR, NOT} a complete set of logic.

However, other gates are also used:

o Usefulness (eg: XOR gate for parity bit generation)

o Economical

o Self-sufficient (eg: NAND/NOR gates)


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NAND GATE:

– {NAND} is a complete set of logic.

– Proof: Implement NOT/AND/OR using only NAND gates.

NOR GATE:

– {NOR} is a complete set of logic.

– Proof: Implement NOT/AND/OR using only NOR gates.

SOP and NAND Circuits: (SOP: Sum-of-Product)


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An SOP expression can be easily implemented using

o 2-level AND-OR circuit

o 2-level NAND circuit

Example: F = AB + C'D + E

o Using 2-level AND-OR circuit.

Example:

F = AB + C'D + E

– Using 2-level NAND circuit

POS and NOR Circuits: (POS: Product of Sums)

A POS expression can be easily implemented using


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o 2-level OR-AND circuit

o 2-level NOR circuit

Example: G = (A+B) (C'+D) E

o Using 2-level OR-AND circuit

Example:

G = (A+B) (C'+D) E

– Using 2-level NOR circuit


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Circuit Equivalence:

The Majority Function:

M = f (A, B, C)

M = ABC + ABC + ABC + ABC

The Majority Function: M = f (A, B, C)



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HARDWARE:


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INTEGRATED CIRCUIT (IC) CHIP:

Example: 74LS00

Combinatorial Logic:

Many inputs and many outputs

Outputs are uniquely determined by inputs


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Absence of memory elements

Basic combinatorial circuits

o Multiplexers

o Demultiplexers

o Decoders

o Comparators

Multiplexer:

Decoder:


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Comparator:

Programmable Logic Array:

A programmable integrated circuit – implements sum-of-products circuits

(allow multiple outputs).

2 stages

o AND gates = product terms

o OR gates = outputs

Connections between inputs and the planes can be „burned‟.


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PLA EXAMPLE:

Simplified representation of previous PLA.


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READ ONLY MEMORY (ROM):

Similar to PLA

o Set of inputs (called addresses)

o Set of outputs

o Programmable mapping between inputs and outputs

Fully decoded: able to implement any mapping.

In contrast, PLAs may not be able to implement a given mapping due to not

having enough minterms.


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Answers:

1. b

2. d

3. a

4. c

5. d

6. c

7. b

8. c

9. a

10. c


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Chapter 7

Digital Devices

CONTENTS:

– Gates

– Flip-Flops

– PLDs

– FPGAs

Gates:

The most basic digital devices are called gates.

Gates got their name from their function of allowing or blocking (gating) the

flow of digital information.

A gate has one or more inputs and produces an output depending on the

input(s).

A gate is called a combinational circuit.

Three most important gates are: AND, OR, NOT

Logic Gates:

All digital circuits are based upon the interconnection of the various logic gates

described.

Complex logic circuits are based upon the OR, AND, and NOT functions along

with their derivatives.


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Logic Symbols:

• The standard and IEC logic symbols for the various logic gates are shown

below.

Gate Conversions:

• Two or more logic gates can be combined to provide the same function as a

different type of logic gate.


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• This is often done to reduce the total number of IC packages used in a product.

What is the Basic Digital Element in Electronics ?

Ans.: a Switch

Using Switch to represent digital information:

Digital Abstraction:

It is difficult to make ideal switches means a switch is completely ON or

completely OFF.


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So, we impose some rules that allow analog behavior to be ignored in most

cases, so circuits can be modeled as if they really did process 0s and 1s, known

as digital abstraction.

Digital abstraction allows us to associate a noise margin with each logic values

(0 and 1).

Real Switches to represent digital information:

Logic levels:

• Undefined region is inherent digital, not analog

• Switching threshold varies with voltage, temperature need “noise margin”

• Logic voltage levels decreasing with new processors.

5 , 3.3 , 2.5 , 1.8 V

Switch model:


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Flip-flops:

A device that stores either a 0 or 1.

Stored value can be changed only at certain times determined by a clock input.

New value depend on the current state and it‟s control inputs

A digital circuit that contains filp-flops is called a sequential circuit

Flip-flops are important devices used in many digital applications and serve as

building blocks for more complex integrated circuits.

Two of the most common types of flip-flops are:

• D flip-flop

• JK flip-flop

Flip-flops can operate in two different modes:

• Asynchronous

• Synchronous

Counters:


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• In essence, a flip-flop that is configured to toggle on every clock pulse is a 1-bit

counter. If multiple flip-flops are connected together, a counter of any length

can be built.

• There two general classes of counters:

– Asynchronous - clock pulses arrive at the flip-flops at different times.

– Synchronous - clock pulses arrive at the flip-flops at the same time.

Integrated Circuits:

• A collection of one or more gates fabricated on a single silicon chip is called an

integrated circuit (IC).

• ICs were classified by size:

– SSI - small scale integration - 1~20 gates

– MSI - medium scale integration - 20~200 gates

– LSI - large scale integration - 200~200,000 gates

– VLSI - very large scale integration - over 1M transistors

• Pentium-III - 40 million transistors

DIP Packages:

Gates in ICs:


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Gate Array Logic:

Many IC manufacturers produce complex logic systems that can be

programmed to perform a variety of logical functions within a single IC.

These ICs are known by various names:

– Gate Array Logic (GAL)

– Programmable Array Logic (PAL)

– Programmable Logic Device (PLD)

– Complex Programmable Logic Device (CPLD)

Programmable Logic Devices:

• PLDs allow the function to be programmed into them after they are

manufactured.

• Complex PLDs (CPLD) are a collection of PLDs on the same chip.

• Another programmable logic chip is FPGA - field-programmable gate arrays.

CPLDs and FPGAs:


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Digital Design Levels:

– The lowest level of design is device physics and IC manufacturing processes.

– Design at the transistor level

– Level of functional building blocks

– Level of logic design using HDLs

– Computer design and overall system design.

Interfacing Digital and Analog Systems:

– Computers are used in nearly every aspect of our daily lives, including business,

industrial, recreational, and personal applications.

– In many industrial applications, the devices being controlled or monitored are

analog.

– It is important to understand the operation of analog-to-digital and digital-to-

analog conversion processes.

Digital-to-Analog Conversion:

One type of digital-to-analog converter is shown below.

Note that the least significant bit has the highest value input resistor.

For each binary input increment, the output voltage will increase

correspondingly.


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Analog-to-Digital Conversion:

• An analog-to-digital (ADC) is the functional opposite of a digital-to-analog

(DAC) converter.

• An analog voltage or current is applied to the ADC input and is transformed into

an equivalent digital value.

• A flash ADC is shown.


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Troubleshooting Digital Systems:

• As digital systems have only two possible states, conceptually they should be

less complex to troubleshoot; however, the complexity of digital systems can

make troubleshooting them difficult.

• Regardless of their complexity, each device conforms to some basic rules.

Combinational logic:

o Determine relevant inputs

o Probable defects:

– Output always low

– Output always high

– Output at a “bad” level

– Input shorted to ground or supply voltage

– Input open

o Logic probes and logic pulsers are useful tools for identifying specific

defects in a logic circuit.

Sequential Logic:

– Sequential logic circuits pose a serious troubleshooting challenge to even

an experienced technician.

– In most cases, the logic states in the system are continuously changing.

– Often, the logic status of many points at any one time are necessary to

understand and troubleshoot the circuit.

– A logic analyzer is an effective troubleshooting instrument for sequential

logic circuits.

Suplementary Reading:

• Digital Design

by - John F. Wakerly

– www.ddpp.com - you will find some solutions at this site.

– www.xilinx.com - Xlinix Web site

• Logic and Computer Design Fundamentals

by - M. Morris Mano & Charles R. Kime

• Digital Design

by - M. Morris Mano

• Digital Logic Circuit Analysis and Design

by - Victor P. Nelson, H. Troy Nagle, J. David Irwin & Bill D. Carrol


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Appendix Laws and Theorems of Boolean Algebra

entity laws (operations with 0 and 1):

1. X + 0 = X 10. X • 1 = X

Annulment laws (operations with 0 and 1):

2. X + 1 = 1 20. X • 0 = 0

Idempotent laws:

3. X + X = X 30. X • X = X

Involution law:

4. ( X· ) · = X

Laws of complementarity:

5. X + X· = 1 50. X • X' = 0

Commutative laws:

6. X + v = v + X 60. X • Y = Y • X

Associative laws:

7. (X + v) + Z = X + (v + Z) = X + v + Z 70. (Xv)Z = X(vZ) = XvZ

0istributive laws:

8. X( v + Z ) = Xv + XZ 80. X + vZ = ( X + v ) ( X + Z )

Simplification theorems:

9. X v + X v· = X 90. ( X + v ) ( X + v· ) = X

10. X + Xv = X 100. X ( X + v ) = X

11. ( X + v· ) v = Xv 110. Xv· + v = X + v

DeMorgan s laws:

12. ( X + Y + z + )' = X'Y'z' 120. (X Y z )' = X' + Y' + z' +

13. [ f ( X1, X2, XN, 0, 1, +, • ) ]' = f ( X1', X2', XN', 1, 0, •, + )

0uality:

14. ( X + Y + z + )0

= X Y z 140. (X Y z )0

= X + Y + z +

15. [ f ( X1, X2, XN, 0, 1, +, • ) ] 0

= f ( X1, X2, XN, 1, 0, •, + )

Theorem for multiplying out and factoring:

16. ( X + v ) ( X· + Z ) = X Z + X· v 160. Xv + X· Z = ( X + Z ) ( X· + v )

Consensus theorem:

17. Xv + vZ + X·Z = Xv + X·Z 170. (X + v)(v + Z)(X· + Z) = (X + v)(X· + Z)


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IPage

Truth Tables for the Laws of Boolean

Boolean

Expression Description

Equivalent

Switching Circuit

Boolean Algebra

Law or Rule

A + 1 = 1 A in parallel with

closed = "CLOSED"

Annulment

A + 0 = A A in parallel with

open = "A"

A . 1 = A A in series with

closed = "A"

Identity

Identity

A . 0 = 0 A in series with

open = "OPEN"

A + A = A A in parallel with

A = "A"

Annulment

Idempotent

A . A = A A in series with

A = "A"

NOT A̅ = A NOT NOT A (double negative) = "A"

Idempotent

Double Negation

A + A̅ = 1 A in parallel with

NOT A = "CLOSED"

Complement

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A . A̅ = O A in series with

NOT A = "OPEN"

Complement

A+B = B+A A in parallel with B =

B in parallel with A

A.B = B.A A in series with B =

B in series with A

Commutative

Commutative

A̅̅̅+̅̅B̅ = A̅ . B̅ invert and replace OR with

AND

de Morgan s

Theorem

A̅̅̅.̅B̅ = A̅ +B̅ invert and replace AND with

OR

de Morgan s

Theorem

The basic Laws of Boolean Algebra that relate to:

• The Commutative Law allowing

a change

in position for

addition

an

d multiplication.

• The Associative Law allowing the

removal

of brackets for

addition

an

d multiplication. • The Distributive Law allowing the factoring of an expression are the same as in

ordinary algebra.

• Each of the Boolean Laws above are given with just a single or

two variables, but the number of variables defined by a single

law is not limited to this as there can be an infinite number of

variables as inputs too the expression.

• These Boolean laws detailed above can be used to prove

any given Boolean expression as well as for simplifying

complicated digital circuits.

A brief description of the various Laws of Boolean are given below

with A representing a variable input.

IPage

Description of the Laws of Boolean Algebra • Annulment Law – A term AND'ed with a Ȋ0 equals 0 or OR'ed with a Ȋ1 will equal

1.

o A . 0 = 0 A variable AND ed with 0 is always equal to 0.

o A + 1 = 1 A variable OR ed with 1 is always equal to 1.

• Identity Law – A term OR'ed with a Ȋ0 or AND'ed with a Ȋ1 will always equal that

term.

o A + 0 = A A variable OR ed with 0 is always equal to the variable.

o A . 1 = A A variable AND ed with 1 is always equal to the variable.

• Idempotent Law – An input that is AND'ed or OR'ed with itself is equal to that

input.

o A + A = A A variable OR ed with itself is always equal to the variable.

o A . A = A A variable AND ed with itself is always equal to the variable.

• Complement Law – A term AND'ed with its complement equals Ȋ0 and a

term OR'ed with its complement equals Ȋ1 .

o A . A̅ = 0 A variable AND ed with its complement is always equal to 0.

o A + A̅ = 1 A variable OR ed with its complement is always equal to 1.

• Commutative Law – The order of application of two separate terms is not

important.

o A . B = B . A The order in which two variables are AND ed makes no

difference.

o A + B = B + A The order in which two variables are OR ed makes no

difference.

• Double Negation Law – A term that is inverted twice is equal to the original term.

o A̿ = A A double complement of a variable is always equal to the variable.

• de Morgan's Theorem – There are two Ȋde Morgan's rules or theorems,

• (1) Two separate terms NOR'ed together is the same as the two terms inverted

(Complement) and AND'ed for example, A+B = A. B.

• (2) Two separate terms NAND'ed together is the same as the two terms inverted

(Complement) and OR'ed for example, A.B = A +B.

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Other algebraic Laws of Boolean not detailed above include:

• Distributive Law – This law permits the multiplying or factoring out of an

expression.

o A(B + C) = A.B + A.C (OR Distributive Law)

o A + (B.C) = (A + B).(A + C) (AND Distributive Law)

• Absorptive Law – This law enables a reduction in a complicated expression to a

simpler one by absorbing like terms.

o A + (A.B) = A (OR Absorption Law)

o A(A + B) = A (AND Absorption Law)

• Associative Law – This law allows the removal of brackets from an expression and

regrouping of the variables.

o A + (B + C) = (A + B) + C = A + B + C (OR Associate Law)

o A(B.C) = (A.B)C = A . B . C (AND Associate Law)

Boolean Algebra Functions

Using the information above, simple 2-input AND, OR and NOT Gates can be

represented by 16 possible functions as shown in the following table.

Function Description Expression

1. NULL 0

2. IDENTITY 1

3. Input A A

4. Input B B

5. NOT A A̅

6. NOT B B̅

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7. A AND B (AND) A . B

8. A AND NOT B A . B̅

9. NOT A AND B A̅ . B

10. NOT AND (NAND) A̅̅̅.̅B̅

11. A OR B (OR) A + B

12. A OR NOT B A + B̅

13. NOT A OR B A̅ + B

14. NOT OR (NOR) A̅̅̅+̅̅B̅

15. Exclusive-OR

A . B + A . B

16. Exclusive-NOR ̅A̅.̅B̅̅+̅̅A̅̅.̅B̅

Laws of Boolean Algebra Example No1

Using the above laws, simplify the following expression:

(A + B) . (A + C)

Q = (A + B).(A + C)

A.A + A.C + A.B + B.C – Distributive law

A + A.C + A.B + B.C – Idempotent AND law (A.A = A)

A(1 + C) + A.B + B.C – Distributive law

A.1 + A.B + B.C – Identity OR law (1 + C = 1)

A(1 + B) + B.C – Distributive law

A.1 + B.C – Identity OR law (1 + B = 1)

Q = A + (B.C) – Identity AND law (A.1 = A)

Then the expression: (A + B) (A + C) can be simplified to A + (B.C) as in the

Distributive law.

Assignments

Assignment (1.1):

1. Complete the following:

(a) Analog systems process time-varying signals that can take on

................voltages.

(b) Digital systems process time-varying signals that can take on .............of

voltages.

(c) “Analog electronics” deals with ………… values

(d) “Digital electronics” deals with ..............values

(e) Groups of bits (combinations of 0s and 1s) are called ………..

(f) The voltages used to represent a 1 and 0 are called …………..

(g) For CMOS, the range of voltage of high is between…….to…….

(h) For CMOS, the range of voltage of low is between…….to…….

(i) Serial data transfer means……….

(j) Parallel data transfer means……….

2. Write down the scientific meaning for the following sentences:

(a) Systems process time-varying signals that can take on any value across a continuous

range of voltages.

(b) Systems process time-varying signals that can take on only one of two discrete

values of voltages.

(c) Are groups of bits (combinations of 0s and 1s).

(d) Are the voltages used to represent a 1 and 0.

3. What are the benefits of digital over analog?

4. What the advantages of digital?

5. Define the rise time and the fall time?

6. Write an expression for the frequency and the duty cycle for the periodic

waveform?

7. From a portion of a periodic waveform (as shown) determine:

Period

Frequency

Duty cycle

8. In data transfer what are the advantages and disadvantages of serial over parallel?

Assignment (2.1):

1. Calculate the value of the following Binary Arithmetics:

(a) 111101 + 10111

(b) 1001101 – 0111

(c) 10111 1010

2. Convert 110102 to decimal

3. Convert 2610 to binary

4. Convert Decimal (Integer) to Binary: (13)10

5. Convert Decimal (Fraction) to Binary: (0.625)10

6. Convert Decimal to Octal: (175)10 , (0.3125)10

7. Convert Binary to Octal: (101110.01)

8. Convert Binary to Hexadecimal: (10110.01)

9. Convert Octal to Hexadecimal: (26.2) 8

10. Using 10's complement, subtract 72532 – 3250.

11. Given the two binary numbers X = 1010100 and Y = 1000011, perform

the subtraction (a) X – Y ; and (b) Y X, by using 2's complement.

12. Given the two binary numbers X = 1010100 and Y = 1000011, perform

the subtraction (a) X – Y ; and (b) Y X, by using 1's complement.

13. Calculate the arithmetic subtraction of the 2‟s-complement:

( 6) ( 13)

14. Calculate the arithmetic addition of the 2 numbers: (+6) + (+13)

15. Consider the decimal 185 calculate its corresponding value in BCD and

binary.

16. Consider the addition of 184 + 576 = 760 , calculate its value in BCD.

17. Choose the correct answer:

18. Converting (153)10 to base 8 yields which of the

following results?

(a) 107

(b) 132

(c) 701

(d) 231

(e) 153


following results?

(a) 107

(b) 132

(c) 701

(d) 231

(e) 153


following results?

(a) 531

(b) 721

(c) 44

(d) 135

(e) 127

21. The two's complement of the number (01010)2 is:

(a) 10101

(b) 10011

(c) 00101

(d) 01100

http://homepages.wmich.edu/~johnson/ece250/Quiz1/q1f1.html



















(e) 10110

22. Converting (11011.01)2 to base 8 yields which of the

following results?

(a) 33.2

(b) 63.2

(c) 63.1

(d) 33.1

(e) 63.01

23. Converting (.375)10 to base 2 yields which of the

following results?

(a) .1011

(b) .110

(c) .1101

(d) .011

(e) .110111111


following results?

(a) 169

(b) 9A

(c) B3

(d) A9

(e) 361

25. 10111 is the two's complement representation of:

(a) -23

(b) -9



















(c) -7

(d) +22

(e) +7

26. Converting (0111011.100)2 to base 16 yields which of

the following results?

(a) 73.8

(b) 3C.4

(c) 3B.8

(d) 73.4

(e) 3B.4


(a) -23

(b) -9

(c) -7

(d) +22

(e) +7


following results?

(a) 205

(b) 135

(c) 273

(d) 372

(e) 531


a. -11

b. +12

c. -12

d. -20























e. +20

30. A Hamming code 1010101 was received. What is the

received data?

(a) 1000

(b) 1101

(c) 1010

(d) 0101

(e) 0110

31. A Hamming code 0010111 was received. The HC

should have been 1111111 (based upon the data field

received). What bit position is the error?

(a) 1

(b) 6

(c) 3

(d) 7

(e) 5

NOTE: The solution of problems 1 to 16 is in chapter (2).

Assignment (3.1):

1. Using Boolean algebra technique, simplify the expression:

X.Y + X(Y + Z) + Y(Y + Z)

2.

3.












4. Draw the truth table for: A + BC

5. Draw the truth table for: A(B + D)

6. Draw the truth table for: (A + B) (A + C)

7. Draw the truth table for:

8. Draw the truth table for:

9. Simplify:

10. Simplify:

11. Simplify:

12. Simplify

Assignment (3.2):

Boolean Algebra Practice Problems (do not turn in):

Simplify each expression by algebraic manipulation. Try to recognize

when it is appropriate to transform to the dual, simplify, and re-transform

(e.g. no. 6). Try doing the problems before looking at the solutions which

are at the end of this problem set.

1) a + 0 = 14)

2) a · 0 = 15)

y + y y =

xy + x y =

3) a + a =

16)

x + y x =

4) a + a = 17) (w + x + y + z) y =

5) a + ab = 18) ( x + y)( x + y) =

6) a + ab = 19) w + [w + (wx)] =

7) a(a + b) = 20)

x[ x + ( xy)] =

8) ab + ab =

9) (a + b)(a + b) =

21) ( x + x) =

22) ( x + x) =

10) a(a + b + c + ...) = 23) w + (wx yz) =

For (11),(12), (13),

f (a, b, c) = a + b + c

24) w · (wxyz ) =

11)

f (a, b, ab) = 25)

xz + x y + zy =

12)

f (a, b, a · b) = 26) ( x + z)( x + y)( z + y) =

13)

f [a, b, (ab)] = 27)

x + y + xy z =

Assignment (3.3):

Simplify following Boolean Functions: 1. F = xy + x‟y + xy‟

2. F = x + x‟y

3. F = (x + y)(x +y‟)

4. F = xy + x‟z + yz

5. F = xyz + x‟y + xyz‟

Assignment (3.4):

Simplify the following by using Boolean algebra:

Assignment (3.5):

Boolean Algebra and Logic Simplification - Filling the Blanks

1. The Boolean expression C + CD is equal to ________.

A. C

B. D

C. C + D

D. 1

2. The Boolean expression for the logic circuit shown is _____.

A.

B.

C.

D.

3. Applying DeMorgan's theorem and Boolean algebra to the expression results in

________.

A.

B.

C.

D.

4. The standard SOP form of the expression is ________.

A.

B.

C.

D.

5. Identify the Boolean expression that is in standard POS form.

A.

B.

C.

D. (A + B)(C + D)

6. The Boolean expression is equal to ________.

A. C

B. D

C. C + D

D. 1

7. The Boolean expression can be reduced to ________.

A.

B.

C.

D.

8. Which of the following is true for a 5-variable Karnaugh map?

A. There is no such thing.

B. It can be used only with the aid of a computer.

C. It is made up of two 4-variable Karnaugh maps.

D. It is made up of a 2-variable and a 3-variable Karnaugh map.

9. When four 1s are taken as a group on a Karnaugh map, the number of variables eliminated

from the output expression is ________.

A. 1

B. 2

C. 3

D. 4

10. In Boolean algebra, the word "literal" means ________.

A. a product term

B. all the variables in a Boolean expression

C. the inverse function

D. a variable or its complement

Assignment (3.6):

Boolean Algebra and Logic Simplification - General Questions

1. Convert the following SOP expression to an equivalent POS expression.

A.

B.

C.

D.

2. Determine the values of A, B, C, and D that make the sum term equal to zero.

A. A = 1, B = 0, C = 0, D = 0

B. A = 1, B = 0, C = 1, D = 0

C. A = 0, B = 1, C = 0, D = 0

D. A = 1, B = 0, C = 1, D = 1

3. Which of the following expressions is in the sum-of-products (SOP) form?

A. (A + B)(C + D)

B. (A)B(CD)

C. AB(CD)

D. AB + CD

4. Derive the Boolean expression for the logic circuit shown below:

A.

B.

C.

D.

5. From the truth table below, determine the standard SOP expression.

A.

B.

C.

D.

6. One of De Morgan's theorems states that . Simply stated, this means that

logically there is no difference between:

A. a NOR and an AND gate with inverted inputs

B. a NAND and an OR gate with inverted inputs

C. an AND and a NOR gate with inverted inputs

D. a NOR and a NAND gate with inverted inputs

7. The commutative law of Boolean addition states that A + B = A × B.

A. True

B. False

8. Applying DeMorgan's theorem to the expression , we get ________.

A.

B.

C.

D.

9. The systematic reduction of logic circuits is accomplished by:

A. using Boolean algebra

B. symbolic reduction

C. TTL logic

D.

using a truth table

10. Which output expression might indicate a product-of-sums circuit construction?

A.

B.

C.

D.

11. An AND gate with schematic "bubbles" on its inputs performs the same function as

a(n)________ gate.

A. NOT

B. OR

C. NOR

D. NAND

12. For the SOP expression , how many 1s are in the truth table's output

column?

A. 1

B. 2

C. 3

D. 5

13. A truth table for the SOP expression has how many input combinations?

A. 1

B. 2

C. 4

D. 8

14. How many gates would be required to implement the following Boolean expression before

simplification? XY + X(X + Z) + Y(X + Z)

A. 1

B. 2

C. 4

D. 5

15. Determine the values of A, B, C, and D that make the product term equal to 1.

A. A = 0, B = 1, C = 0, D = 1

B. A = 0, B = 0, C = 0, D = 1

C. A = 1, B = 1, C = 1, D = 1

D. A = 0, B = 0, C = 1, D = 0

16. How many gates would be required to implement the following Boolean expression after

simplification? XY + X(X + Z) + Y(X + Z)

A. 1

B. 2

C. 4

D. 5

17. AC + ABC = AC

A. True

B. False

18. When are the inputs to a NAND gate, according to De Morgan's theorem, the output

expression could be:

A. X = A + B

B.

C. X = (A)(B)

D.

19. Which Boolean algebra property allows us to group operands in an expression in any order

without affecting the results of the operation [for example, A + B = B + A]?

A. associative

B. commutative

C. Boolean

D. distributive

20. Applying DeMorgan's theorem to the expression , we get ________

A.

B.

C.

D.

21. When grouping cells within a K-map, the cells must be combined in groups of ________.

A. 2s

B. 1, 2, 4, 8, etc.

C. 4s

D. 3s

22. Use Boolean algebra to find the most simplified SOP expression for F = ABD + CD + ACD +

ABC + ABCD.

A. F = ABD + ABC + CD

B. F = CD + AD

C. F = BC + AB

D. F = AC + AD

23. Occasionally, a particular logic expression will be of no consequence in the operation of a

circuit, such as a BCD-to-decimal converter. These result in ________terms in the K-map and

can be treated as either ________ or ________, in order to ________ the resulting term.

A. don't care, 1s, 0s, simplify

B. spurious, ANDs, ORs, eliminate

C. duplicate, 1s, 0s, verify

D. spurious, 1s, 0s, simplify

24. The NAND or NOR gates are referred to as "universal" gates because either:

A. can be found in almost all digital circuits

B. can be used to build all the other types of gates

C. are used in all countries of the world

D. were the first gates to be integrated

25. The truth table for the SOP expression has how many input combinations?

A. 1

B. 2

C. 4

D. 8

26. Converting the Boolean expression LM + M(NO + PQ) to SOP form, we get ________.

A. LM + MNOPQ

B. L + MNO + MPQ

C. LM + M + NO + MPQ

D. LM + MNO + MPQ

27. A Karnaugh map is a systematic way of reducing which type of expression?

A. product-of-sums

B. exclusive NOR

C. sum-of-products

D. those with overbars

28. The Boolean expression is logically equivalent to what single gate?

A. NAND

B. NOR

C. AND

D. OR

29. Applying the distributive law to the expression , we get ________.

A.

B.

C.

D.

30. Mapping the SOP expression , we get ________.

A. (A)

B. (B)

C. (C)

D. (D)

31. Derive the Boolean expression for the logic circuit shown below:

A.

B.

C.

D.

32. Which is the correct logic function for this PAL diagram?

A.

B.

C.

D.

33. For the SOP expression , how many 0s are in the truth table's output column?

A. zero

B. 1

C. 4

D. 5

34. Mapping the standard SOP expression , we get

A. (A)

B. (B)

C. (C)

D. (D)

35. Which statement below best describes a Karnaugh map?

A. A Karnaugh map can be used to replace Boolean rules.

B. The Karnaugh map eliminates the need for using NAND and NOR gates.

C. Variable complements can be eliminated by using Karnaugh maps.

D. Karnaugh maps provide a cookbook approach to simplifying Boolean expressions.


A.

B.

C.

D.

37. Which of the examples below expresses the distributive law of Boolean algebra?

A. (A + B) + C = A + (B + C)

B. A(B + C) = AB + AC

C. A + (B + C) = AB + AC

D. A(BC) = (AB) + C


A.

B.

C.

D.

39. Which of the following is an important feature of the sum-of-products (SOP) form of

expression?

A. All logic circuits are reduced to nothing more than simple AND and OR gates.

B. The delay times are greatly reduced over other forms.

C. No signal must pass through more than two gates, not including inverters.

D.

The maximum number of gates that any signal must pass through is reduced by a factor of

two.

40. An OR gate with schematic "bubbles" on its inputs performs the same functions as

a(n)________ gate.

A. NOR

B. OR

C. NOT

D. NAND

41. Which of the examples below expresses the commutative law of multiplication?

A. A + B = B + A

B. AB = B + A

C. AB = BA

D. AB = A × B

42. Determine the binary values of the variables for which the following standard POS expression

is equal to 0.

A. (0 + 1 + 0)(1 + 0 + 1)

B. (1 + 1 + 1)(0 + 0 + 0)

C. (0 + 0 + 0)(1 + 0 + 1)

D. (1 + 1 + 0)(1 + 0 + 0)

43. The expression W(X + YZ) can be converted to SOP form by applying which law?

A. associative law

B. commutative law

C. distributive law

D. none of the above

44. The commutative law of addition and multiplication indicates that:

A. we can group variables in an AND or in an OR any way we want

B.

an expression can be expanded by multiplying term by term just the same as in ordinary

algebra

C. the way we OR or AND two variables is unimportant because the result is the same

D.

the factoring of Boolean expressions requires the multiplication of product terms that

contain like variables

45. Which of the following combinations cannot be combined into K-map groups?

A. corners in the same row

B. corners in the same column

C. diagonal

D. overlapping combinations

Assignment (4.1): Logic Gates - Filling the Blanks

1. The gates in this figure are implemented using TTL logic. If the input of the inverter is open,

and you apply logic pulses to point B, the output of the AND gate will be ________.

A. a steady LOW

B. a steady HIGH

C. an undefined level

D. pulses

2. The gates in this figure are implemented using TTL logic. If the output of the inverter is open,

and you apply logic pulses to point B, the output of the AND gate will be ________.

A. a steady LOW

B. a steady HIGH

C. an undefined level

D. pulses

3. If A is LOW or B is LOW or BOTH are LOW, then X is LOW. If A is HIGH and B is HIGH,

then X is HIGH. These rules specify the operation of a(n) ________.

A. AND gate

B. OR gate

C. NAND gate

D. XOR gate

4. A major advantage of ECL logic over TTL and CMOS is ________.

A. low power dissipation

B. high speed

C. both low power dissipation and high speed

D. neither low power dissipation nor high speed

5. The output of an XOR gate is HIGH only when ________.

A. both inputs = 0

B. both inputs = 1

C. the two inputs are unequal

D. both inputs are undefined

6. A 2-input gate that can be used to pass a digital waveform unchanged at certain times and

inverted at other times is a(n) ________.

A. AND gate

B. OR gate

C. NAND gate

D. XOR gate

7. The gates in this figure are implemented using TTL logic. If the output of the inverter has an

internal open circuit, what voltage would you expect to measure at the inverter's output?

A. Less than 0.4 V

B. 1.6 V

C. Greater than 2.4 V

D. All of the above

8. When does the output of a NAND gate = 1?

A. Whenever a 0 is present at an input

B. Only when all inputs = 0

C. Whenever a 1 is present at an input

D. Only when all inputs = 1

9. The number of input combinations for a 4-input gate is ________.

A. 9

B. 8

C. 15

D. 16

10. When does the output of a NOR gate = 0?

A. Whenever a 0 is present at an input

B. Only when all inputs = 0

C. Whenever a 1 is present at an input

D. Only when all inputs = 1

Assignment (4.2):

Logic Gates - True or False

1. A truth table illustrates how the input level of a gate responds to all the possible

output level combinations.

A. True

B. False

2. A NOR gate output is LOW if any of its inputs is LOW.

A. True

B. False

3. As a rule, CMOS has the lowest power consumption of all IC families.

A. True

B. False

4. A popular waveform generator is the Johnson shift counter.

A. True

B. False

5. Good troubleshooting is done by looking at the input signal and how it interacts

with the circuits.

A. True

B. False

6. A NOR gate and an OR gate operate in exactly the same way.

A. True

B. False

7. An OR array is programmed by blowing fuses to eliminate selected variables

from the output functions.

A. True

B. False

8. A NAND gate output is LOW only if all the inputs are HIGH.

A. True

B. False

9. An AND gate output is LOW if all the inputs are HIGH.

A. True

B. False

10

.

Power is connected to pins 7 and 14 of a 7408 quad two-input AND gate IC to

allow voltage for all four AND gates on the IC.

A. True

B. False

11

.

An exclusive-NOR gate output is HIGH when the inputs are unequal.

A. True

B. False

12

.

An OR gate output is HIGH only if all the inputs are HIGH.

A. True

B. False

13

.

A waveform can be enabled or disabled by both AND and OR gates.

A. True

B. False

14

.

An exclusive-OR gate output is HIGH when the inputs are unequal.

A. True

B. False

15

.

In a Boolean equation the use of the + symbol represents the OR function.

A. True

B. False

16

.

A logic gate has one or more output terminals and one input terminal.

A. True

B. False

17

.

A logic pulser is used to determine the level of floating in a circuit.

A. True

B. False

18

.

An inverter output is the complement of its input.

A. True

B. False

19

.

It is important to memorize logic symbols, Boolean equations, and truth tables

for logic gates.

A. True

B. False

Assignment (4.3):

Logic Gates General Questions . 1. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.

A. A = 1, B = 1, C = 0

B. A = 0, B = 0, C = 0

C. A = 1, B = 1, C = 1

D. A = 1, B = 0, C = 1

2. If a 3-input NOR gate has eight input possibilities, how many of those possibilities will

result in a HIGH output?

A. 1

B. 2

C. 7

D. 8

3. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs,

and the output is HIGH, the gate is a(n):

A. AND

B. NAND

C. NOR

D. OR

4. A device used to display one or more digital signals so that they can be compared to

expected timing diagrams for the signals is a:

A. DMM

B. spectrum analyzer

C. logic analyzer

D. frequency counter

5. When used with an IC, what does the term "QUAD" indicate?

A. 2 circuits

B. 4 circuits

C. 6 circuits

D. 8 circuits

6. The output of an OR gate with three inputs, A, B, and C, is LOW when ________.

A. A = 0, B = 0, C = 0

B. A = 0, B = 0, C = 1

C. A = 0, B = 1, C = 1

D. all of the above

7. Which of the following logical operations is represented by the + sign in Boolean algebra?

A. Inversion

B. AND

C. OR

D. Complementation

8. Output will be a LOW for any case when one or more inputs are zero for a(n):

A. OR gate

B. NOT gate

C. AND gate

9. How many pins does the 4049 IC have?

A. 14

B. 16

C. 18

D. 20

10. Which of the following choices meets the minimum requirement needed to create

specialized waveforms that are used in digital control and sequencing circuits?

A. basic gates, a clock oscillator, and a repetitive waveform generator

B. basic gates, a clock oscillator, and a Johnson shift counter

C. basic gates, a clock oscillator, and a DeMorgan pulse generator

D.

basic gates, a clock oscillator, a repetitive waveform generator, and a Johnson shift

counter

Answer: Option A

11. TTL operates from a ________.

A. 9-volt supply

B. 3-volt supply

C. 12-volt supply

D. 5-volt supply

12. The output of a NOR gate is HIGH if ________.

A. all inputs are HIGH

B. any input is HIGH

C. any input is LOW

D. all inputs are LOW

13. The switching speed of CMOS is now ________.

A. competitive with TTL

B. three times that of TTL

C. slower than TTL

D. twice that of TTL

14. The format used to present the logic output for the various combinations of logic inputs to

a gate is called a(n):

A. Boolean constant

B. Boolean variable

C. truth table

D. input logic function

15. The power dissipation, PD, of a logic gate is the product of the ________.

A. dc supply voltage and the peak current

B. dc supply voltage and the average supply current

C. ac supply voltage and the peak current

D. ac supply voltage and the average supply current

16. A logic probe is again applied to the pins of a 7421 IC with the following results. Is

there a problem with the circuit and if so, what is the problem?

A. Pin 6 should be ON.

B. Pin 8 should be ON.

C. Pin 8 should be pulsing.

D. no problem

17. If a 3-input AND gate has eight input possibilities, how many of those possibilities will


A. 1

B. 2

C. 7

D. 8

18. The Boolean expression for a 3-input AND gate is ________.

A. X = AB

B. X = ABC

C. X = A + B + C

D. X = AB + C

19. A CMOS IC operating from a 3-volt supply will consume ________.

A. less power than a TTL IC

B. more power than a TTL IC

C. the same power as a TTL IC

D. no power at all

20. What does the small bubble on the output of the NAND gate logic symbol mean?

A. open collector output

B. Tristate

C. The output is inverted.


21. What are the pin numbers of the outputs of the gates in a 7432 IC?

A. 3, 6, 10, and 13

B. 1, 4, 10, and 13

C. 3, 6, 8, and 11

D. 1, 4, 8, and 11

22. The output of a NOT gate is HIGH when ________.

A. the input is LOW

B. the input is HIGH

C. power is applied to the gate's IC

D. power is removed from the gate's IC

23. If the input to a NOT gate is A and the output is X, then ________.

A. X = A

B.

C. X = 0


24. A logic probe is used to test the pins of a 7411 IC with the following results. Is there a

problem with the chip and if so, what is the problem?

A. Pin 6 should be ON.

B. Pin 6 should be pulsing.

C. Pin 8 should be ON.

D. no problem

25. How many inputs of a four-input AND gate must be HIGH in order for the output of

the logic gate to go HIGH?

A. any one of the inputs

B. any two of the inputs

C. any three of the inputs

D. all four inputs

26. If the output of a three-input AND gate must be a logic LOW, what must the condition

of the inputs be?

A. All inputs must be LOW.

B. All inputs must be HIGH.

C. At least one input must be LOW.

D. At least one input must be HIGH.

27. Logically, the output of a NOR gate would have the same Boolean expression as a(n):

A. NAND gate immediately followed by an inverter

B. OR gate immediately followed by an inverter

C. AND gate immediately followed by an inverter

D. NOR gate immediately followed by an inverter

28. A logic probe is placed on the output of a gate and the display indicator is dim. A

pulser is used on each of the input terminals, but the output indication does not change.

What is wrong?

A.

The dim indication on the logic probe indicates that the supply voltage is probably

low.

B. The output of the gate appears to be open.

C. The dim indication is the result of a bad ground connection on the logic probe.

D. The gate is a tristate device.

29. What is the Boolean expression for a three-input AND gate?

A. X = A + B + C

B. X = A BC

C. A – B – C

D. A $ B $ C

30. Which of the following gates has the exact inverse output of the OR gate for all

possible input combinations?

A. NOR

B. NOT

C. NAND

D. AND

31. What is the difference between a 7400 and a 7411 IC?

A. 7400 has two four-input NAND gates; 7411 has three three-input AND gates

B. 7400 has four two-input NAND gates; 7411 has three three-input AND gates

C. 7400 has two four-input AND gates; 7411 has three three-input NAND gates

D. 7400 has four two-input AND gates; 7411 has three three-input NAND gates

32. Write the Boolean expression for an inverter logic gate with input C and output Y.

A. Y = C

B. Y =

33. The output of an exclusive-OR gate is HIGH if ________.

A. all inputs are LOW

B. all inputs are HIGH

C. the inputs are unequal


34. A clock signal with a period of 1 s is applied to the input of an enable gate. The

output must contain six pulses. How long must the enable pulse be active?

A. Enable must be active for 0 s.

B. Enable must be active for 3 s.

C. Enable must be active for 6 s.

D. Enable must be active for 12 s.

35. The AND function can be used to ________ and the OR function can be used to

________ .

A. enable, disable

B. disable, enable

C. enable or disable, enable or disable

D. detect, invert

36. One advantage TTL has over CMOS is that TTL is ________.

A. less expensive

B. not sensitive to electrostatic discharge

C. Faster

D. more widely available

37. A 2-input NOR gate is equivalent to a ________.

A. negative-OR gate

B. negative-AND gate

C. negative-NAND gate


38. If a 3-input OR gate has eight input possibilities, how many of those possibilities will


A. 1

B. 2

C. 7

D. 8

39. Fan-out is specified in terms of ________.

A. Voltage

B. Current

C. Wattage

D. unit loads

40. How many input combinations would a truth table have for a six-input AND gate?

A. 32

B. 48

C. 64

D. 128

41. What is the circuit number of the IC that contains four two-input AND gates in

standard TTL?

A. 7402

B. 7404

C. 7408

D. 7432

42. The terms "low speed" and "high speed," applied to logic circuits, refer to the

________.

A. rise time

B. fall time

C. propagation delay time

D. clock speed

43. The NOR logic gate is the same as the operation of the ________ gate with an inverter

connected to the output.

A. OR

B. AND

C. NAND


44. The logic expression for a NOR gate is ________.

A.

B.

C.

D.

45. With regard to an AND gate, which statement is true?

A. An AND gate has two inputs and one output.

B. An AND gate has two or more inputs and two outputs.

C. If one input to a 2-input AND gate is HIGH, the output reflects the other input.

D. A 2-input AND gate has eight input possibilities.

46. The term "hex inverter" refers to:

A. an inverter that has six inputs

B. six inverters in a single package

C. a six-input symbolic logic device

D. an inverter that has a history of failure

47. How many inputs are on the logic gates of a 74HC21 IC?

A. 1

B. 2

C. 3

D. 4

48. The basic logic gate whose output is the complement of the input is the:

A. OR gate

B. AND gate

C. Inverter

D. Comparator

49. When reading a Boolean expression, what does the word "NOT" indicate?

A. the same as

B. inversion

C. High

D. Low

50. The output of an exclusive-NOR gate is HIGH if ________.

A. the inputs are equal

B. one input is HIGH, and the other input is LOW

C. the inputs are unequal


51. How many AND gates are found in a 7411 IC?

A. 1

B. 2

C. 3

D. 4

52. Which of the following equations would accurately describe a four-input OR gate when

A = 1, B = 1, C = 0, and D = 0?

A. 1 + 1 + 0 + 0 = 01

B. 1 + 1 + 0 + 0 = 1

C. 1 + 1 + 0 + 0 = 0

D. 1 + 1 + 0 + 0 = 00

53. What is the name of a digital circuit that produces several repetitive digital waveforms?

A. an inverter

B. an OR gate

C. a Johnson shift counter

D. an AND gate

54. The basic types of programmable arrays are made up of ________.

A. AND gates

B. OR gates

C. NAND and NOR gates

D. AND gates and OR gates

55. The logic gate that will have HIGH or "1" at its output when any one (or more) of its

inputs is HIGH is a(n):

A. OR gate

B. AND gate

C. NOR gate

D. NOT operation

56. CMOS IC packages are available in ________.

A. DIP configuration

B. SOIC configuration

C. DIP and SOIC configurations

D. neither DIP nor SOIC configurations

57. Which of the following is not a basic Boolean operation?

A. OR

B. NOT

C. AND

D. FOR

58. Which of the following gates is described by the expression ?

A. OR

B. AND

C. NOR

D. NAND

59. What is the Boolean expression for a four-input OR gate?

A. Y = A + B + C + D

B. Y = A B C D

C. Y = A – B – C – D

D. Y = A $ B $ C $ D

60. How many truth table entries are necessary for a four-input circuit?

A. 4

B. 8

C. 12

D. 16

61. How many entries would a truth table for a four-input NAND gate have?

A. 2

B. 8

C. 16

D. 32

62. The Boolean expression for a 3-input OR gate is ________.

A. X = A + B

B. X = A + B + C

C. X = ABC

D. X = A + BC

63. From the truth table for a three-input NOR gate, what is the only condition of inputs A,

B, and C that will make the output X high?

A. A = 1, B = 1, C = 1

B. A = 1, B = 0, C = 0

C. A = 0, B = 0, C = 1

D. A = 0, B = 0, C = 0

64. The logic gate that will have a LOW output when any one of its inputs is HIGH is the:

A. NAND gate

B. AND gate

C. NOR gate

D. OR gate

65. The output of a NAND gate is LOW if ________.

A. all inputs are LOW

B. all inputs are HIGH

C. any input is LOW

D. any input is HIGH

Assignment (5.1);

4. Define the meaning of the following integrated circuit part number:

MC 74ALS08P6?

5. What is the difference between commercial and military TTL logic

families?

6. Compare between 74L and 40S integrated circuits for:

b) Logic family - Propagation delay time - Power dissipation

4. Draw the symbols of schottky diode and schottky transistor?

5. What are the operating requirements for TTL logic family?

6. Why MOS/CMOS technology is popular?

7. What is the major advantage of MOS/CMOS technology?

8. What are the operating requirements for MOS/CMOS logic family?

9. What are the operating ranges (temperature and power supply) for

MOS/CMOS technology?

Assignment (6.1):

Logic gates Examples

1. Given a Boolean expression, implement it as a logic circuit (Draw the equivalent logic

circuit):

a) X1 = (A + B)C

b) X2 = A + BC + D‟

c) X3 = AB + (AC )‟

d) X4 = (A + B)‟ (C + D)C‟

e) F1 = x. Y. z'

f) F2 = x + y'. z [If complemented literals are available and are not available]

g) F3 = x. y' + x'. z [If complemented literals are available and are not available]

2. Given the logic circuit below, what is the Boolean expression of F4?

3. Draw the equivalent logic circuit F = A. B + C'. D + E using 2-level AND-OR circuit

4. Draw the equivalent logic circuit F = A. B + C'. D + E using 2-level NAND circuit

5. Draw the equivalent logic circuit G = (A+B) . (C'+D) . E using 2-level OR-AND

circuit

6. Draw the equivalent logic circuit G = (A+B) (C'+D) E using 2-level NOR circuit

7. Draw the truth table for the following circuits:

8. Draw the truth table and the equivalent logic circuit for the following equation:


Assignment (7.1):

9. Complete the following:

(k) A digital circuit that contains filp-flops is called .............

(l) The most common types of flip-flops are ..............

(m) The modes that flip-flops can operate are........... and ..............

(n) Asynchronous counter means ................

(o) Synchronous counter means ..............

(p) If multiple flip-flops are connected together, a ............. of any length

can be built.

(q) In asynchronous counter, clock pulses arrive at the flip-flops at

…………..

(r) In synchronous counter, clock pulses arrive at the flip-flops at

…………..

(s) The following abbreviations are stands for:

– SSI

– MSI

– LSI

– VLSI

– POS

– SOP

– GAL

– PAL

– PLD

– CPLD

– FBGA

10. Write down the scientific meaning for the following sentences:

(e) A digital circuit that contains filp-flops.

(f) Clock pulses arrive at the flip-flops at different times.

(g) Clock pulses arrive at the flip-flops at the same time.

(h) Small scale integration IC- 1~20 gates

(i) Medium scale integration IC- 20~200 gates

(j) Large scale integration IC- 200~200,000 gates

(k) Very large scale integration IC - over 1M transistors

(l) Logic device which allow the function to be programmed into them after

they are manufactured.

digital systems - e-learningforum.com 02, 2012 · dr. kamel a. m. soliman [email protected]...

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