full-custom design flow - welcome to vlsi information...

Introduction to VLSI and System-on-Chip Design

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science

National Chiao Tung University

Taiwan, R.O.C.

Fall, 2009

Full-Custom Design Flow

Lan-Da Van VLSI-03-2

Lecture 3


Outlines

Introduction

SPICE Simulation (Chapter 5 of the textbook)

� SPICE Commands

� SPICE Model

Design Rules (Chapter 3 of the textbook)

� Why We Need Design Rules?

� Scalable CMOS Design Rules

Layout (Chapter 1 of the textbook)

� Stick Diagram

� Layout Diagram

Conclusion


Lecture 3


Full Custom Design Step

Spec. Def.: clock freq., I/O timing, function mapping...

Process Selection: (0.35//0.18/0.13, logic, mixed-mode, Embed)CMOS, BiCMOS,GaAs

Circuit Architecture: Dynamic/Static logic, Parallel/Serial/Pipelined ...

Circuit Simulation: functional simulation, timing verification, spec. analysis...

Layout Design: HandCraft Placement&Route

Layout Verification: DRC/ERC, LVS, ...

Post Layout Simulation: LPE, Delay Calculation , Back annotation


Lecture 3


Specification

?

f

In Out

0 0 1 0 1 x

1 0 1 1 0 1

1/01/1

Function

Timing

2500um X 2500umArea

Power

T

Signal to Noise Ratio

200mW

50dB


Lecture 3


Full-Custom Simulation Flow

Circuit Design and Simulation

Layout Design and Verification

Post Layout Verification

TapeoutTapeout

Composer HSpice /Spectre

(Virtuso,Laker)/ (Calibre)

RC Extraction (Calibre)

GDSII


Lecture 3


Circuit Architecture Design

Parallel v.s Sequential

Number of clock phase

Number of pipeline stage

Dynamic logic / Static logic

Current-mode /Voltage-mode operation

Gain stage type and stage number

Differential signal v.s. Single ended

Compensation scheme


Lecture 3


Circuit Parameter Setting

In full-custom design, each parameter (including W/L,

capacitance, resistance) can be obtained by spec.

DC current (ID = F(VGS, W/L)) can be obtained by KCL,

KVL.

Delay time can be obtained by Tr ≈ (L/W)driver * (WL)load

In analog circuit, gain : -gm*ro , gm ∝ (W/L)1/2 , go = λID

According to the demanded current and voltage, we can

derive coarse estimated value of W/L.

According to environment, the capacitance can be

determined.


Lecture 3


Design Corner

Because of process variation, the parameters of the transistor will be varied.

Each NMOS and PMOS have well-defined range of the process variations, those are slow, typical, and fast.

5 design corners simulation: ss,sf,tt,fs,ff

NMOS

PMOS

typicalslowslow

typical

fast

fastModel

.lib “model_file” TT

.lib “model_file” SS

Or

.lib “model_file” mos_tt


Lecture 3


Layout Design and Verification

電路設計及模擬的驗證決定電路的組成及相關參數電路設計及模擬的驗證決定電路的組成及相關參數電路設計及模擬的驗證決定電路的組成及相關參數電路設計及模擬的驗證決定電路的組成及相關參數，，，，但仍但仍但仍但仍不是實體的成品不是實體的成品不是實體的成品不是實體的成品，，，，積體電路的實際成品需經晶圓廠製作積體電路的實際成品需經晶圓廠製作積體電路的實際成品需經晶圓廠製作積體電路的實際成品需經晶圓廠製作

設計者需提供積體電路製作的實體描述稱為佈局設計者需提供積體電路製作的實體描述稱為佈局設計者需提供積體電路製作的實體描述稱為佈局設計者需提供積體電路製作的實體描述稱為佈局

佈局設計將所設計的電路轉換為電路製作的圖形描述格式佈局設計將所設計的電路轉換為電路製作的圖形描述格式佈局設計將所設計的電路轉換為電路製作的圖形描述格式佈局設計將所設計的電路轉換為電路製作的圖形描述格式

LakerLakerLakerLaker工具提供佈局設計的環境工具提供佈局設計的環境工具提供佈局設計的環境工具提供佈局設計的環境

為讓晶片製作過程的合理變動不致影響製作的結果為讓晶片製作過程的合理變動不致影響製作的結果為讓晶片製作過程的合理變動不致影響製作的結果為讓晶片製作過程的合理變動不致影響製作的結果，，，，電路電路電路電路設計者所設計的電路佈局必需滿足晶圓廠所提供的佈局規設計者所設計的電路佈局必需滿足晶圓廠所提供的佈局規設計者所設計的電路佈局必需滿足晶圓廠所提供的佈局規設計者所設計的電路佈局必需滿足晶圓廠所提供的佈局規

範範範範。。。。(Design Rule Check)

電路設計及佈局設計為不同階段的獨立設計過程電路設計及佈局設計為不同階段的獨立設計過程電路設計及佈局設計為不同階段的獨立設計過程電路設計及佈局設計為不同階段的獨立設計過程，，，，必須確必須確必須確必須確

保佈局設計及原電路的一致性保佈局設計及原電路的一致性保佈局設計及原電路的一致性保佈局設計及原電路的一致性。。。。(Layout v.s. Schematic)

Calibre, Dracula等軟體等軟體等軟體等軟體提供佈局驗證的功能提供佈局驗證的功能提供佈局驗證的功能提供佈局驗證的功能


Lecture 3


Post Layout Simulation

實際的訊號線具有阻抗及負載實際的訊號線具有阻抗及負載實際的訊號線具有阻抗及負載實際的訊號線具有阻抗及負載，，，，對原電路將造成特性上的對原電路將造成特性上的對原電路將造成特性上的對原電路將造成特性上的改變改變改變改變，，，，完整設計應考量訊號線的負載延遲效應完整設計應考量訊號線的負載延遲效應完整設計應考量訊號線的負載延遲效應完整設計應考量訊號線的負載延遲效應。。。。

準確的連接線模型方可促成正確的模擬結果準確的連接線模型方可促成正確的模擬結果準確的連接線模型方可促成正確的模擬結果準確的連接線模型方可促成正確的模擬結果。。。。

完整的連接線負載包含龐大數量的雜散元件完整的連接線負載包含龐大數量的雜散元件完整的連接線負載包含龐大數量的雜散元件完整的連接線負載包含龐大數量的雜散元件，，，，完整的模擬完整的模擬完整的模擬完整的模擬將增加所需的時間將增加所需的時間將增加所需的時間將增加所需的時間，，，，device reduction 為必須的考量為必須的考量為必須的考量為必須的考量。。。。

佈局後模擬包含佈局後模擬包含佈局後模擬包含佈局後模擬包含電路及雜散元件萃取電路及雜散元件萃取電路及雜散元件萃取電路及雜散元件萃取 + 電路模擬等兩項電路模擬等兩項電路模擬等兩項電路模擬等兩項步驟步驟步驟步驟。。。。

Extraction Reduction


Lecture 3


由於積體電路中訊號線的距離相當接近由於積體電路中訊號線的距離相當接近由於積體電路中訊號線的距離相當接近由於積體電路中訊號線的距離相當接近，，，，一條訊號線上的一條訊號線上的一條訊號線上的一條訊號線上的

訊號轉態會干擾鄰近訊號線的位準訊號轉態會干擾鄰近訊號線的位準訊號轉態會干擾鄰近訊號線的位準訊號轉態會干擾鄰近訊號線的位準(Interconnect

coupling)。。。。

由於積體電路的所有元件均位於同一基底上由於積體電路的所有元件均位於同一基底上由於積體電路的所有元件均位於同一基底上由於積體電路的所有元件均位於同一基底上，，，，因此因此因此因此，，，，雜訊雜訊雜訊雜訊

可能會透過基底干擾其他電路的運作可能會透過基底干擾其他電路的運作可能會透過基底干擾其他電路的運作可能會透過基底干擾其他電路的運作(Substrate coupling)。。。。

由於電路的電源訊號係由金屬線連至晶片各處由於電路的電源訊號係由金屬線連至晶片各處由於電路的電源訊號係由金屬線連至晶片各處由於電路的電源訊號係由金屬線連至晶片各處，，，，金屬線上金屬線上金屬線上金屬線上的雜散電感值將使電流變化轉換為電壓降產生雜訊影響電的雜散電感值將使電流變化轉換為電壓降產生雜訊影響電的雜散電感值將使電流變化轉換為電壓降產生雜訊影響電的雜散電感值將使電流變化轉換為電壓降產生雜訊影響電

路的運作路的運作路的運作路的運作(IR drop induced power/ground bounce)

CircuitSignal input

Noise input

Noise Analysis


Lecture 3


Outlines

Introduction

SPICE Simulation

� SPICE Commands

� SPICE Model

Design Rules



Layout

� Stick Diagram

� Layout Diagram

Conclusion


Lecture 3


Circuit Simulation: SPICE (1975)

SPICE: Simulation Program for Integrated Circuits

Emphasis� SPICE was originally developed at the Electronics Research

Laboratory of the University of California, Berkeley (1975).

� HSPICE is a robust industry standard.

Circuit simulators like SPICE numerically solve device models and Kirchoff’s laws to determine time-domain

circuit behavior.

Numerical solution allows more sophisticated models

and non-functional (table-driven) models.

Written in FORTRAN for punch-card machines

� – Circuits elements are called cards

� – Complete description is called a SPICE deck


Lecture 3


Writing SPICE Deck

Writing a SPICE deck is like writing a good program

� – Plan: sketch schematic on paper or in editor

� Modify existing decks whenever possible

� – Code: strive for clarity

� Start with name, email, date, purpose

� Generously comment

� – Test:

� Predict what results should be

� Compare with actual

� Garbage In, Garbage Out!


Lecture 3


Source

DC Source� Vdd vdd gnd 2.5

Piecewise Linear Source� Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps

1.8

Pulsed Source� Vck clk gnd PULSE 0 1.8 0ps 100ps 100ps

300ps 800ps


Lecture 3


MOSFET Element

M element for MOSFET� Mname drain gate source body type

� + W=<width> L=<length>

� + AS=<area source> AD = <area drain>

� + PS=<perimeter source> PD=<perimeter drain>


Lecture 3


Common Elements & Units


Lecture 3


Example: RC Circuit


Lecture 3


Simulation Result (Textual)

.plot v(in) v(out)


Lecture 3


Simulation Result (Graphical)


Lecture 3


DC Analysis


Lecture 3


IV Characteristics Result


Lecture 3


Transient Analysis


Lecture 3


Transient Result


Lecture 3


layout view

schematic view

symbol view

Cell View

View name and view type are defined in technology file.


Lecture 3


Subcircuits

Declare common elements as subcircuits� .subckt inv a y N=4 P=8

� M1 y a gnd gnd NMOS W='N' L=2

� + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10'

� M2 y a vdd vdd PMOS W='P' L=2

� + AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10’

� .end

Ex: Fanout-of-4 Inverter Delay

� – Reuse inv

� – Shaping

� – Loading


Lecture 3


Example: FO4 Inverter Delay(1/3)


Lecture 3




Lecture 3


SPICE MOSFET Models

Level 1: Based on the Shichman-Hodges equations that are similar hand analysis

� Not very accurate

� Simple channel length modulation

� Simple body effect model

Level 2: Based on the Grove-Frohman equations

� more accurate model and fast (effective channel length, etc.)

Level 3: Based on the empirical equations

� more accurate model and fast (effective channel length, etc.)

BSIM (Berkeley Short-Channel Insulated Gate Field Effect

Transistor Model): efficient empirical model

� BSIM1 (level 13), BSIM2 (level 39), BSIM3v3 (level 47), BSIM4 (level 54),


Lecture 3


Some SPICE Model Parameters

L: transistor length

W, : transistor width

KP: transconductance

GAMMA: body bias factor

AS, AD: source/drain areas

CJSW: zero-bias sidewall capacitance

CGBO: zero-bias gate/bulk overlap capacitance


Lecture 3


Level 1 MOS FET Model


Lecture 3


Outlines

Introduction

SPICE Simulation

Design Rules



Layout

� Stick Diagram

� Layout Diagram

Conclusion


Lecture 3


Why We Need Design Rules

Manufacturing processes have inherent limitations in accuracy.

Design rules can be

� constructing process masks

� specifying geometry of masks which will provide reasonable yields.

� determined by experience.

Interface between designer and process engineer

Unit dimension of design rules: Minimum line width

� scalable design rules: lambda parameter

� absolute dimensions (micron rules)


Lecture 3


Manufacturing and Transistor Problems

Manufacture

� Photoresist shrinkage.

� Variations in material deposition.

� Variations in temperature.

� Variations in oxide thickness.

� Impurities.

� Variations across a wafer.

Transistor

� Variations in threshold voltage:

� oxide thickness;

� ion implantation;

� poly variations.

� Changes in source/drain diffusion overlap.

� Variations in substrate.


Lecture 3


Wiring Problems

Diffusion: changes in doping -> variations in

resistance, capacitance.

Poly, metal: variations in height, width ->

variations in resistance, capacitance.

Shorts and opens:

Short

Open


Lecture 3


Oxide and Via Problems

Variations in height

Via may not be cut all the way through.

Undersize via has too much resistance.

Via may be too large and create short.

metal 1metal 2

metal 2


Lecture 3


Scalable Design Rules

Designed to scale across a wide range of technologies.

Designed to support multiple vendors.

Designed for educational use.

Scalable design rules

� λ is the size of a minimum feature.

� Specifying λ particularizes the scalable rules.

� Parasitics are generally not specified in λ units.


Lecture 3


Types of Wire, Contact, Vias

Types of contact:

� n/p diffusion – metal 1

� n/p diffusion – poly

� Metal1- poly

� Well/Tub tie

Via:

� Metal1- metal2.

Types of wires:

� Metal 1

� Poly

� Diffusion


Lecture 3


Active and Select


Lecture 3


MOSIS Scalable Design Rule


Lecture 3




Lecture 3


Well (1/2)

0 0 0

Minimum spacing between wells of different types (if both are drawn)

1.4

6 66

Minimum spacing between wells at same potential

1.3

18 189

Minimum spacing between wells at different potential

1.2

12 12 10 Minimum width 1.1

DEEP SUBM SCMOS

Lambda Description Rule

http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html#references


Lecture 3


Well (2/2)


Lecture 3


Active/Diffusion (1/2)

4 4 4

Minimum spacing between non-abutting active of different implant. Abutting active ("split-active") is illustrated under Select Layout Rules.

2.5

3 3 3 Substrate/well

contact active to well edge

2.4

6 6 5 Source/drain active

to well edge 2.3

3 3 3 Minimum spacing 2.2

3 3 * 3 * Minimum width 2.1

DEEP SUBM SCMOS



Lecture 3


Active/Diffusion (2/2)


Lecture 3


Poly 1 (1/2)

1 1 1 Minimum field poly to

active 3.5

4 3 3 Minimum active

extension of poly 3.4

2.5 2 2 Minimum gate

extension of active 3.3

4 3 2 Minimum spacing

over active 3.2.a

3 3 2 Minimum spacing

over field 3.2


DEEP SUBM SCMOS

Lambda

Description Rule


Lecture 3


Poly 1 (2/2)


Lecture 3


Poly 2 for Capacitor (1/2)

n/a 2 2 Minimum spacing to unrelated metal

11.6

n/a 6 3 Minimum spacing to

poly contact 11.5

n/a 2 2

Minimum spacing to active or well edge (not illustrated)

11.4

n/a 52Minimum poly

overlap 11.3

n/a 33Minimum spacing 11.2

n/a 7 3Minimum width 11.1

DEEP SUBM SCMOS

Lambda

Description Rule


Lecture 3


Poly 2 for Capacitor (2/2)


Lecture 3


Poly 2 for Transistor (1/2)

n/a 3 3 Minimum spacing

to poly or active contact

12.6


or overlap of poly

12.5


to active 12.4

n/a 2 2 Minimum electrode

gate overlap of active

12.3

n/a 33 Minimum spacing 12.2

n/a 2 2 Minimum width 12.1

DEEP SUBM SCMOS

Lambda

Description Rule


Lecture 3


Poly 2 for Transistor (2/2)


Lecture 3


Select (1/2)

2 12

Minimum select width and spacing (Note: P-select and N-select may be coincident, but must not overlap) (not illustrated)

4.4

1.5 1 1 Minimum select overlap of

contact 4.3

2 2 2 Minimum select overlap of

active 4.2

3 3 3

Minimum select spacing to channel of transistor to ensure adequate source/drain width

4.1

DEEP SUBM SCMOS

Lambda

Description Rule


Lecture 3


Select (2/2)


Lecture 3


Contact to Poly 1

2 2 2 Minimum spacing to gate of transistor 5.4

4 3 2 Minimum contact spacing 5.3

1.5 1.5 1.5 Minimum poly overlap 5.2

2x2 2x2 2x2 Exact contact size 5.1

DEEP SUBM SCMOS



Lecture 3


Metal 1 (1/2)

6 6 4

Minimum spacing when either metal line is wider than 10 lambda

7.4

1 1 1 Minimum overlap of any contact

7.3

3 3 2 Minimum spacing 7.2


DEEP SUBM SCMOS

Lambda

Description Rule


Lecture 3


Metal 1 (2/2)


Lecture 3


Metal 2 (1/2)

8 6 6 n/a n/a 6

Minimum spacing when either metal line is wider than 10 lambda

9.4

1 1 1 n/a n/a 1 Minimum overlap of via1

9.3

4 3 3 n/a n/a 3 Minimum spacing

9.2

3 3 3 n/a n/a 3 Minimum width

9.1

DEEP SUBM SCMOS DEEP SUBM SCMOS

3+ Metal Process 2 Metal Process

Lambda

Description Rule


Lecture 3


Metal 2 (2/2)


Lecture 3


Via (1/2)

n/a 2 2 n/a n/a 2

Minimum spacing to poly or active edge for technology codes mapped to processes that do not allow

8.5

n/a 2 2 n/a n/a 2

Minimum spacing to contact for technology codes mapped to processes that do not allow

8.4

1 1 1 n/a n/a 1 Minimum overlap by metal1

8.3

3 3 3 n/a n/a 3 Minimum via1 spacing 8.2

3 x 3 2 x 2 2 x 2 n/a n/a 2 x 2 Exact size 8.1

DEEP SUBM SCMOS DEEP SUBM SCMOS

3+ Metal Process 2 Metal Process

Lambda

Description Rule


Lecture 3


Via (2/2)


Lecture 3


Capacitance Well

n/a 6 5 Minimum overlap of

active 17.4

n/a 6 5 Minimum spacing to

external active 17.3

n/a 18 9 Minimum spacing 17.2

n/a 12 10 Minimum width 17.1

DEEP SUBM SCMOS



Lecture 3


Micron Design Rule (1/2)


Lecture 3


Micron Design Rule (2/2)


Lecture 3


Outlines

Introduction

SPICE Simulation

Design Rules



Layout

� Stick Diagram

� Layout Diagram

Conclusion


Lecture 3


Stick Diagrams

A stick diagram is a cartoon of a layout.

Does show all components/vias (except possibly tub

ties), relative placement.

Does not show exact placement, transistor sizes,

wire lengths, wire widths, tub boundaries.


Lecture 3


Buffer Circuit Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2

Stick Diagram


Lecture 3


Stick Layers

metal 3

metal 2

metal 1

poly

ndiff

pdiff


Lecture 3


Stick Design of 3-bit Multiplexer

When select=0, the data output’s value is equal to the b

data input’s value; if select =1, the data output’s value is

equal to a.

Oi=(ai & select) + (bi & select’) = NAND (NAND (ai, select),

NAND (bi, select’))

Start with NAND gate:

+

ab

out

NAND


Lecture 3


NAND Sticks

VDD

a

VSS

out

b


Lecture 3


One-bit mux Sticks

VDD

VSS

N1

(NAND)sele

ct’ out

a

b

N1

(NAND)

out

a

b

N1

(NAND)

out

a

b

sele

ct

ai

bi


Lecture 3


3-bit mux Sticks

m2(one-bit-mux)

select’ select VDD

VSS

oiai

bi

m2(one-bit-mux)


VSS

oiai

bi

m2(one-bit-mux)


VSS

oiai

bi

select’ select

a2

b2

a1

b1

a0

b0

o2

o1

o0


Lecture 3


Inverter and NAND3

Stick diagrams help plan layout quickly

� Need not be to scale

� Draw with color pencils or dry-erase markers


Lecture 3


Example: Inverter

Layout can be very time

consuming

� Design gates to fit together nicely

� Build a library of standard cells

Standard cell design

methodology

� VDD and GND should abut (standard height)

� Adjacent gates should satisfy design rules

� nMOS at bottom and pMOS at top

� All gates include well and substrate contacts


Lecture 3


Example: NAND3

Horizontal N-diffusion

and p-diffusion strips

Vertical polysilicon

gates

Metal1 VDD rail at top

Metal1 GND rail at bottom


Lecture 3


NAND Gate


Lecture 3


NAND Gate and Layout

+

ba

out

b

a

out

VDD

GND

tub

ties


Lecture 3


NOR Gate


Lecture 3


NOR Gate and Layout

b

a

out

a

b

out

VDD

GND

tub ties


Lecture 3


Conclusion

Widely discuss the following items:� SPICE

� Design Rules

� Stick Diagram

� Layout Diagram


Lecture 3


Reference

Neil Weste and David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 4rd, 2005.

Wayne Wolf, “Modern VLSI Design/System-on-Chip Design”, 3rd, 2002

CIC Training Manual

http://www.mosis.org/Technical/Designrules/scmos/s

cmos-main.html#references

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