digital systems design lab 1 ta : 曾興嘉 [email protected]
TRANSCRIPT
Lab RequirementsLab Requirements
• Write Hardware Description Language (HDL)– Verilog
• The verilog code must:– be able to be synthesized– pass the patterns
• Basic Requirements: 70% of the grades• Competing with others: 30% of the grades
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Lab ScheduleLab Schedule
• 3 Labs– Lab1: Key Arithmetic Units (5%)
• Date: 3/29~4/13
– Lab2: Sequencing and Control Circuits (5%)• Date: 4/13~5/4
– Lab3: Simple RISC Central Processing Units (10%)• Date: 5/4~6/8
• Late submission:– one week from due date: 60%– more than one week: 0%
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EnvironmentEnvironment SetupSetup
• The software must run on workstations based on linux distribution because of the license issue.
• The users can use Pietty to telnet to the workstation and acquire windows-like interface via Xming.
• Tool– Pietty
• http://ntu.csie.org/~piaip/pietty – Xming
• http://sourceforge.net/projects/xming
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EnvironmentEnvironment Setup (Xming)Setup (Xming)• Open Xming
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No Access Control
EnvironmentEnvironment Setup (Pietty)Setup (Pietty)
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•Server: 140.113.241.168
Set X11 Forwarding in PiettySet X11 Forwarding in Pietty
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FTPFTP
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Basic Unix CommandsBasic Unix Commands
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• cp file1.v file2.v– Make a copy of file1.v called file2.v
• cp ~/dir1/file1.v .– Make a copy of ~/dir1/file1.v in your current directory– “.” means your current directory– “~” means your home directory
• rm file1.v– Delete file1.v
• mkdir dir1– Make a new directory called dir1
• cd dir1– Change the current directory to dir1
• cd ..– Change the current directory to the upper directory
• more file1.v– View the content of file1.v
• ls– List all the files in the current directory
• pwd– Display the name of the current directory
Cell-based Design Flow OverviewCell-based Design Flow Overview
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• A design flow is a set of procedures that allows designers to progress from a specification for a chip to the final chip implementation in an error-free way.
Cell-based Design FlowCell-based Design Flow
Specification DevelopmentSystem Models
Specification DevelopmentSystem Models
RTL code developmentFunctional VerificationRTL code developmentFunctional Verification
SynthesisTiming Verification
SynthesisTiming Verification
Physical Synthesis/Place and RoutePhysical Verification
Physical Synthesis/Place and RoutePhysical Verification
PrototypeBuild and Test
PrototypeBuild and Test
System Architecture
RTL
Synthesis
Physical Design
System Integration and Software Test
Source: CM: 5086 VLSI Design Lab
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Implement your own verilog program
Need to pass the provided testbench
Synthesis your logic with provided (or
modify by yourself) tcl file
Implement your own verilog program
Need to pass the provided testbench
Synthesis your logic with provided (or
modify by yourself) tcl file
Use your(provided) netlist file to run
the Auto Place and Route (APR) flow
Use your(provided) netlist file to run
the Auto Place and Route (APR) flow
Stage 1
Stage 1
Stage 2
Stage 2
Cell-based Design ToolCell-based Design Tool
• System Architecture/SW simulation– C/C++, Matlab, System C, System Verilog…
• RTL simulation/debug– NC-Verilog, NC-VHDL, ModelSim, Verdi(nWave)… (without delay)
• Synthesis– RTL Compiler, Design Compiler , Power Compiler…
• Gate level simulation/debug– NC-Verilog, NC-VHDL, ModelSim, Verdi(nWave)… (with delay)
• Physical Design– SoC Encounter, Astro, IC Compiler…
• Others– PrimePower , Calibre, Nanosim…
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RTL SimulationRTL Simulation
• Development / simulation– NC-verilog
• ncverilog + <your_testbench_file>• ncverilog TESTBED.v +access+r
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RTL WaveformRTL Waveform
• Check the simulation output– Dump waveform from testbench when simulation
• fsdbDumpfile(“MAC.fsdb”);
– nWave• nWave &
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RTL SchematicRTL Schematic
• Verdi from NOVAS– Verdi &– File->Import Design ->From File ->Seq_MAC16.v ->Add ->OK
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SynthesisSynthesis
• Synthesis=translation+ optimization+ mapping
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Residue = 16’h0000;If(high_bits==2’b10)
residue = state_table[i];Else state_table[i] = 16’h0000;
HDL Source(RTL)
Translate(HDL Compiler)
Optimize + Map (Design Compiler)
Generic Boolean
Target Technology
NO Timing Info =>
Timing Info =>
Source: CIC Jan.08 Design Compiler
SynthesisSynthesis
• Design Compiler– It synthesizes your designs (Verilog) into optimized
technology-dependent, gate-level designs.
• Use Design Compiler GUI– tartup xming ( or any other X terminal application)– design_vision (dv)
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SynthesisSynthesis
• Environment Setup– /home directory/.cshrc : set path and license of synthesis
tool– /your working directory/.synopsys_dc.setup : setup
technology file, designware library file…etc
• Use DC-TCL script file(.tcl)– Set design constraints– dv -f syn.tcl
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SynthesisSynthesis
• Put the “RTL file”, “.synopsys_dc.setup” and “syn.tcl” to your working directory, or assert the setup commands by hand, while synthesis.
• Under your working directory, make new directories, Report and Netlist, for saving synthesis reports.
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SynthesisSynthesis
• Output result
commandCommand return result(error)
command
Command return result(done)
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Synthesis ReportSynthesis Report
• The synthesis information is in your “Report” directory
timing.txt
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Gate Level WaveformGate Level Waveform
• Check the simulation output– nWave
• nWave &
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Gate Level SchematicGate Level Schematic
• Verdi from NOVAS– Verdi &– File->Import Design -> From File -> Netlist/Seq_MAC16_SYN.v ->Add
-> /cad/designkit/CBDK_IC_Contest_v2.0/Verilog/tsmc13_neg.v ->Add -> OK
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Verilog Basic ModuleVerilog Basic Module
module module_name(port_name);port declarationdata type declarationtask & function declarationstructure or module functionality
endmodule
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Lexical ConventionLexical Convention
• Number Specification– <size>’<base><value>
• <size> is the length in bits• <base> can be b(binary), o(octal), d(decimal) or h(hexadecimal)• <value> is any legal number in the selected base• e.g. 8’d11 = 8’b00001011 = 8’h0b• e.g. 12’hz = zzzz zzzz zzzz (high impednace)• e.g. 6’bx = xx xxxx (unknown value)
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Lexical ConventionLexical Convention
• Operators– Arithmetic Description
• A = B + C;• A = B – C;• A = B * C;• A = B / C;• A = B % C;• / and % are not supported in most synthesis tools.
– Shift Operator (bit-wise)• A = B >> 2; // shift right ‘B’ by 2-bits• A = B << 3; // shift left ‘B’ by 3-bits
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Lexical ConventionLexical Convention
• Operators– Bit-wise operator
• A = ~B; // not• A = B & C; // and• A = B | C; // or• A = B ^ C; // xor• e.g. 4’b1001 | 4’b0101 => 4’b1101
– Logical operators (return 1-bit result)• A = !B;• A = B && C;• A = B || C;• e.g. 4’0101 || 4’b1101 => 1’b1
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Lexical ConventionLexical Convention
• Operators– Conditional Description
• if else• case endcase• C = sel ? A : B; //if(sel==1’b1) then C=A, else C=B
– Relational and equality(conditional)• <=, <, >, >=, ==, !=
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Lexical ConventionLexical Convention
• Operators– Concatenation
• { }=> a = {b, c};
• {{}}=> a = {2{c}};
• a[3:0] = {d[2:0], 1’b0};
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Data TypeData Type
• Declaration Syntax– <data_type> [<MSB>:<LSB>] <list_of_identifier>
• <data_type>: There are two groups of data types: “register” and “net” in Verilog.
• e.g. wire temp; // 1-bit net• e.g. reg temp; // 1-bit register• e.g. wire [7:0] temp; // 8-bits bus, temp[7] is the MSB• e.g. wire [0:7] temp; // 8-bits bus, temp[0] is the MSB• e.g. reg [4:0] temp;• e.g. reg signed [4:0] temp;• e.g. wire signed [7:0] temp;
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PortPort
• Port declaration– input : input port– output : output port– inout : bidirectional port
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Module ConnectionModule Connection
• 1. connected by port order– MAC16 Com_MAC(REG_IN1,REG_IN2,REG_OUT,OUT);
• 2. connect by name– MAC16 Com_MAC(.a(REG_IN1),.b(REG_IN2),.c(REG_OUT),.out(OUT));
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Sequential LogicSequential Logic
• always@(posedge clk or posedge reset)• always@(negedge clk)
• always@(posedge clk)begin
if(reset) qout<=1’b0;else qout<=din;
end
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DFF
clk
din qout
Combinational LogicCombinational Logic
• 1. wire a,b,sel,out; assign out=(sel)?a:b;
• 2. wire a,b,sel; reg out; always@(a or b or sel) begin
if(sel) out=a;else out=b;
end
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a
b
sel
out1
0
Combinational LogicCombinational Logic
• Full casealways@(a or b or c or d or num) begin
case(num)2’d0: out=a;2’d1: out=b;2’d2: out=c;2’d3: out=d;
endcase end
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01
11
00
10
num
a
b
c
d
out
Combinational LogicCombinational Logic
• Incomplete casealways@(a or b or c or d or num) begin
case(num)3’d0: out=a;3’d1: out=b;3’d2: out=c;3’d3: out=d;
endcase end
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01
11
00
10
num
a
b
c
d
out
Latch
add Default: out=a; can avoid latch