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C 5: N
HDL
1
I. INRODCION
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VHDL = VHSIC Hardware Description
Language(VHSIC = Very High Speed Integrated Circuit)
HDL . I ,
.
HDL fi I
E E E
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II. CODE STRUCTURE
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1.
A HDL :
LIBRAR : C .
ENTIT: Sfi I/O .
ARCHITECTURE: C HDL ,
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Fundamental sections of a VHDL code
2.
T LIBRAR ,
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EX:LIBRARY ieee;USE ieee.std_logic_1164.all;Using std_logic_1164 package from the ieee library
EX:LIBRARY std;USE std.standard.all;Using standard package from the std library
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:
std_logic_1164: Specifies the STD_LOGIC (8 levels)
and STD_ULOGIC (9 levels) multi-valued logic
systems.
std_logic_arith: Specifies the SIGNED and
UNSIGNED data types and related arithmetic and
comparison operations.
std_logic_signed: Contains functions that allow
operations with STD_LOGIC_VECTOR data to beperformed as if the data were of type SIGNED.
std_logic_unsigned: Contains functions that allow
operations with STD_LOGIC_VECTOR data to be
performed as if the data were of type UNSIGNED10
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3. A ENTIT fi (PORTS)
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3 ENTITY (tt)
T IN, OUT, INOUT, BUFFER.
T BIT, STDLOGIC,INTEGER,..
, HDL
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Example: entity of the NAND gate
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:
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E: M
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ENTITY mux ISPORT (a, b : IN std_logic_vector (7 downto 0);
sel : IN std_logic_vector (0 to 1);c: OUT std_logic_vector (7 downto 0));
END mux;
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4. ARCHIECRE
T ARCHITECTURE . I :
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4. ARCHITECTURE (tt)
A : S
T : L
T N ( HDL ) , .
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E : NAND .
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III. DATATYPES
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1.
S, .
S , ,
A :
A : := ;
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2.
. A , ,
.
A :
AAB : := ;
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Reference from : http://www.edaboard.com/thread19065.html
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ENTITY mux IS
PORT (i0, i1, i2, i3, a, b : IN
std_logic;q : OUT std_logic);
END mux;
ARCHITECTURE wrong of mux IS
SIGNAL muxval : INTEGER;
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
BEGIN
muxval
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3. C C
A :
A : := ;
:
CONSTANT PI: REAL := 3.1414;
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4. PDfi D. ( ): 2 0, 1
Examples:
SIGNAL x : BIT;
x
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. SDLOGIC ( SDLOGICECOR):8 1164 .
F U
0 F L
1 F H
H
L
H D
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Examples:
SIGNAL x: STD_LOGIC;
-- x is declared as a one-digit signal of type STD_LOGIC.
SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0)
-- y is declared as a 4-bit vector, with the leftmost bit being
the MSB.
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. INEGER PES
INTEGER TYPES are exactly like mathematical integers.
All of the normal predefined mathematical functions like
add, subtract, multiply, and divide apply to integer types
the integer range is specified from -2,147,483,647 to
2,147,483,647
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Examples:
A
B
()
AAB : ;
AAB : ;
B
:= 1;
:= 1;
:= 1.5;
;
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. REAL PESR
. T
Real numbers ranging from -1.0E38 to +1.0E38.
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5. PHSICAL PESP
, , , .
A , . T ;
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:
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SUMMARY:
BOOLEAN: True, False.
INTEGER: 32-bit integers (from -2,147,483,647 to
+2,147,483,647).
NATURAL: Non-negative integers (from 0 to
+2,147,483,647).
REAL: Real numbers ranging from -1.0E38 to+1.0E38.
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6. D D VHDL allows the user to define his/her own data types. It
calls User-defined integer type
Ex1:
TYPE integer IS RANGE -2147483647 TO +2147483647;
-- This is indeed the pre-defined type INTEGER.
TYPE my_integer IS RANGE -32 TO 32;
-- A user-defined subset of integers
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6. D D ()E2:
TPE IS ('0', '1');
T BIT
('0', '1', '');
A .
E 3:
TPE IS (, , , );
A , .
TPE IS (, , , );
A .
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7. A
. Arrays can be one-dimensional(1D), two-dimensional (2D)
T :
S: BIT, STDLOGIC, STDULOGIC, BOOLEAN.
: BITECTOR, STDLOGICECTOR,
STDULOGICECTOR, INTEGER, SIGNED, UNSIGNED.
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Example:
-- 1D array
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
-- 1Dx1D array
TYPE matrix IS ARRAY (0 TO 3) OF row;
.
SIGNAL y: row;
SIGNAL x: matrix;
.y := 11110000 -- OK
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IV. OPERATORS AND ATTRIBUTES
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1.
U OTHERS.
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:
SIGNAL : STDLOGIC;
ARIABLE : STDLOGICECTOR(3 DONTO 0);
L MSB
SIGNAL : STDLOGICECTOR(0 TO 7);
R MSB
:
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2
2. T :
NOT, AND, OR, NAND, NOR, OR, NOR
T BIT, STDLOGIC,STDULOGIC,BITECTOR,STDLOGICECTOR,
STDULOGICECTOR
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2
+ A S
* M
/ D
** E
MOD M
REM R
ABS A
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4. U . T . T :
= E
/= N
< L
> G
= G S O
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2
6. LO: R
HIGH: R
LEFT: R
RIGHT: R
LENGTH: R
RANGE: R
REERSERANGE: R
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AL(): R
POS(): R
LEFTOF(): R
AL(, ): R
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Example: Consider the following signal:SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
Then:
d'LOW=0, d'HIGH=7
d'LEFT=7, d'RIGHT=0
d'LENGTH=8,
d'RANGE = (7 downto 0),
d'REVERSE_RANGE = (0 to 7).
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7.
EENT: R
STABLE: R
ACTIE: R = 1
QUIET : R
LASTEENT: R
LASTACTIE: R = 1
LASTALUE: R
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:IF ('EENT AND ='1')... EENT
IF
IF (NOT 'STABLE AND ='1')... STABLE IF
AIT UNTIL ('EENT AND ='1'); EENT AIT
IF RISINGEDGE()...
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8. GENERIC
( , ).T .
A GENERIC ENTIT. I :
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2
:
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: 2
;
.1164.;
( : := 2);
(,: ( 1 0);
: ; : ( 1 0);
: );
;
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(,,) : ( 0);
(0) := ;
0 ( 1)
()
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2
1 C S L
,
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3
2. C S CHDL (). O
PROCESS, FUNCTION, PROCEDURE .
I .
T , . I,
, .
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3. C
I , :
O;
T HEN :
(HEN/ELSE ITH/SELECT/HEN);
T GENERATE ;T BLOCK .
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4. O.
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3
63
f
x3
x1
x2 A
B
Library ieee;
Use IEEE.std_logic_1164.all;
Entity example1 IS
END example1;
ARCHITECTURE Lfun of example1 is
Signal A,B : std_logic;
BEGIN
END Lfun;
f
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T .
signal_name
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: 4 1
T :
S 1: HEN/ELSE
S 2: ITH/SELECT/HEN
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6. SS :
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E 2 : E 83
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E 3: AL
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E 1 :
38
E 2:
D
: ( )
: ( )
......77
.
B : 2 :
78
Ket qua:..\..\..\baitapvhdl\alu\alu.qpf
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6. GENERAEGENERATE . I .
/ A:
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:
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VI. SEQUENTIAL CODE
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1. PROCESS
A PROCESS HDL . I IF, AIT, CASE, LOOP, . A PROCESS , .
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S PROCESS:
VARIABLES are optional. If used, they must be declared in
the declarative part of the PROCESS. The initial value isnot synthesizable, being only taken into consideration insimulations.
2. IF
IF, AIT, CASE, LOOP . T, PROCESS, FUNCTION, ROCEDURE.
T IF :
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E 1: D C
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E 2: D C
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Exercise 3: write code for the circuit below
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LIBRAR ;
USE .1164.;ENTIT ISPORT ( , : IN STDLOGICECTOR (7 DONTO 0);
: IN STDLOGICECTOR(1 DONTO 0); : OUT STDLOGICECTOR (7 DONTO 0));
END ;ARCHITECTURE OF ISBEGINPROCESS (, , )
BEGINIF ( = "00") THEN
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4:
A , ().
R =1, = 0, .O, = 0 1
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1:
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ENTITY example IS
PORT ( a, b, clk: IN BIT;
q: OUT BIT);
END example;
---------------------------------------
ARCHITECTURE example OF example IS
SIGNAL temp : BIT;
BEGIN
temp
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95
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4. C
A
1 =>
A ;
2 =>
B ;
:
=>
P ;
A;
Value_1
Value_2
Statements A
Statements B
Statements A
NO
NO
yes
yes
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E 1: D 24
case A is
when 00 => y y y y y
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Code VHDL dem 2 digit.pdf
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Design a Two-digit Counter (00 12)E 2:
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Exercise 1
Design a Two-digit Counter (00 24), using decoder
BCD to led 7 segment
101
Counter
00 - 24
74LS47
74LS47
ckDigit 2
Digit 1
RESET
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5. AI
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AI NIL
T AIT UNTIL .S PROCESS , AIT
UNTIL PROCESS. TPROCESS .
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105
AI ONAIT ON, ,
. T PROCESS . I , PROCESS .
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E: 8 PROCESS
BEGIN
AIT ON , ;
IF (='1') THEN
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6. LOOP
T LOOP . L IF, AIT, CASE,LOOP , PROCESS, FUNCTION, PROCEDURE.
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FOR / LOOPT
T :
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HILE / LOOPT
T :
111
112
E 1: D C R A 8
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113
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E 2 : FSM
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E 3 : FSM
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121
E: L C
Link to Chapter 8 ( /page 186)
MIT.P,.C.D..HDL.(2004).TLFUE.
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VI. PACKAGES AND
COMPONENTS
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Fundamental units of VHDL code.
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1. A COMPONENT .
H, COMPONENT, , .
A COMPONENT .
:
flfl, , , , ..
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:
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:
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:
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128
Example: Write code for the circuit below
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133
2. PACKAGESA , ,
, .
A : , ,
, . T
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:
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137
Example:
E: , = . + .
()
;
.1164.;
( : ; : );
;
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;
.1164.;
(, : ; : );
;
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; .1164.;
(: ;
: );
;
(, : ; : );
;141
(, : ; : );
;
;
----top module------
library ieee;
use ieee.std_logic_1164.all;
use work.mycomponent.all;
entity mypackage is
port (a,b : in std_logic;
y : out std_logic);
end mypackage;
architecture mypackage of
mypackage issignal d1,d2,d3,d4 : std_logic;
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beginu1 : congdao port map (a,d1);u2 : congand port map (d1,b,d3);u3 : congdao port map (b,d2);u4 : congand port map (a,d2,d4);u5 : congor port map (d3,d4,y);end mypackage;
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143
exercise 1: Design combinational circuit
exercise 2: Design A 16-to-1 mux using 4-to-1 mux
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THANK YOU!
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