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A great Ultra Wideband (3.1-10.6-GHz) LNA in 0.18-μm (CMOS) for UWB Pulse-Radio Systems applications Hadi Goodarzi Dehrizi Faculty of Electrical Engineering Sabzevar Tarbiat Moallem University Sabzevar, Iran [email protected] Javad Haddadnia Faculty of Electrical Engineering Sabzevar Tarbiat Moallem University Sabzevar, Iran [email protected] Abstract This paper presents an Ultra-Wideband (UWB) Low-Noise Amplifier (LNA) which its frequency range is from 3.1 to 10.6 GHz using 0.18-μm CMOS at 25 0 C. Simulation results show that the IIP3 is about 1dBm at 6GH and the Noise Figure (NF) ranges from 3.41-4.47 dB over the band of interest. Input matching is better than -12.81dB, S12 below - 27.51 dB, S22 below -13.05 dB ,S21 10.16 ± 1 and the power consume is 6.36mW at 1V supply voltage .The proposed LNA topology is very suitable for UWB pulse-radio system applications. Keywords CMOS, Low-Noise Amplifier (LNA), Ultra Wideband (UWB), low power. I. INTRODUCTION Recently, RF-CMOS processes have become more and more popular for RFICs designs, because it is cost-effective and compatible with the silicon-based system-on-a-chip (SOC) technology [1,2]. The current-reused cascade amplifier has become one of the most popular LNA topologies due to its merits such as low power consumption, high gain, and high reverse isolation [3].In Ultra-Wideband (UWB) receiver front-end design, the UWB low-noise amplifier (LNA) is a critical block that receives small signals from the whole UWB band (3.1–10.6 GHz) and amplifies them with a good signal-to-noise ratio property. In addition, high and flat power gain, good input and output impedance matching, and low and flat Noise Figure (NF) performances across the whole UWB band are required. Recently, several CMOS UWB LNAs have been reported [1, 4]. For an UWB LNA designed in OFDM systems [1], power linearity is a tight requirement for suppressing adjacent channel interferences, while it is relaxed in the UWB pulse-radio system [5]. Many wideband input- matching networks for UWB LNAs have been proposed lately. For instance, a wideband input matching with small power dissipation and die size can be realized by the common-gate input topology [6]. Nevertheless, it was found that single-stage common-gate amplifier cannot provide sufficient power gain, and hence, extra stages are required to boost the gain, resulting in ripples in the passband due to the nonbroadband inter-stage matching. Besides, in [1], a cascade CMOS LNA with a bandpass response at the input for wideband impedance matching was reported. The three-order Chebyshev-filter-based topology incorporated the input impedance of the conventional narrowband cascade amplifier as a part of the filter. However, the adoption of the filter at the input required a number of additional reactive elements (four, i.e., L1, C1, L2 andC2 in [1]), which inevitably resulted in larger die size and higher NF (due to the finite quality factor (Q factor) of the reactive elements) when implemented on-chip. In this paper, we have designed a 0.18μm CMOS UWB LNA with excellent power consumption, input impedance matching, IIP 3 and NF performances, which is suitable for UWB pulse-radio system applications. Fig. 1: complete schematic 978-1-4673-1591-3/12/$31.00 ©2012 IEEE

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Page 1: [IEEE 2012 IEEE 9th International Multi-Conference on Systems, Signals and Devices (SSD) - Chemnitz, Germany (2012.03.20-2012.03.23)] International Multi-Conference on Systems, Sygnals

A great Ultra Wideband (3.1-10.6-GHz) LNA in 0.18-μm (CMOS) for UWB Pulse-Radio Systems

applicationsHadi Goodarzi Dehrizi

Faculty of Electrical EngineeringSabzevar Tarbiat Moallem University

Sabzevar, [email protected]

Javad HaddadniaFaculty of Electrical EngineeringSabzevar Tarbiat Moallem University

Sabzevar, [email protected]

Abstract — This paper presents an Ultra-Wideband (UWB) Low-Noise Amplifier (LNA) which its frequency range is from 3.1 to 10.6 GHz using 0.18-μm CMOS at 25 0C. Simulation results show that the IIP3 is about 1dBm at 6GH and the Noise Figure (NF) ranges from 3.41-4.47 dB over the band of interest. Input matching is better than -12.81dB, S12 below -27.51 dB, S22 below -13.05 dB ,S21 10.16 ± 1 and the power consume is 6.36mW at 1V supply voltage .The proposed LNA topology is very suitable for UWB pulse-radio system applications.Keywords — CMOS, Low-Noise Amplifier (LNA), Ultra Wideband (UWB), low power.

I. INTRODUCTION

Recently, RF-CMOS processes have become more and more popular for RFICs designs, because it is cost-effective and compatible with the silicon-based system-on-a-chip (SOC) technology [1,2]. The current-reused cascade amplifier has become one of the most popular LNA topologies due to its merits such as low power consumption, high gain, and high reverse isolation [3].In Ultra-Wideband (UWB) receiver front-end design, the UWB low-noise amplifier (LNA) is a critical block that receives small signals from the whole UWB band (3.1–10.6 GHz) and amplifies them with a good signal-to-noise ratio property. Inaddition, high and flat power gain, good input and output impedance matching, and low and flat Noise Figure (NF) performances across the whole UWB band are required. Recently, several CMOS UWB LNAs have been reported [1, 4]. For an UWB LNA designed in OFDM systems [1], power linearity is a tight requirement for suppressing adjacent channel interferences, while it is relaxed in the UWB pulse-radio system [5]. Many wideband input-matching networks for UWB LNAs have been proposed lately. For instance, a wideband input matching with small power dissipation and die size can be realized by the common-gate input topology [6]. Nevertheless, it was found that single-stage common-gate amplifier cannot provide sufficient power gain, and hence, extra stages are required

to boost the gain, resulting in ripples in the passband due to the nonbroadband inter-stage matching.

Besides, in [1], a cascade CMOS LNA with a bandpass response at the input for wideband impedance matching was reported. The three-order Chebyshev-filter-based topology incorporated the input impedance of the conventional narrowband cascade amplifier as a part of the filter.However, the adoption of the filter at the input required a number of additional reactive elements (four, i.e., L1, C1, L2 andC2 in [1]), which inevitably resulted in larger die size and higher NF (due to the finite quality factor (Q factor) of the reactive elements) when implemented on-chip. In this paper, we have designed a 0.18µm CMOS UWB LNA with excellent power consumption, input impedance matching, IIP3 and NF performances, which is suitable for UWB pulse-radio system applications.

Fig. 1: complete schematic

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978-1-4673-1591-3/12/$31.00 ©2012 IEEE

Page 2: [IEEE 2012 IEEE 9th International Multi-Conference on Systems, Signals and Devices (SSD) - Chemnitz, Germany (2012.03.20-2012.03.23)] International Multi-Conference on Systems, Sygnals

II. CIRCUIT DESIGN

We have designed this LNA by using advance design system (ADS) soft ware in 0.18µm technology. We should set a good tradeoff between important circuit parameters and power consumption, and have done it. Fig.1 shows the complete schematic of the 3.1-10.6 GHz CMOS UWB LNA. An LNA which composes of two cascaded common-source stages should be used for achieveding enough gain output, and this circuit has this feature. The output of each stage was equivalently loaded with a low-Q RLC parallel resonant circuit to maximize the 3-dB bandwidth of the gain. Peaking inductors L4 and L5 has effect on the S21 performance of the LNA. In addition to the purpose of self-biasing, the feedback resistor R3 is also beneficial for the output impedance matching. Based on the methodology in [7], simultaneous input impedance and noise matching over the 3.1-10.6-GHz-band of interest are achieved by appropriately selecting the values of L5, R3, L3, C1, and the size and bias of the input transistor M1, i.e. Cgs1, gm1, Cgs2, and gm2. Moreover, the inductive load L1 and L2 of the input and the output stage have made a low VDD of 1.0V possible since the voltage drop across them was negligible. This is the way to achieve low power consumption. To the best of my knowledge if we have a lower power supply we will have lower power consumption then we did it, but the other parameters were ruined. Therefore, we should make a good tradeoff between important Circuit parameters and power consumption based on tuning. A peaking inductor L4 is added to the gate-terminal of M1 to double the 3-dB bandwidth of the output stage, so the high-frequency poles of the LNA can be pushed outside of the 3.1-10.6-GHz-band of interest. As a result, the LNA exhibits flat S21, the best IIP3, sufficient s11 and excellent NF at the same time, comparable with other works.

(a)

(b)

Fig. 2 The simulated (a) input-return-loss S11 and output-return loss S22, (b) forward gain S21, versus frequency characteristics of the 3.1-10.6 GHz CMOS UWB LNA.

TABLE 1: SUMMARY OF CMOS WIDEBAND LNAs IN THIS STUDY, AND THE RECENTLY REPORTED STATE-OF-THE-ART CMOS WIDEBAND LNAs

[4] (0.18µm

CMOS)

[6] (0.18µm

CMOS)

[9] (0.13µm

CMOS)

[8] (0.18µm

CMOS)

[1] (0.18µm

CMOS)

This work

BW (GHz) 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6 3.1 ~ 10.6 3.1~10.6 S11 (dB) <-9.7 <-9 <-17.5 <-11.8 <-9.9 <-12.81 S22 (dB) <-8.4 <-13 <-14.4 <-12.7 <-13 <-13.05 S21 (dB) 11.25 ± .4 16.7±.8 7.92±.23 11.2 ± 2.3 6.65 ± 2.65 10.16± 1 S12 (dB) <-40 <-70 <-25.81 <-27.7 <-43 <-27.51

3-dB BW of S21 (GHz)

1.3 ~ 12.1 3.1 ~ 10.6 1.3 ~ 12.1 1.7 ~ 5.9 2.3 ~ 9.2 2.5 ~ 13.15

NF (dB) 4.12 ~ 5.16 3.1 ~ 5.7 2.5 ~ 4.56 3.61 ~ 4.68 4~9.3 3.41 ~ 4.47

NF(dB)@10.6-GHz

4.17 5.7 2.5 3.88 8.3 3.87

IIP3 .72 NA -4 -12 -6.7 1

Power consumption )mV(

22.7 33.2 10.68 10.34 9 6.36

Page 3: [IEEE 2012 IEEE 9th International Multi-Conference on Systems, Signals and Devices (SSD) - Chemnitz, Germany (2012.03.20-2012.03.23)] International Multi-Conference on Systems, Sygnals

III. SIMULATION RESULTS

Table 1 is a summary of the CMOS UWB LNA, and the

recently reported state-of-the-art CMOS UWB LNAs. As

can be seen, compared with other works, our CMOS UWB

LNA exhibits the flattest S21, the best IIP3 and NF, and has

a good S11, S22 and low power consumption. The results

show that our LNA is suitable for UWB pulse-radio system

applications.

The LNA was biased at 6.34mA and 1V. That is to say

the LNA only consumed 6mW power. Component

parameters of the LNA are listed as follows: L1 0.4nH, L2

1.6nH, L3 109pH, L4 319pH, L5 570pH, C1 1.61pF, C2

972.2fF, C3 16.18pF, R1 30Ω, R2 1KΩ, R3 300Ω, R4 1997Ω. All transistors had the same gate length of 0.18μ m. The

gate-width per finger/finger numbers of M1 and M2 were

7.22µm/22 and 8µm/21, respectively.

(a)

(b)

Fig. 3: The simulated (a) NF (b) stability factor, versus frequency characteristics of the 3.1-10.6 GHz CMOS UWB

LNA.

Fig. 2(a) shows the simulated S11 and S22 versus

frequency characteristics of the CMOS UWB LNA. S11 of -

12.81~ -38 dB was achieved over the 3.1-10.6-GHz-band of

interest .The simulated S22 versus frequency characteristics

of the CMOS UWB LNA. S22 of -13.05 ~ -33 dB was

achieved over the 3.1-10.6-GHz-band of interest. Fig. 2(b)

shows the simulated S21 versus frequency characteristics of

the CMOS UWB LNA. Flat S21 of 10.16± 1 dB was

achieved over the 3.1-10.6-GHz-band of interest. Fig. 3(a)

shows the simulated noise figure (NF) versus frequency

characteristics of the CMOS UWB LNA. Flat NF of 3.9 ±

0.5 dB was achieved over the 3.1-10.6-GHz-band of

interest. Fig. 3(b) shows stability factor (K) versus

frequency characteristics of the CMOS UWB LNA. Clearly,

the LNA is unconditionally stable over the 3.1-10.6-GHz-

band of interest because for achieving this parameter “K”

should be more than 1 and this LNA has this possible. Fig4

shows the simulation input third-order inter-modulation

point (IIP3) at 6 GHz of the CMOS UWB LNA. In this

work, IIP3 of 1 dBm is achieved.

Fig .4: The simulation IIP3 at 6 GHz of the CMOS UWB

LNA.

IV. CONCLUSION

A CMOS UWB LNA, which its power supply is 1v, with

a flat S21 and great S11 and S22 is designed. The frequency

rang of this LNA is 3.1-10.6 GHz. Also exhibits state-of-

the-art NF and low power consumption. These results

demonstrate that this LNA is very suitable for UWB pulse-

radio system applications.

REFERENCES

[1] A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS lownoise amplifier for 3.1–10.6-GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.

[2] Y. Park, C. H. Lee, J. D. Cressler, and J. Laskar, “The analysis of UWB SiGe HBT LNAfor its noise, linearity, and minimum group delay

Page 4: [IEEE 2012 IEEE 9th International Multi-Conference on Systems, Signals and Devices (SSD) - Chemnitz, Germany (2012.03.20-2012.03.23)] International Multi-Conference on Systems, Sygnals

variation,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 4, pp. 1687–1697, Apr. 2006.

[3] C. Y. Cha and S. G. Lee, “A low power, high gain LNA topology,” inIEEE Int. Microw. MillimeterWave Technol. Conf., 2005, pp. 420–42

[4] Q. Li and Y. P. Zhang, “A 1.5 V 2–9.6 GHz inductorless low-noise

amplifier in 0.13 �m CMOS,” IEEE Trans. Mircrow. Theory Tech., vol. 55, no. 10, pp. 2015–2023, Oct. 2007

[5] Y. Park, C. H. Lee, J. D. Cressler, and J. Laskar, "Theoretical Analysis of a Low Dispersion SiGe LNA for Ultra-wideband Applications," IEEE Microwave and Wireless Components Letters, vol. 16, no. 9, pp. 517-519, Sept. 2006.

[6] Y. Lu, K. S. Yeo, A. Cabuk, J. Ma, M. A. Do, and Z. Lu, "A Novel CMOS Low Noise Amplifier Design for 3.1-to-10.6-GHz Ultra-wide-band Wireless Receiver," IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 53, no. 8, pp. 1683-1692, Aug. 2006.

[7] T. Wang, H. C. Chen, H. W. Chiu, Y. S. Lin, G. W. Huang, and S. S. Lu, "Micromachined CMOS LNA and VCO by CMOS Compatible ICP Deep Trench Technology," IEEE Trans. on Microwave Theory and Techniques, vol. 54, no. 2, pp. 580-588, 2006..

[8] Y.Sheng Lin and C.Z. Chen, “Analysis and Design of a CMOS UWB LNA With Dual-RLC-Branch Wideband Input Matching Network,” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 2, FEBRUARY 2010

[9] H. Y. Yang, Y. S. Lin, and C. C. Chen, “2.5 dB NF 3.1–10.6 GHz CMOS UWB LNA with small group-delay variation,” IET Electron. Lett., vol. 44, no. 8, pp. 528–529, 2008