A 0.8-11GHz 0.15µm pHEMT Reconfigurable LowPower Consumption Distributed Low Noise

Amplifier for Wireless Home NetworksLiang Zhou, Cedric Duperrier, Sebastien Quintanel, Sofiane Aloui, Emmanuelle Bourdel, Member, IEEE

ETIS Laboratory – ENSEA/University of Cergy-Pontoise/UMR CNRS 80516, avenue du Ponceau 95014 Cergy-Pontoise, FRANCE

Email: liang.zhou@ensea.fr

Abstract—A design methodology of reconfigurable distributedlow noise amplifier (RDLNA) dedicated for wireless home com-munications operating from 0.8GHz to 11GHz is presented inthis paper. This RDLNA is suitable to operate in two differentoperation modes: low power consumption mode and high per-formance mode. The used technology is 0.15µm InGaAs ActiveLayer pHEMT Process provided by TRIQUINT. The circuit iscomposed of six unit gain cells. Each cell is mounted in cascodetopology. The design and the simulation results are detailed andcommented. In low power consumption mode, the RDLNA has again of 14.0±0.3dB, a noise figure (NF ) of 2.4dB on average anda power consumption of 15.4mW (1.0V ). In high performancemode, it demonstrates a gain of 19.8 ± 0.2dB, a NF of 1.7dBon average and a power consumption of 94.0mW (2.0V ).

Index Terms—Low noise amplifier (LNA), distributed amplifier(DA), variable gain, broadband, low power consumption, lowpower consumption mode, high performance mode.

I. INTRODUCTION

Nowadays, most of home networks are wireless. The rapiddevelopment of wireless communication demands a high levelof integration and a high degree of flexibility to adapt the needsof both the multi-standards and an optimal power management.The design of the low noise amplifier (LNA) is a key elementin the implementation of radio frequency receivers. There areseveral common goals: a low power consumption, a goodinput/output matching networks (<-10dB), an extremely flatgain (>10dB), a low noise factor, a good linearity and anunconditional stability across a wide range of frequencies from0.8GHz to 11GHz. In broadband low noise amplifiers, thereexists a fundamental tradeoff between low noise and productgain-bandwidth (GBW ). For low power broadband wirelesshome networks application, we make a tradeoff between theNoise Figure (NF ), GBW , gain’s flatness, linearity andpower consumption Pdc.

Several broadband LNA architectures are reported in lit-erature: Active Feedback [2], Resistive feedback [4], FilterMatching [5], Noise Canceling [7] and Distributed Amplifier(DA) [11]. However, some of them achieve a broad bandwidthat the expense of their gain and most of them can’t providethe gain control function except the circuit described in [11].

The drawback of DA is its high power consumption dueto the large number of components. Besides, it is difficultfor a DA to maintain a flat gain over a wide bandwidth for

various gain levels. For a distributed amplifier, the gain canbe controlled by the bias voltage. Hence, the input/outputcharacteristic impedances of the artificial transmission linesare modified. This causes the load mismatch at both input andoutput terminations.

In this paper, a method for designing RDLNA is proposed.A six stages distributed amplifier with two operation modes ispresented. The main objective is to reduce power consumptionin DA. The two modes are low power consumption modeand high performance mode. As shown in Fig.1, the DAoperates in a low power consumption mode (consumptionoptimization) in normal circumstance. When the networkrequires better reception and therefore better performance, theRDLNA switches to high performance mode (performanceoptimization). This mode consist of two operating points:1) High Gain Operating Point (HGOP) and 2) High Gainand Boosted Linearity Operating Point (HGBLOP). While thereception system needs only an enhanced gain to receive thesignals from distant or misguided, the DA operates in highgain operating point. While the reception system suffer froma distortion at the same time, more power consumption iscontributed to obtain high gain and boosted linearity operatingpoint.

Figure 1: Two operation modes and their desired performance

This paper is organized as follows: Section II studies propertiesof distributed amplifier and the design methodology. SectionIII describes the reconfigurability of the device. Section IVdetails the final design and then shows the simulation results.Finally, section V draws conclusions and future work.

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II. DESIGN AND METHODOLOGY FOR THE LOW POWERLOW NOISE AMPLIFIER

This design focuses on realizing a reconfigurable DLNA.The first target is to achieve the best performance. Then,the polarization is reduced to carry out a power optimiza-tion mode. As discussed before, when polarization changes,amplifier will have the load mismatch at terminations. Thiscauses the gain variation. In this part, the method maintainingreconfigurable constant gain is proposed.

A. Principle of distributed amplifier

The concept of distributed amplification depicted in Fig. 2is based on combining the input and output capacitances (Cg ,Cd) of the active devices with inductors in such way that twoartificial transmission lines are obtained. The lines are coupledby the transconductance gm of each identical elementary gaincell consisted of active devices. If the phase velocities onboth input and output lines are identical (ABD = ACD),the RF signal applied to the input port will be amplified byeach elementary gain cell and will be added in the forwarddirection on the output line.

Figure 2: Principle Scheme of a distributed amplifier

In lossless case: Rg = 0 and Rd = 0 , the characteristicimpedances of each lines are given by:

Z0g =

√Lg

CgZ0d =

√Ld

Cd(1)

The cutoff frequencies of each lines equal to:

fg =1

π√LgCg

fd =1

π√LdCd

(2)

The bandwidth depends on the cutoff frequency. The goodinput/output adaptation (<-10dB) can’t be achieved for fre-quencies above 86% of the cutoff frequency [9].

Having the same characteristic impedances and the cutofffrequencies, the capacitance and inductance on both the drainand gate lines should be the same. For a field-effect transistor(FET), Cg is bigger than Cd, hence a capacitor Cadd is addedin shunt to the drain to make the capacitance equal.

B. Theoretical analysis

Analysis of distributed amplifiers is facilitated by the as-sumption of lossless transmission networks and unilateralactive devices.

1) Gain: With equal phase velocities β, expression ofpower gain is:

Gp = n2 gm2<(Zd)<(Zg)

(1 + cosβ)2(3)

The factor n is the number of elementary gain cell.2) Noise: The Noise Factor NF is close to the Minimum

Noise Factor NFmin for DAs. The DA’s minimum noise figureNFmin is [10], [8]:

Nfmin∼= 1+2

"Rn(

Gg

n+ Gcor) +

rRn(

Gg

n+ Gn) + Rn

2(Gg

n+ Gcor)2

#(4)

Rn, Gn, Ycor correspond to the noise resistance, the noiseconductance and the correlation admittance of each elementarygain cell respectively . Gcord is the real part of Ycord andGg= 1

Rg.

3) Consumption: The drain’s power contribution is themajor source of the DA’s consumption Pdc, which is:

Pdc =n∑

i=1

VdiIdi (5)

Vdi is the tension of ith elementary gain cell and Idi is thecurrent of ith elementary gain cell.

C. Topology

A single transistor can’t satisfy our constraints. Hence, acascode configuration consisting of a common-source transis-tor first stage followed by a common-gate transistor secondstage is used for a DA elementary gain cell. In the gateartificial line, the amplifier does not suffer from Miller effects.The impact of Miller effect on DA performance are:

1) more ripple in the gain,2) less bandwidth3) less isolation (higher S12)

In the drain artificial line, the output impedance of the cascodestructure is decreased at high frequency, which compensatesthe loss of the line and improve the gain [6].

In a lossless system, increasing the number of stages canget higher gain and better noise factor (Eq.(3), (4)). However,the system suffers losses of the active devices and attenuationof transmission lines.The number of stages used in the state ofart is around 4 [3]. Considering that the loss in GaAs PHEMTis much lower than that in silicon technology due to the highresistivity of the substrate, we use 6 elementary gain cells toget better tradeoff between performance and consumption.

III. RECONFIGURABILITY

First, a high gain operating point of the high performancemode is designed. Then we increase the drain’s bias Vd

which improves linearity to have a high gain boosted linearityoperating point achievement. As shown in Figure3, the changeof the bias Vd has few influence to the parameter S21 as ameasure of gain and the noise factor.

Vg=-0.7V,Vd :

1.0V1.5V2.0V2.5V3.0V

Figure 3: Performance in terms of Vd

The transition from the high performance mode to lowconsumption mode is realized by reducing bias thanks to thefollowing priorities: For each elementary gain cell,• transconductance gm varies proportionally with the bias

which allows to obtain a variable power gain,• the elements that modeling the structure elementary

varies slightly with the frequency of each mode.The decrease of bias results in several changes in cascodestructure presented as follows:

1) change of the difference between the capacitances of Cg ,Cd that causes an inequality of phase velocities,

2) augmentation of the Miller capacitance,3) decrease of the transconductance gm.

In order to improve the performance especially the gain’sflatness in low consumption mode, Some parameters need tobe adjusted.

IV. TWO OPERATING MODES AND RESULTS

The proposed RDLNA is designed with 0.15µm InGaAsActive Layer pHEMT Process provided by TRIQUINT. Thefinal circuit design is plotted in Fig.4. MRIND inductor (Mi-crostrip Rectangular Spiral Inductor), precision NiCr resistorsand high value MIM capacitors are used allowing higher levelsof integration, while maintaining smaller, cost effective diesizes. The dimension of transistors are choose to be 4x50µmfor Q1 and 6x50µm for Q2. The input capacitance Cg ofcascode structure is almost equal to that of the first stagetransistor. A smaller input capacitance facilitates identifyingthe phase velocities. That’s the reason the transistor Q1 hasa smaller dimension. We set the characteristic impedances ofthe input line and output line more than 50Ω to get betterperformance [1].

In high performance mode, we set identity gate bias Vgs forboth transistors of the cascode structure. In low consumptionmode, we reduce both drain and gate bias Vds and Vgs toturn down Pdc. As discussed before, this will cause ripple ingain’s curve, mainly a drop in high frequency. To overcomethis drawback, we have serval feasible options:

1) adjust the capacitance Cadd, the decrement of this capac-itance will enhance drain line characteristic impedance,then the gain.

2) set single gate bias at gate artificial transmission line,3) modify the gate bias for Q1 and Q2 separately.

For the first proposition, we need to obtain a varicap realizedby either an inverse diode or a transistor. But this willbring extra power consumption. The last two propositionsdifferentiate the bias for transistors Q1 and Q2. A single gatebias simplifies the circuit and reduces the die size. It imposesthat the gate bias of transistor Q2 to be the same value withthe drain bias of transistor Q1. This constraint will limit a highgain’s realization in high performance mode. In this work, weobtain the low consumption by modifying the gate bias for Q1

and Q2 separately.The results in Fig. 5 highlight the simulated performance

for both modes. When polarization increases, a better noisefactor is obtained and gain varies from 14dB to 20dB. whileinput and output matching networks are maintained. In lowconsumption mode it consumes 15,4mW . In high performancemode, it consumes 94.0mW for high gain operating pointand 198.0mW for high gain boosted linearity operating point.The amplifier also provides 10.5dBm of output power at a1dB gain compression point and 6.0dBm of input third orderintercept point in high performance mode, which demonstratesthe excellent performance of linearity. The amplifier is un-conditionally stable across the entire frequency band for thetwo modes. The performance of the presented amplifier are inTable I. In low consumption mode, the transistor Q2 is nearlybeen shut down.

Table I: Element values and performance for the two modes

Low consumption mode High performance modeHGOP HGBLOP

Drain bias Q1 Vds1=0.55V Vds1=1.0V Vds1=1.75VDrain bias Q2 Vds2=0.14V Vds2=1.0V Vds2=1.75VGate bias Q1 Vgs1=-0.80V Vgs1=-0.70VGate bias Q2 Vgs2=-0.74V Vgs2=-0.70VIIP3@6GHz -5.7dBm 1.0dBm 6.0dBmP1dB@6GHz -4.8dBm 5.0dBm 10.5dBm

S21 14.0± 0.3dB 19.8± 0.2dB 20.5± 0.3dBNF (on average) 2.4dB 1.7dB

Consumption 15.4mW 94.0mW 198.0mW

Figure 4: Proposed RDLNA

Figure 5: Performance of distributed amplifier:HGBLOP , HGOP - - - - -, low consumptionmode

V. CONCLUSION AND FUTURE WORK

This work proposes an innovative solution to design adistributed low noise amplifier that meets broadband, multi-standards and low power consumption criteria. The supplypower of device drives the reconfigurable performance. Anexcellent linearity and dynamic of gain are obtained. Thelow power consumption mode saves at least 84% of powerconsumption compared to that of high performance mode. Thatmeans the proposed amplifier is always under consumptionoptimization state unless the high performance is needed.

The future work focus on the conception of a signaldetecting device who tells the RDLNA how to switch fromone mode to another automatically. The layout will be sent tofabricate in April 2013.

ACKNOWLEDGMENT

This work is partially supported by the project Econhomelabeled by Systematic and funded by the French FUI (ProjectsUnique Interministerial Fund). We would like to thank LaurentProtois for his technical support.

REFERENCES

[1] Srikanth Arekapudi, Echere Iroaga, and Boris Murmann. A low-powerdistributed wide-band lna in 0.18 µm cmos. In Circuits and Systems,2005. ISCAS 2005. IEEE International Symposium on, pages 5055–5058. IEEE, 2005.

[2] A. Bharade, H. Ghyvat, D.S. Ajnar, and P. Jain. ”design of cmosbased ultra wideband low noise amplifier using active shunt feedbacktechnique”. In Multimedia, Signal Processing and CommunicationTechnologies (IMPACT), 2011 International Conference on, pages 200–203, dec. 2011.

[3] M.K. Chirala, X. Guan, C. Huynh, and C. nguyen. Design of an ultra-small distributed low-noise-amplifier for ultra-wideband applications.In Antennas and Propagation (APSURSI), 2011 IEEE InternationalSymposium on, pages 3361 –3364, july 2011.

[4] V. Diddi, K.V. Srivastava, and A. Biswas. ”a 6 mw low noise amplifierfor 3.1 to 10.6 ghz uwb application”. In Communications (NCC), 2011National Conference on, pages 1 –4, jan. 2011.

[5] A. Ismail and A.A. Abidi. ”a 3-10-ghz low-noise amplifier withwideband lc-ladder matching network”. Solid-State Circuits, IEEEJournal of, 39(12):2269 – 2277, dec. 2004.

[6] S. Kimura, Y. Imai, Y. Umeda, and T. Enoki. Loss-compensateddistributed baseband amplifier ic’s for optical transmission systems.Microwave Theory and Techniques, IEEE Transactions on, 44(10):1688–1693, oct 1996.

[7] Chih-Fan Liao and Shen-Iuan Liu. ”a broadband noise-canceling cmoslna for 3.1-10.6 ghz uwb receiver”. pages 161 – 164, sept. 2005.

[8] K.B. Niclas and B.A. Tucker. ”on noise in distributed amplifiers atmicrowave frequencies”. Microwave Theory and Techniques, IEEETransactions on, 31(8):661 –668, aug. 1983.

[9] P.H.Ladbrookr. ”mmic design: Gaas fets and hemts”. Artech House,1989.

[10] H. Rothe and W. Dahlke. ”theory of noisy fourpoles”. Proceedings ofthe IRE, 44(6):811 –818, june 1956.

[11] F. Zhang and P.R. Kinget. ”low-power programmable gain cmosdistributed lna”. Solid-State Circuits, IEEE Journal of, 41(6):1333 –1343, june 2006.